bin/ksh/c_ksh.c
207
#define PO_NL BIT(0) /* print newline */
bin/ksh/c_ksh.c
208
#define PO_EXPAND BIT(1) /* expand backslash sequences */
bin/ksh/c_ksh.c
209
#define PO_PMINUSMINUS BIT(2) /* print a -- argument */
bin/ksh/c_ksh.c
210
#define PO_HIST BIT(3) /* print to history instead of stdout */
bin/ksh/c_ksh.c
211
#define PO_COPROC BIT(4) /* printing to coprocess: block SIGPIPE */
bin/ksh/c_sh.c
727
#define TF_NOARGS BIT(0)
bin/ksh/c_sh.c
728
#define TF_NOREAL BIT(1) /* don't report real time */
bin/ksh/c_sh.c
729
#define TF_POSIX BIT(2) /* report in posix format */
bin/ksh/c_test.h
34
#define TEF_ERROR BIT(0) /* set if we've hit an error */
bin/ksh/c_test.h
35
#define TEF_DBRACKET BIT(1) /* set if [[ .. ]] test */
bin/ksh/edit.h
36
#define XCF_COMMAND BIT(0) /* Do command completion */
bin/ksh/edit.h
37
#define XCF_FILE BIT(1) /* Do file completion */
bin/ksh/edit.h
38
#define XCF_FULLPATH BIT(2) /* command completion: store full path */
bin/ksh/eval.c
1001
#define GF_EXCHECK BIT(0) /* do existence check on file */
bin/ksh/eval.c
1002
#define GF_GLOBBED BIT(1) /* some globbing has been done */
bin/ksh/eval.c
1003
#define GF_MARKDIR BIT(2) /* add trailing / to directories */
bin/ksh/lex.h
46
#define SF_ECHO BIT(0) /* echo input to shlout */
bin/ksh/lex.h
47
#define SF_ALIAS BIT(1) /* faking space at end of alias */
bin/ksh/lex.h
48
#define SF_ALIASEND BIT(2) /* faking space at end of alias */
bin/ksh/lex.h
49
#define SF_TTY BIT(3) /* type == SSTDIN & it is a tty */
bin/ksh/lex.h
88
#define CONTIN BIT(0) /* skip new lines to complete command */
bin/ksh/lex.h
89
#define ONEWORD BIT(1) /* single word for substitute() */
bin/ksh/lex.h
90
#define ALIAS BIT(2) /* recognize alias */
bin/ksh/lex.h
91
#define KEYWORD BIT(3) /* recognize keywords */
bin/ksh/lex.h
92
#define LETEXPR BIT(4) /* get expression inside (( )) */
bin/ksh/lex.h
93
#define VARASN BIT(5) /* check for var=word */
bin/ksh/lex.h
94
#define ARRAYVAR BIT(6) /* parse x[1 & 2] as one word */
bin/ksh/lex.h
95
#define ESACONLY BIT(7) /* only accept esac keyword */
bin/ksh/lex.h
96
#define CMDWORD BIT(8) /* parsing simple command (alias related) */
bin/ksh/lex.h
97
#define HEREDELIM BIT(9) /* parsing <<,<<- delimiter */
bin/ksh/lex.h
98
#define HEREDOC BIT(10) /* parsing heredoc */
bin/ksh/lex.h
99
#define UNESCAPE BIT(11) /* remove backslashes */
bin/ksh/sh.h
225
#define TF_SHELL_USES BIT(0) /* shell uses signal, user can't change */
bin/ksh/sh.h
226
#define TF_USER_SET BIT(1) /* user has (tried to) set trap */
bin/ksh/sh.h
227
#define TF_ORIG_IGN BIT(2) /* original action was SIG_IGN */
bin/ksh/sh.h
228
#define TF_ORIG_DFL BIT(3) /* original action was SIG_DFL */
bin/ksh/sh.h
229
#define TF_EXEC_IGN BIT(4) /* restore SIG_IGN just before exec */
bin/ksh/sh.h
230
#define TF_EXEC_DFL BIT(5) /* restore SIG_DFL just before exec */
bin/ksh/sh.h
231
#define TF_DFL_INTR BIT(6) /* when received, default action is LINTR */
bin/ksh/sh.h
232
#define TF_TTY_INTR BIT(7) /* tty generated signal (see j_waitj) */
bin/ksh/sh.h
233
#define TF_CHANGED BIT(8) /* used by runtrap() to detect trap changes */
bin/ksh/sh.h
234
#define TF_FATAL BIT(9) /* causes termination if not trapped */
bin/ksh/sh.h
242
#define SS_FORCE BIT(3) /* set signal even if original signal ignored */
bin/ksh/sh.h
243
#define SS_USER BIT(4) /* user is doing the set (ie, trap command) */
bin/ksh/sh.h
244
#define SS_SHTRAP BIT(5) /* trap for internal use (CHLD,ALRM,WINCH) */
bin/ksh/sh.h
273
#define C_ALPHA BIT(0) /* a-z_A-Z */
bin/ksh/sh.h
275
#define C_LEX1 BIT(2) /* \0 \t\n|&;<>() */
bin/ksh/sh.h
276
#define C_VAR1 BIT(3) /* *@#!$-? */
bin/ksh/sh.h
277
#define C_IFSWS BIT(4) /* \t \n (IFS white space) */
bin/ksh/sh.h
278
#define C_SUBOP1 BIT(5) /* "=-+?" */
bin/ksh/sh.h
279
#define C_SUBOP2 BIT(6) /* "#%" */
bin/ksh/sh.h
280
#define C_IFS BIT(7) /* $IFS */
bin/ksh/sh.h
281
#define C_QUOTE BIT(8) /* \n\t"#$&'()*;<>?[\`| (needing quoting) */
bin/ksh/sh.h
295
#define GF_ERROR BIT(0) /* call errorf() if there is an error */
bin/ksh/sh.h
296
#define GF_PLUSOPT BIT(1) /* allow +c as an option */
bin/ksh/sh.h
297
#define GF_NONAME BIT(2) /* don't print argv[0] in errors */
bin/ksh/sh.h
300
#define GI_MINUS BIT(0) /* an option started with -... */
bin/ksh/sh.h
301
#define GI_PLUS BIT(1) /* an option started with +... */
bin/ksh/sh.h
302
#define GI_MINUSMINUS BIT(2) /* arguments were ended with -- */
bin/ksh/sh.h
96
#define EF_FUNC_PARSE BIT(0) /* function being parsed */
bin/ksh/sh.h
97
#define EF_BRKCONT_PASS BIT(1) /* set if E_LOOP must pass break/continue on */
bin/ksh/sh.h
98
#define EF_FAKE_SIGDIE BIT(2) /* hack to get info from unwind to quitenv */
bin/ksh/table.h
129
#define BF_DOGETOPTS BIT(0) /* save/restore getopts state */
bin/ksh/table.h
39
#define ALLOC BIT(0) /* val.s has been allocated */
bin/ksh/table.h
40
#define DEFINED BIT(1) /* is defined in block */
bin/ksh/table.h
41
#define ISSET BIT(2) /* has value, vp->val.[si] */
bin/ksh/table.h
42
#define EXPORT BIT(3) /* exported variable/function */
bin/ksh/table.h
43
#define TRACE BIT(4) /* var: user flagged, func: execution tracing */
bin/ksh/table.h
46
#define SPECIAL BIT(8) /* PATH, IFS, SECONDS, etc */
bin/ksh/table.h
47
#define INTEGER BIT(9) /* val.i contains integer value */
bin/ksh/table.h
48
#define RDONLY BIT(10) /* read-only variable */
bin/ksh/table.h
49
#define LOCAL BIT(11) /* for local typeset() */
bin/ksh/table.h
50
#define ARRAY BIT(13) /* array */
bin/ksh/table.h
51
#define LJUST BIT(14) /* left justify */
bin/ksh/table.h
52
#define RJUST BIT(15) /* right justify */
bin/ksh/table.h
53
#define ZEROFIL BIT(16) /* 0 filled if RJUSTIFY, strip 0s if LJUSTIFY */
bin/ksh/table.h
54
#define LCASEV BIT(17) /* convert to lower case */
bin/ksh/table.h
55
#define UCASEV_AL BIT(18)/* convert to upper case / autoload function */
bin/ksh/table.h
56
#define INT_U BIT(19) /* unsigned integer */
bin/ksh/table.h
57
#define INT_L BIT(20) /* long integer (no-op) */
bin/ksh/table.h
58
#define IMPORT BIT(21) /* flag to typeset(): no arrays, must have = */
bin/ksh/table.h
59
#define LOCAL_COPY BIT(22) /* with LOCAL - copy attrs from existing var */
bin/ksh/table.h
60
#define EXPRINEVAL BIT(23) /* contents currently being evaluated */
bin/ksh/table.h
61
#define EXPRLVALUE BIT(24) /* useable as lvalue (temp flag) */
bin/ksh/table.h
63
#define KEEPASN BIT(8) /* keep command assignments (eg, var=x cmd) */
bin/ksh/table.h
64
#define FINUSE BIT(9) /* function being executed */
bin/ksh/table.h
65
#define FDELETE BIT(10) /* function deleted while it was executing */
bin/ksh/table.h
66
#define FKSH BIT(11) /* function defined with function x (vs x()) */
bin/ksh/table.h
67
#define SPEC_BI BIT(12) /* a POSIX special builtin */
bin/ksh/table.h
68
#define REG_BI BIT(13) /* a POSIX regular builtin */
bin/ksh/table.h
85
#define FC_SPECBI BIT(0) /* special builtin */
bin/ksh/table.h
86
#define FC_FUNC BIT(1) /* function builtin */
bin/ksh/table.h
87
#define FC_REGBI BIT(2) /* regular builtin */
bin/ksh/table.h
88
#define FC_UNREGBI BIT(3) /* un-regular builtin (!special,!regular) */
bin/ksh/table.h
90
#define FC_PATH BIT(4) /* do path search */
bin/ksh/table.h
91
#define FC_DEFPATH BIT(5) /* use default path in path search */
bin/ksh/tree.h
100
#define XPIPEI BIT(3) /* input is pipe */
bin/ksh/tree.h
101
#define XPIPEO BIT(4) /* output is pipe */
bin/ksh/tree.h
103
#define XXCOM BIT(5) /* `...` command */
bin/ksh/tree.h
104
#define XPCLOSE BIT(6) /* exchild: close close_fd in parent */
bin/ksh/tree.h
105
#define XCCLOSE BIT(7) /* exchild: close close_fd in child */
bin/ksh/tree.h
106
#define XERROK BIT(8) /* non-zero exit ok (for set -e) */
bin/ksh/tree.h
107
#define XCOPROC BIT(9) /* starting a co-process */
bin/ksh/tree.h
108
#define XTIME BIT(10) /* timing TCOM command */
bin/ksh/tree.h
114
#define DOBLANK BIT(0) /* perform blank interpretation */
bin/ksh/tree.h
115
#define DOGLOB BIT(1) /* expand [?* */
bin/ksh/tree.h
116
#define DOPAT BIT(2) /* quote *?[ */
bin/ksh/tree.h
117
#define DOTILDE BIT(3) /* normal ~ expansion (first char) */
bin/ksh/tree.h
118
#define DONTRUNCOMMAND BIT(4) /* do not run $(command) things */
bin/ksh/tree.h
119
#define DOASNTILDE BIT(5) /* assignment ~ expansion (after =, :) */
bin/ksh/tree.h
120
#define DOBRACE_ BIT(6) /* used by expand(): do brace expansion */
bin/ksh/tree.h
121
#define DOMAGIC_ BIT(7) /* used by expand(): string contains MAGIC */
bin/ksh/tree.h
122
#define DOTEMP_ BIT(8) /* ditto : in word part of ${..[%#=?]..} */
bin/ksh/tree.h
123
#define DOVACHECK BIT(9) /* var assign check (for typeset, set, etc) */
bin/ksh/tree.h
124
#define DOMARKDIRS BIT(10) /* force markdirs behaviour */
bin/ksh/tree.h
90
#define IOEVAL BIT(4) /* expand in << */
bin/ksh/tree.h
91
#define IOSKIP BIT(5) /* <<-, skip ^\t* */
bin/ksh/tree.h
92
#define IOCLOB BIT(6) /* >|, override -o noclobber */
bin/ksh/tree.h
93
#define IORDUP BIT(7) /* x<&y (as opposed to x>&y) */
bin/ksh/tree.h
94
#define IONAMEXP BIT(8) /* name has been expanded */
bin/ksh/tree.h
97
#define XEXEC BIT(0) /* execute without forking */
bin/ksh/tree.h
98
#define XFORK BIT(1) /* fork before executing */
bin/ksh/tree.h
99
#define XBGND BIT(2) /* command & */
sys/dev/fdt/if_mvpp.c
3534
if (!(enable & BIT(i)))
sys/dev/fdt/if_mvpp.c
3537
if (bits & BIT(i))
sys/dev/fdt/if_mvpp.c
3538
pe->tcam.byte[ai_idx] |= BIT(i);
sys/dev/fdt/if_mvpp.c
3540
pe->tcam.byte[ai_idx] &= ~BIT(i);
sys/dev/fdt/if_mvpp.c
3593
if (!(mask & BIT(i)))
sys/dev/fdt/if_mvpp.c
3596
if (bits & BIT(i))
sys/dev/fdt/if_mvpp.c
3619
if (!(mask & BIT(i)))
sys/dev/fdt/if_mvpp.c
3622
if (bits & BIT(i))
sys/dev/fdt/if_mvpp.c
4395
tid = mvpp2_prs_mac_da_range_find(sc, BIT(port->sc_id), da, mask,
sys/dev/fdt/if_mvppreg.h
108
#define MVPP2_PRS_TCAM_INV_MASK BIT(31)
sys/dev/fdt/if_mvppreg.h
1094
#define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3))
sys/dev/fdt/if_mvppreg.h
1095
#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
sys/dev/fdt/if_mvppreg.h
1096
#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
sys/dev/fdt/if_mvppreg.h
1097
#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
sys/dev/fdt/if_mvppreg.h
1099
#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
sys/dev/fdt/if_mvppreg.h
1101
#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
sys/dev/fdt/if_mvppreg.h
1102
#define MVPP2_PRS_RI_L2_MCAST BIT(9)
sys/dev/fdt/if_mvppreg.h
1103
#define MVPP2_PRS_RI_L2_BCAST BIT(10)
sys/dev/fdt/if_mvppreg.h
1106
#define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14))
sys/dev/fdt/if_mvppreg.h
1107
#define MVPP2_PRS_RI_L3_IP4 BIT(12)
sys/dev/fdt/if_mvppreg.h
1108
#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
sys/dev/fdt/if_mvppreg.h
1109
#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
sys/dev/fdt/if_mvppreg.h
1110
#define MVPP2_PRS_RI_L3_IP6 BIT(14)
sys/dev/fdt/if_mvppreg.h
1111
#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
sys/dev/fdt/if_mvppreg.h
1112
#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
sys/dev/fdt/if_mvppreg.h
1114
#define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16))
sys/dev/fdt/if_mvppreg.h
1115
#define MVPP2_PRS_RI_L3_MCAST BIT(15)
sys/dev/fdt/if_mvppreg.h
1116
#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
sys/dev/fdt/if_mvppreg.h
1119
#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
sys/dev/fdt/if_mvppreg.h
112
#define MVPP2_PRS_TCAM_EN_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
1121
#define MVPP2_PRS_RI_L4_TCP BIT(22)
sys/dev/fdt/if_mvppreg.h
1122
#define MVPP2_PRS_RI_L4_UDP BIT(23)
sys/dev/fdt/if_mvppreg.h
1123
#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
sys/dev/fdt/if_mvppreg.h
1125
#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
sys/dev/fdt/if_mvppreg.h
1129
#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
sys/dev/fdt/if_mvppreg.h
1130
#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
sys/dev/fdt/if_mvppreg.h
1131
#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
sys/dev/fdt/if_mvppreg.h
1132
#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
sys/dev/fdt/if_mvppreg.h
1133
#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
sys/dev/fdt/if_mvppreg.h
1134
#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
sys/dev/fdt/if_mvppreg.h
1136
#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
sys/dev/fdt/if_mvppreg.h
116
#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
1179
#define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
sys/dev/fdt/if_mvppreg.h
1180
#define MVPP2_TXD_L4_CSUM_NOT BIT(14)
sys/dev/fdt/if_mvppreg.h
1181
#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
sys/dev/fdt/if_mvppreg.h
1182
#define MVPP2_TXD_PADDING_DISABLE BIT(23)
sys/dev/fdt/if_mvppreg.h
1183
#define MVPP2_TXD_L4_UDP BIT(24)
sys/dev/fdt/if_mvppreg.h
1184
#define MVPP2_TXD_L3_IP6 BIT(26)
sys/dev/fdt/if_mvppreg.h
1185
#define MVPP2_TXD_L_DESC BIT(28)
sys/dev/fdt/if_mvppreg.h
1186
#define MVPP2_TXD_F_DESC BIT(29)
sys/dev/fdt/if_mvppreg.h
1188
#define MVPP2_RXD_ERR_SUMMARY BIT(15)
sys/dev/fdt/if_mvppreg.h
1189
#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
sys/dev/fdt/if_mvppreg.h
1191
#define MVPP2_RXD_ERR_OVERRUN BIT(13)
sys/dev/fdt/if_mvppreg.h
1192
#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
sys/dev/fdt/if_mvppreg.h
1194
#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
sys/dev/fdt/if_mvppreg.h
1195
#define MVPP2_RXD_HWF_SYNC BIT(21)
sys/dev/fdt/if_mvppreg.h
1196
#define MVPP2_RXD_L4_CSUM_OK BIT(22)
sys/dev/fdt/if_mvppreg.h
1197
#define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
sys/dev/fdt/if_mvppreg.h
1198
#define MVPP2_RXD_L4_TCP BIT(25)
sys/dev/fdt/if_mvppreg.h
1199
#define MVPP2_RXD_L4_UDP BIT(26)
sys/dev/fdt/if_mvppreg.h
1200
#define MVPP2_RXD_L3_IP4 BIT(28)
sys/dev/fdt/if_mvppreg.h
1201
#define MVPP2_RXD_L3_IP6 BIT(30)
sys/dev/fdt/if_mvppreg.h
1202
#define MVPP2_RXD_BUF_HDR BIT(31)
sys/dev/fdt/if_mvppreg.h
123
#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
sys/dev/fdt/if_mvppreg.h
1279
#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
sys/dev/fdt/if_mvppreg.h
165
#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
sys/dev/fdt/if_mvppreg.h
166
#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
sys/dev/fdt/if_mvppreg.h
168
#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
sys/dev/fdt/if_mvppreg.h
236
#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
sys/dev/fdt/if_mvppreg.h
237
#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
sys/dev/fdt/if_mvppreg.h
238
#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
sys/dev/fdt/if_mvppreg.h
239
#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
sys/dev/fdt/if_mvppreg.h
240
#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
sys/dev/fdt/if_mvppreg.h
241
#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
sys/dev/fdt/if_mvppreg.h
246
#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
sys/dev/fdt/if_mvppreg.h
261
#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
sys/dev/fdt/if_mvppreg.h
263
#define MVPP2_BM_START_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
264
#define MVPP2_BM_STOP_MASK BIT(1)
sys/dev/fdt/if_mvppreg.h
265
#define MVPP2_BM_STATE_MASK BIT(4)
sys/dev/fdt/if_mvppreg.h
275
#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
276
#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
sys/dev/fdt/if_mvppreg.h
277
#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
sys/dev/fdt/if_mvppreg.h
278
#define MVPP2_BM_BPPE_FULL_MASK BIT(3)
sys/dev/fdt/if_mvppreg.h
279
#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
sys/dev/fdt/if_mvppreg.h
282
#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
289
#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
290
#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
sys/dev/fdt/if_mvppreg.h
291
#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
sys/dev/fdt/if_mvppreg.h
335
#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
sys/dev/fdt/if_mvppreg.h
344
#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
345
#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
sys/dev/fdt/if_mvppreg.h
348
#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
sys/dev/fdt/if_mvppreg.h
350
#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
sys/dev/fdt/if_mvppreg.h
351
#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
sys/dev/fdt/if_mvppreg.h
353
#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
sys/dev/fdt/if_mvppreg.h
356
#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
357
#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
sys/dev/fdt/if_mvppreg.h
358
#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
sys/dev/fdt/if_mvppreg.h
359
#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
sys/dev/fdt/if_mvppreg.h
361
#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
sys/dev/fdt/if_mvppreg.h
362
#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
sys/dev/fdt/if_mvppreg.h
363
#define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)
sys/dev/fdt/if_mvppreg.h
364
#define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)
sys/dev/fdt/if_mvppreg.h
365
#define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4)
sys/dev/fdt/if_mvppreg.h
366
#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
sys/dev/fdt/if_mvppreg.h
367
#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
sys/dev/fdt/if_mvppreg.h
368
#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
sys/dev/fdt/if_mvppreg.h
369
#define MVPP2_GMAC_FC_ADV_EN BIT(9)
sys/dev/fdt/if_mvppreg.h
370
#define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10)
sys/dev/fdt/if_mvppreg.h
371
#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
sys/dev/fdt/if_mvppreg.h
372
#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
sys/dev/fdt/if_mvppreg.h
373
#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
sys/dev/fdt/if_mvppreg.h
381
#define MVPP2_GMAC_INT_CAUSE_LINK_CHANGE BIT(1)
sys/dev/fdt/if_mvppreg.h
384
#define MVPP2_GMAC_INT_SUM_CAUSE_LINK_CHANGE BIT(1)
sys/dev/fdt/if_mvppreg.h
388
#define MVPP2_PORT_CTRL0_PORTEN BIT(0)
sys/dev/fdt/if_mvppreg.h
389
#define MVPP2_PORT_CTRL0_PORTTYPE BIT(1)
sys/dev/fdt/if_mvppreg.h
391
#define MVPP2_PORT_CTRL0_COUNT_EN BIT(15)
sys/dev/fdt/if_mvppreg.h
395
#define MVPP2_PORT_CTRL1_EN_RX_CRC_CHECK BIT(0)
sys/dev/fdt/if_mvppreg.h
396
#define MVPP2_PORT_CTRL1_EN_PERIODIC_FC_XON BIT(1)
sys/dev/fdt/if_mvppreg.h
397
#define MVPP2_PORT_CTRL1_MGMII_MODE BIT(2)
sys/dev/fdt/if_mvppreg.h
398
#define MVPP2_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE BIT(3)
sys/dev/fdt/if_mvppreg.h
399
#define MVPP2_PORT_CTRL1_DIS_EXCESSIVE_COL BIT(4)
sys/dev/fdt/if_mvppreg.h
400
#define MVPP2_PORT_CTRL1_GMII_LOOPBACK BIT(5)
sys/dev/fdt/if_mvppreg.h
401
#define MVPP2_PORT_CTRL1_PCS_LOOPBACK BIT(6)
sys/dev/fdt/if_mvppreg.h
403
#define MVPP2_PORT_CTRL1_EN_SHORT_PREAMBLE BIT(15)
sys/dev/fdt/if_mvppreg.h
407
#define MVPP2_PORT_CTRL2_SGMII_MODE BIT(0)
sys/dev/fdt/if_mvppreg.h
409
#define MVPP2_PORT_CTRL2_PCS_EN BIT(3)
sys/dev/fdt/if_mvppreg.h
410
#define MVPP2_PORT_CTRL2_RGMII_MODE BIT(4)
sys/dev/fdt/if_mvppreg.h
411
#define MVPP2_PORT_CTRL2_DIS_PADING BIT(5)
sys/dev/fdt/if_mvppreg.h
412
#define MVPP2_PORT_CTRL2_PORTMACRESET BIT(6)
sys/dev/fdt/if_mvppreg.h
413
#define MVPP2_PORT_CTRL2_TX_DRAIN BIT(7)
sys/dev/fdt/if_mvppreg.h
414
#define MVPP2_PORT_CTRL2_EN_MII_ODD_PRE BIT(8)
sys/dev/fdt/if_mvppreg.h
415
#define MVPP2_PORT_CTRL2_CLK_125_BYPS_EN BIT(9)
sys/dev/fdt/if_mvppreg.h
416
#define MVPP2_PORT_CTRL2_PRBS_CHECK_EN BIT(10)
sys/dev/fdt/if_mvppreg.h
417
#define MVPP2_PORT_CTRL2_PRBS_GEN_EN BIT(11)
sys/dev/fdt/if_mvppreg.h
419
#define MVPP2_PORT_CTRL2_EN_COL_ON_BP BIT(14)
sys/dev/fdt/if_mvppreg.h
420
#define MVPP2_PORT_CTRL2_EARLY_REJECT_MODE BIT(15)
sys/dev/fdt/if_mvppreg.h
424
#define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN BIT(0)
sys/dev/fdt/if_mvppreg.h
425
#define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP BIT(1)
sys/dev/fdt/if_mvppreg.h
426
#define MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN BIT(2)
sys/dev/fdt/if_mvppreg.h
427
#define MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN BIT(3)
sys/dev/fdt/if_mvppreg.h
428
#define MVPP2_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN BIT(4)
sys/dev/fdt/if_mvppreg.h
429
#define MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED BIT(5)
sys/dev/fdt/if_mvppreg.h
430
#define MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED BIT(6)
sys/dev/fdt/if_mvppreg.h
431
#define MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED BIT(7)
sys/dev/fdt/if_mvppreg.h
432
#define MVPP2_PORT_AUTO_NEG_CFG_ADV_PAUSE BIT(9)
sys/dev/fdt/if_mvppreg.h
433
#define MVPP2_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE BIT(10)
sys/dev/fdt/if_mvppreg.h
434
#define MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN BIT(11)
sys/dev/fdt/if_mvppreg.h
435
#define MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX BIT(12)
sys/dev/fdt/if_mvppreg.h
436
#define MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN BIT(13)
sys/dev/fdt/if_mvppreg.h
437
#define MVPP2_PORT_AUTO_NEG_CFG_PHY_MODE BIT(14)
sys/dev/fdt/if_mvppreg.h
438
#define MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
sys/dev/fdt/if_mvppreg.h
442
#define MVPP2_PORT_STATUS0_LINKUP BIT(0)
sys/dev/fdt/if_mvppreg.h
443
#define MVPP2_PORT_STATUS0_GMIISPEED BIT(1)
sys/dev/fdt/if_mvppreg.h
444
#define MVPP2_PORT_STATUS0_MIISPEED BIT(2)
sys/dev/fdt/if_mvppreg.h
445
#define MVPP2_PORT_STATUS0_FULLDX BIT(3)
sys/dev/fdt/if_mvppreg.h
446
#define MVPP2_PORT_STATUS0_RXFCEN BIT(4)
sys/dev/fdt/if_mvppreg.h
447
#define MVPP2_PORT_STATUS0_TXFCEN BIT(5)
sys/dev/fdt/if_mvppreg.h
448
#define MVPP2_PORT_STATUS0_PORTRXPAUSE BIT(6)
sys/dev/fdt/if_mvppreg.h
449
#define MVPP2_PORT_STATUS0_PORTTXPAUSE BIT(7)
sys/dev/fdt/if_mvppreg.h
450
#define MVPP2_PORT_STATUS0_PORTIS_DOINGPRESSURE BIT(8)
sys/dev/fdt/if_mvppreg.h
451
#define MVPP2_PORT_STATUS0_PORTBUFFULL BIT(9)
sys/dev/fdt/if_mvppreg.h
452
#define MVPP2_PORT_STATUS0_SYNCFAIL10MS BIT(10)
sys/dev/fdt/if_mvppreg.h
453
#define MVPP2_PORT_STATUS0_ANDONE BIT(11)
sys/dev/fdt/if_mvppreg.h
454
#define MVPP2_PORT_STATUS0_INBAND_AUTONEG_BYPASSAC BIT(12)
sys/dev/fdt/if_mvppreg.h
455
#define MVPP2_PORT_STATUS0_SERDESPLL_LOCKED BIT(13)
sys/dev/fdt/if_mvppreg.h
456
#define MVPP2_PORT_STATUS0_SYNCOK BIT(14)
sys/dev/fdt/if_mvppreg.h
457
#define MVPP2_PORT_STATUS0_SQUELCHNOT_DETECTED BIT(15)
sys/dev/fdt/if_mvppreg.h
461
#define MVPP2_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE BIT(0)
sys/dev/fdt/if_mvppreg.h
462
#define MVPP2_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN BIT(1)
sys/dev/fdt/if_mvppreg.h
463
#define MVPP2_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN BIT(2)
sys/dev/fdt/if_mvppreg.h
464
#define MVPP2_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN BIT(3)
sys/dev/fdt/if_mvppreg.h
465
#define MVPP2_PORT_SERIAL_PARAM_CFG_BP_EN BIT(4)
sys/dev/fdt/if_mvppreg.h
466
#define MVPP2_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN BIT(5)
sys/dev/fdt/if_mvppreg.h
468
#define MVPP2_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT BIT(12)
sys/dev/fdt/if_mvppreg.h
469
#define MVPP2_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN BIT(13)
sys/dev/fdt/if_mvppreg.h
470
#define MVPP2_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7 BIT(14)
sys/dev/fdt/if_mvppreg.h
471
#define MVPP2_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX BIT(15)
sys/dev/fdt/if_mvppreg.h
482
#define MVPP2_PORT_FIFO_CFG_1_PORT_EN_FIX_EN BIT(15)
sys/dev/fdt/if_mvppreg.h
486
#define MVPP2_PORT_SERDES_CFG0_SERDESRESET BIT(0)
sys/dev/fdt/if_mvppreg.h
487
#define MVPP2_PORT_SERDES_CFG0_PU_TX BIT(1)
sys/dev/fdt/if_mvppreg.h
488
#define MVPP2_PORT_SERDES_CFG0_PU_RX BIT(2)
sys/dev/fdt/if_mvppreg.h
489
#define MVPP2_PORT_SERDES_CFG0_PU_PLL BIT(3)
sys/dev/fdt/if_mvppreg.h
490
#define MVPP2_PORT_SERDES_CFG0_PU_IVREF BIT(4)
sys/dev/fdt/if_mvppreg.h
491
#define MVPP2_PORT_SERDES_CFG0_TESTEN BIT(5)
sys/dev/fdt/if_mvppreg.h
492
#define MVPP2_PORT_SERDES_CFG0_DPHER_EN BIT(6)
sys/dev/fdt/if_mvppreg.h
493
#define MVPP2_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE BIT(7)
sys/dev/fdt/if_mvppreg.h
494
#define MVPP2_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE BIT(8)
sys/dev/fdt/if_mvppreg.h
495
#define MVPP2_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE BIT(9)
sys/dev/fdt/if_mvppreg.h
496
#define MVPP2_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE BIT(10)
sys/dev/fdt/if_mvppreg.h
497
#define MVPP2_PORT_SERDES_CFG0_MASTER_MODE_ENABLE BIT(11)
sys/dev/fdt/if_mvppreg.h
498
#define MVPP2_PORT_SERDES_CFG0_TERM75_TX BIT(12)
sys/dev/fdt/if_mvppreg.h
499
#define MVPP2_PORT_SERDES_CFG0_OUTAMP BIT(13)
sys/dev/fdt/if_mvppreg.h
500
#define MVPP2_PORT_SERDES_CFG0_BTS712_FIX_EN BIT(14)
sys/dev/fdt/if_mvppreg.h
501
#define MVPP2_PORT_SERDES_CFG0_BTS156_FIX_EN BIT(15)
sys/dev/fdt/if_mvppreg.h
505
#define MVPP2_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL BIT(0)
sys/dev/fdt/if_mvppreg.h
506
#define MVPP2_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL BIT(1)
sys/dev/fdt/if_mvppreg.h
508
#define MVPP2_GMAC_PORT_SERDES_CFG1_VCMS BIT(4)
sys/dev/fdt/if_mvppreg.h
509
#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET BIT(5)
sys/dev/fdt/if_mvppreg.h
510
#define MVPP2_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX BIT(6)
sys/dev/fdt/if_mvppreg.h
511
#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_ENABLE BIT(7)
sys/dev/fdt/if_mvppreg.h
513
#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY BIT(13)
sys/dev/fdt/if_mvppreg.h
514
#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY BIT(14)
sys/dev/fdt/if_mvppreg.h
515
#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY BIT(15)
sys/dev/fdt/if_mvppreg.h
527
#define MVPP2_PORT_PRBS_STATUS_PRBSCHECK_LOCKED BIT(0)
sys/dev/fdt/if_mvppreg.h
528
#define MVPP2_PORT_PRBS_STATUS_PRBSCHECKRDY BIT(1)
sys/dev/fdt/if_mvppreg.h
536
#define MVPP2_PORT_STATUS1_MEDIAACTIVE BIT(0)
sys/dev/fdt/if_mvppreg.h
540
#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER BIT(0)
sys/dev/fdt/if_mvppreg.h
541
#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ BIT(1)
sys/dev/fdt/if_mvppreg.h
542
#define MVPP2_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN BIT(2)
sys/dev/fdt/if_mvppreg.h
543
#define MVPP2_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN BIT(3)
sys/dev/fdt/if_mvppreg.h
544
#define MVPP2_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE BIT(4)
sys/dev/fdt/if_mvppreg.h
545
#define MVPP2_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN BIT(5)
sys/dev/fdt/if_mvppreg.h
546
#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST BIT(6)
sys/dev/fdt/if_mvppreg.h
547
#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522 BIT(7)
sys/dev/fdt/if_mvppreg.h
553
#define MVPP2_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE BIT(15)
sys/dev/fdt/if_mvppreg.h
557
#define MVPP2_PORT_CTRL4_EXT_PIN_GMII_SEL BIT(0)
sys/dev/fdt/if_mvppreg.h
558
#define MVPP2_PORT_CTRL4_PREAMBLE_FIX BIT(1)
sys/dev/fdt/if_mvppreg.h
559
#define MVPP2_PORT_CTRL4_SQ_DETECT_FIX_EN BIT(2)
sys/dev/fdt/if_mvppreg.h
560
#define MVPP2_PORT_CTRL4_FC_EN_RX BIT(3)
sys/dev/fdt/if_mvppreg.h
561
#define MVPP2_PORT_CTRL4_FC_EN_TX BIT(4)
sys/dev/fdt/if_mvppreg.h
562
#define MVPP2_PORT_CTRL4_DP_CLK_SEL BIT(5)
sys/dev/fdt/if_mvppreg.h
563
#define MVPP2_PORT_CTRL4_SYNC_BYPASS BIT(6)
sys/dev/fdt/if_mvppreg.h
564
#define MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
sys/dev/fdt/if_mvppreg.h
565
#define MVPP2_PORT_CTRL4_COUNT_EXTERNAL_FC_EN BIT(8)
sys/dev/fdt/if_mvppreg.h
566
#define MVPP2_PORT_CTRL4_MARVELL_HEADER_EN BIT(9)
sys/dev/fdt/if_mvppreg.h
567
#define MVPP2_PORT_CTRL4_LEDS_NUMBER BIT(10)
sys/dev/fdt/if_mvppreg.h
571
#define MVPP22_SMI_POLLING_EN BIT(10)
sys/dev/fdt/if_mvppreg.h
577
#define MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK BIT(10)
sys/dev/fdt/if_mvppreg.h
579
#define MVPP22_MPCS_TX_SD_CLK_RESET BIT(0)
sys/dev/fdt/if_mvppreg.h
580
#define MVPP22_MPCS_RX_SD_CLK_RESET BIT(1)
sys/dev/fdt/if_mvppreg.h
581
#define MVPP22_MPCS_MAC_CLK_RESET BIT(2)
sys/dev/fdt/if_mvppreg.h
584
#define MVPP22_MPCS_CLK_DIV_PHASE_SET BIT(11)
sys/dev/fdt/if_mvppreg.h
588
#define MVPP22_XPCS_PCSRESET BIT(0)
sys/dev/fdt/if_mvppreg.h
596
#define GENCONF_SOFT_RESET1_GOP BIT(6)
sys/dev/fdt/if_mvppreg.h
598
#define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1)
sys/dev/fdt/if_mvppreg.h
599
#define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29)
sys/dev/fdt/if_mvppreg.h
600
#define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31)
sys/dev/fdt/if_mvppreg.h
602
#define GENCONF_PORT_CTRL1_EN(p) BIT(p)
sys/dev/fdt/if_mvppreg.h
603
#define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28)
sys/dev/fdt/if_mvppreg.h
605
#define GENCONF_CTRL0_PORT0_RGMII BIT(0)
sys/dev/fdt/if_mvppreg.h
606
#define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1)
sys/dev/fdt/if_mvppreg.h
607
#define GENCONF_CTRL0_PORT1_RGMII BIT(2)
sys/dev/fdt/if_mvppreg.h
704
#define MVPP2_F_LOOPBACK BIT(0)
sys/dev/fdt/if_mvppreg.h
708
#define SD1_CONTROL_RXAUI1_L45_EN_MASK BIT(26)
sys/dev/fdt/if_mvppreg.h
709
#define SD1_CONTROL_RXAUI0_L23_EN_MASK BIT(27)
sys/dev/fdt/if_mvppreg.h
710
#define SD1_CONTROL_XAUI_EN_MASK BIT(28)
sys/dev/fdt/if_mvppreg.h
714
#define NETC_GOP_SOFT_RESET BIT(6)
sys/dev/fdt/if_mvppreg.h
718
#define NETC_GOP_ENABLE_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
719
#define NETC_BUS_WIDTH_SELECT_MASK BIT(1)
sys/dev/fdt/if_mvppreg.h
720
#define NETC_GIG_RX_DATA_SAMPLE_MASK BIT(29)
sys/dev/fdt/if_mvppreg.h
721
#define NETC_CLK_DIV_PHASE_MASK BIT(31)
sys/dev/fdt/if_mvppreg.h
734
#define NETC_GBE_PORT0_SGMII_MODE_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
735
#define NETC_GBE_PORT1_SGMII_MODE_MASK BIT(1)
sys/dev/fdt/if_mvppreg.h
736
#define NETC_GBE_PORT1_MII_MODE_MASK BIT(2)
sys/dev/fdt/if_mvppreg.h
740
#define MV_XLG_MAC_CTRL0_PORTEN BIT(0)
sys/dev/fdt/if_mvppreg.h
741
#define MV_XLG_MAC_CTRL0_MACRESETN BIT(1)
sys/dev/fdt/if_mvppreg.h
742
#define MV_XLG_MAC_CTRL0_FORCELINKDOWN BIT(2)
sys/dev/fdt/if_mvppreg.h
743
#define MV_XLG_MAC_CTRL0_FORCELINKPASS BIT(3)
sys/dev/fdt/if_mvppreg.h
745
#define MV_XLG_MAC_CTRL0_RXFCEN BIT(7)
sys/dev/fdt/if_mvppreg.h
746
#define MV_XLG_MAC_CTRL0_TXFCEN BIT(8)
sys/dev/fdt/if_mvppreg.h
747
#define MV_XLG_MAC_CTRL0_RXCRCCHECKEN BIT(9)
sys/dev/fdt/if_mvppreg.h
748
#define MV_XLG_MAC_CTRL0_PERIODICXONEN BIT(10)
sys/dev/fdt/if_mvppreg.h
749
#define MV_XLG_MAC_CTRL0_RXCRCSTRIPEN BIT(11)
sys/dev/fdt/if_mvppreg.h
750
#define MV_XLG_MAC_CTRL0_PADDINGDIS BIT(13)
sys/dev/fdt/if_mvppreg.h
751
#define MV_XLG_MAC_CTRL0_MIBCNTDIS BIT(14)
sys/dev/fdt/if_mvppreg.h
752
#define MV_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE BIT(15)
sys/dev/fdt/if_mvppreg.h
759
#define MV_XLG_MAC_CTRL1_MACLOOPBACKEN BIT(13)
sys/dev/fdt/if_mvppreg.h
760
#define MV_XLG_MAC_CTRL1_XGMIILOOPBACKEN BIT(14)
sys/dev/fdt/if_mvppreg.h
761
#define MV_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT BIT(15)
sys/dev/fdt/if_mvppreg.h
766
#define MV_XLG_MAC_CTRL2_UNIDIRECTIONALEN BIT(8)
sys/dev/fdt/if_mvppreg.h
767
#define MV_XLG_MAC_CTRL2_FIXEDIPGBASE BIT(9)
sys/dev/fdt/if_mvppreg.h
768
#define MV_XLG_MAC_CTRL2_PERIODICXOFFEN BIT(10)
sys/dev/fdt/if_mvppreg.h
769
#define MV_XLG_MAC_CTRL2_SIMPLEXMODEEN BIT(13)
sys/dev/fdt/if_mvppreg.h
774
#define MV_XLG_MAC_PORT_STATUS_LINKSTATUS BIT(0)
sys/dev/fdt/if_mvppreg.h
775
#define MV_XLG_MAC_PORT_STATUS_REMOTEFAULT BIT(1)
sys/dev/fdt/if_mvppreg.h
776
#define MV_XLG_MAC_PORT_STATUS_LOCALFAULT BIT(2)
sys/dev/fdt/if_mvppreg.h
777
#define MV_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN BIT(3)
sys/dev/fdt/if_mvppreg.h
778
#define MV_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN BIT(4)
sys/dev/fdt/if_mvppreg.h
779
#define MV_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN BIT(5)
sys/dev/fdt/if_mvppreg.h
780
#define MV_XLG_MAC_PORT_STATUS_PORTRXPAUSE BIT(6)
sys/dev/fdt/if_mvppreg.h
781
#define MV_XLG_MAC_PORT_STATUS_PORTTXPAUSE BIT(7)
sys/dev/fdt/if_mvppreg.h
782
#define MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL BIT(8)
sys/dev/fdt/if_mvppreg.h
800
#define MV_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS BIT(0)
sys/dev/fdt/if_mvppreg.h
808
#define MV_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO BIT(0)
sys/dev/fdt/if_mvppreg.h
809
#define MV_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX BIT(1)
sys/dev/fdt/if_mvppreg.h
81
#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
sys/dev/fdt/if_mvppreg.h
810
#define MV_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX BIT(2)
sys/dev/fdt/if_mvppreg.h
811
#define MV_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX BIT(3)
sys/dev/fdt/if_mvppreg.h
812
#define MV_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT BIT(4)
sys/dev/fdt/if_mvppreg.h
813
#define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44 BIT(5)
sys/dev/fdt/if_mvppreg.h
814
#define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42 BIT(6)
sys/dev/fdt/if_mvppreg.h
815
#define MV_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX BIT(7)
sys/dev/fdt/if_mvppreg.h
816
#define MV_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX BIT(8)
sys/dev/fdt/if_mvppreg.h
822
#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER BIT(0)
sys/dev/fdt/if_mvppreg.h
823
#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD BIT(1)
sys/dev/fdt/if_mvppreg.h
824
#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN BIT(2)
sys/dev/fdt/if_mvppreg.h
825
#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN BIT(3)
sys/dev/fdt/if_mvppreg.h
826
#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE BIT(4)
sys/dev/fdt/if_mvppreg.h
828
#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST BIT(11)
sys/dev/fdt/if_mvppreg.h
829
#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522 BIT(12)
sys/dev/fdt/if_mvppreg.h
837
#define MV_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI BIT(0)
sys/dev/fdt/if_mvppreg.h
838
#define MV_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN BIT(9)
sys/dev/fdt/if_mvppreg.h
86
#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
sys/dev/fdt/if_mvppreg.h
862
#define MV_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE BIT(0)
sys/dev/fdt/if_mvppreg.h
863
#define MV_XLG_MAC_CTRL4_LED_STREAM_SELECT BIT(1)
sys/dev/fdt/if_mvppreg.h
864
#define MV_XLG_MAC_CTRL4_DEBUG_BUS_SELECT BIT(2)
sys/dev/fdt/if_mvppreg.h
865
#define MV_XLG_MAC_CTRL4_MASK_PCS_RESET BIT(3)
sys/dev/fdt/if_mvppreg.h
866
#define MV_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG BIT(4)
sys/dev/fdt/if_mvppreg.h
867
#define MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN BIT(5)
sys/dev/fdt/if_mvppreg.h
868
#define MV_XLG_MAC_CTRL4_FORWARD_PFC_EN BIT(6)
sys/dev/fdt/if_mvppreg.h
869
#define MV_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN BIT(7)
sys/dev/fdt/if_mvppreg.h
870
#define MV_XLG_MAC_CTRL4_USE_XPCS BIT(8)
sys/dev/fdt/if_mvppreg.h
871
#define MV_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT BIT(9)
sys/dev/fdt/if_mvppreg.h
873
#define MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G BIT(12)
sys/dev/fdt/if_mvppreg.h
874
#define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK BIT(14)
sys/dev/fdt/if_mvppreg.h
886
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0 BIT(0)
sys/dev/fdt/if_mvppreg.h
887
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1 BIT(1)
sys/dev/fdt/if_mvppreg.h
888
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2 BIT(2)
sys/dev/fdt/if_mvppreg.h
889
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3 BIT(3)
sys/dev/fdt/if_mvppreg.h
890
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4 BIT(4)
sys/dev/fdt/if_mvppreg.h
891
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5 BIT(5)
sys/dev/fdt/if_mvppreg.h
892
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6 BIT(6)
sys/dev/fdt/if_mvppreg.h
893
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7 BIT(7)
sys/dev/fdt/if_mvppreg.h
894
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8 BIT(8)
sys/dev/fdt/if_mvppreg.h
895
#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9 BIT(9)
sys/dev/fdt/if_mvppreg.h
896
#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_10 BIT(10)
sys/dev/fdt/if_mvppreg.h
897
#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_11 BIT(11)
sys/dev/fdt/if_mvppreg.h
898
#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_12 BIT(12)
sys/dev/fdt/if_mvppreg.h
899
#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_13 BIT(13)
sys/dev/fdt/if_mvppreg.h
900
#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_14 BIT(14)
sys/dev/fdt/if_mvppreg.h
901
#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_15 BIT(15)
sys/dev/fdt/if_mvppreg.h
905
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0 BIT(0)
sys/dev/fdt/if_mvppreg.h
906
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1 BIT(1)
sys/dev/fdt/if_mvppreg.h
907
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2 BIT(2)
sys/dev/fdt/if_mvppreg.h
908
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3 BIT(3)
sys/dev/fdt/if_mvppreg.h
909
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4 BIT(4)
sys/dev/fdt/if_mvppreg.h
910
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5 BIT(5)
sys/dev/fdt/if_mvppreg.h
911
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6 BIT(6)
sys/dev/fdt/if_mvppreg.h
912
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7 BIT(7)
sys/dev/fdt/if_mvppreg.h
913
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8 BIT(8)
sys/dev/fdt/if_mvppreg.h
914
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9 BIT(9)
sys/dev/fdt/if_mvppreg.h
915
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10 BIT(10)
sys/dev/fdt/if_mvppreg.h
916
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11 BIT(11)
sys/dev/fdt/if_mvppreg.h
917
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12 BIT(12)
sys/dev/fdt/if_mvppreg.h
918
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13 BIT(13)
sys/dev/fdt/if_mvppreg.h
919
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14 BIT(14)
sys/dev/fdt/if_mvppreg.h
920
#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15 BIT(15)
sys/dev/fdt/if_mvppreg.h
928
#define MV_XLG_SUMMARY_INTERRUPT_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
929
#define MV_XLG_INTERRUPT_LINK_CHANGE BIT(1)
sys/dev/fdt/if_mvppreg.h
93
#define MVPP2_RXQ_DISABLE_MASK BIT(31)
sys/dev/fdt/if_mvppreg.h
935
#define MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_XLG BIT(1)
sys/dev/fdt/if_mvppreg.h
936
#define MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_GIG BIT(2)
sys/dev/fdt/if_mvppreg.h
978
#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
sys/dev/fdt/if_mvppreg.h
992
#define MVPP2_PRS_CAST_MASK BIT(0)
sys/dev/fdt/if_mvppreg.h
993
#define MVPP2_PRS_MCAST_VAL BIT(0)
sys/dev/ic/atwreg.h
729
#define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */
sys/dev/ic/qwx.c
11368
BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
sys/dev/ic/qwx.c
11389
BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
sys/dev/ic/qwx.c
11567
if (wmi_svc_bm[i] & BIT(j % WMI_SERVICE_BITS_IN_SIZE32))
sys/dev/ic/qwx.c
18066
hal->avail_blk_resource |= BIT(hal->current_blk_index);
sys/dev/ic/qwx.c
18107
hal->avail_blk_resource &= ~BIT(hal->current_blk_index);
sys/dev/ic/qwx.c
2449
#define ATH11K_TX_RING_MASK_0 BIT(0)
sys/dev/ic/qwx.c
2450
#define ATH11K_TX_RING_MASK_1 BIT(1)
sys/dev/ic/qwx.c
2451
#define ATH11K_TX_RING_MASK_2 BIT(2)
sys/dev/ic/qwx.c
2452
#define ATH11K_TX_RING_MASK_3 BIT(3)
sys/dev/ic/qwx.c
2453
#define ATH11K_TX_RING_MASK_4 BIT(4)
sys/dev/ic/qwx.c
26367
if ((ic->ic_sup_mcs[i / 8] & BIT(i % 8)) &&
sys/dev/ic/qwx.c
26368
(ni->ni_rxmcs[i / 8] & BIT(i % 8))) {
sys/dev/ic/qwx.c
3676
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
3677
BIT(NL80211_IFTYPE_AP) |
sys/dev/ic/qwx.c
3678
BIT(NL80211_IFTYPE_MESH_POINT),
sys/dev/ic/qwx.c
3765
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
3766
BIT(NL80211_IFTYPE_AP) |
sys/dev/ic/qwx.c
3767
BIT(NL80211_IFTYPE_MESH_POINT),
sys/dev/ic/qwx.c
3854
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
3855
BIT(NL80211_IFTYPE_AP),
sys/dev/ic/qwx.c
3946
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
3947
BIT(NL80211_IFTYPE_AP) |
sys/dev/ic/qwx.c
3948
BIT(NL80211_IFTYPE_MESH_POINT),
sys/dev/ic/qwx.c
4035
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
4036
BIT(NL80211_IFTYPE_AP),
sys/dev/ic/qwx.c
4126
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
4127
BIT(NL80211_IFTYPE_AP),
sys/dev/ic/qwx.c
4216
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
4217
BIT(NL80211_IFTYPE_AP),
sys/dev/ic/qwx.c
4303
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
sys/dev/ic/qwx.c
4304
BIT(NL80211_IFTYPE_AP),
sys/dev/ic/qwxreg.h
10157
#define ATH11K_GLOBAL_DISABLE_CREDIT_FLOW BIT(1)
sys/dev/ic/qwxreg.h
10298
#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
sys/dev/ic/qwxreg.h
10299
#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
sys/dev/ic/qwxreg.h
10427
#define DP_RX_MPDU_ERR_FCS BIT(0)
sys/dev/ic/qwxreg.h
10428
#define DP_RX_MPDU_ERR_DECRYPT BIT(1)
sys/dev/ic/qwxreg.h
10429
#define DP_RX_MPDU_ERR_TKIP_MIC BIT(2)
sys/dev/ic/qwxreg.h
10430
#define DP_RX_MPDU_ERR_AMSDU_ERR BIT(3)
sys/dev/ic/qwxreg.h
10431
#define DP_RX_MPDU_ERR_OVERFLOW BIT(4)
sys/dev/ic/qwxreg.h
10432
#define DP_RX_MPDU_ERR_MSDU_LEN BIT(5)
sys/dev/ic/qwxreg.h
10433
#define DP_RX_MPDU_ERR_MPDU_LEN BIT(6)
sys/dev/ic/qwxreg.h
10434
#define DP_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)
sys/dev/ic/qwxreg.h
10459
#define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
sys/dev/ic/qwxreg.h
10460
#define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
sys/dev/ic/qwxreg.h
10461
#define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
sys/dev/ic/qwxreg.h
10462
#define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
sys/dev/ic/qwxreg.h
10463
#define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
sys/dev/ic/qwxreg.h
10464
#define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
sys/dev/ic/qwxreg.h
10465
#define RX_ATTENTION_INFO1_NON_QOS BIT(6)
sys/dev/ic/qwxreg.h
10466
#define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
sys/dev/ic/qwxreg.h
10467
#define RX_ATTENTION_INFO1_MGMT_TYPE BIT(8)
sys/dev/ic/qwxreg.h
10468
#define RX_ATTENTION_INFO1_CTRL_TYPE BIT(9)
sys/dev/ic/qwxreg.h
10469
#define RX_ATTENTION_INFO1_MORE_DATA BIT(10)
sys/dev/ic/qwxreg.h
10470
#define RX_ATTENTION_INFO1_EOSP BIT(11)
sys/dev/ic/qwxreg.h
10471
#define RX_ATTENTION_INFO1_A_MSDU_ERROR BIT(12)
sys/dev/ic/qwxreg.h
10472
#define RX_ATTENTION_INFO1_FRAGMENT BIT(13)
sys/dev/ic/qwxreg.h
10473
#define RX_ATTENTION_INFO1_ORDER BIT(14)
sys/dev/ic/qwxreg.h
10474
#define RX_ATTENTION_INFO1_CCE_MATCH BIT(15)
sys/dev/ic/qwxreg.h
10475
#define RX_ATTENTION_INFO1_OVERFLOW_ERR BIT(16)
sys/dev/ic/qwxreg.h
10476
#define RX_ATTENTION_INFO1_MSDU_LEN_ERR BIT(17)
sys/dev/ic/qwxreg.h
10477
#define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL BIT(18)
sys/dev/ic/qwxreg.h
10478
#define RX_ATTENTION_INFO1_IP_CKSUM_FAIL BIT(19)
sys/dev/ic/qwxreg.h
10479
#define RX_ATTENTION_INFO1_SA_IDX_INVALID BIT(20)
sys/dev/ic/qwxreg.h
10480
#define RX_ATTENTION_INFO1_DA_IDX_INVALID BIT(21)
sys/dev/ic/qwxreg.h
10481
#define RX_ATTENTION_INFO1_RSVD_1B BIT(22)
sys/dev/ic/qwxreg.h
10482
#define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP BIT(23)
sys/dev/ic/qwxreg.h
10483
#define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED BIT(24)
sys/dev/ic/qwxreg.h
10484
#define RX_ATTENTION_INFO1_DIRECTED BIT(25)
sys/dev/ic/qwxreg.h
10485
#define RX_ATTENTION_INFO1_BUFFER_FRAGMENT BIT(26)
sys/dev/ic/qwxreg.h
10486
#define RX_ATTENTION_INFO1_MPDU_LEN_ERR BIT(27)
sys/dev/ic/qwxreg.h
10487
#define RX_ATTENTION_INFO1_TKIP_MIC_ERR BIT(28)
sys/dev/ic/qwxreg.h
10488
#define RX_ATTENTION_INFO1_DECRYPT_ERR BIT(29)
sys/dev/ic/qwxreg.h
10489
#define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR BIT(30)
sys/dev/ic/qwxreg.h
10490
#define RX_ATTENTION_INFO1_FCS_ERR BIT(31)
sys/dev/ic/qwxreg.h
10492
#define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT BIT(0)
sys/dev/ic/qwxreg.h
10493
#define RX_ATTENTION_INFO2_FLOW_IDX_INVALID BIT(1)
sys/dev/ic/qwxreg.h
10494
#define RX_ATTENTION_INFO2_WIFI_PARSER_ERR BIT(2)
sys/dev/ic/qwxreg.h
10495
#define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR BIT(3)
sys/dev/ic/qwxreg.h
10496
#define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT BIT(4)
sys/dev/ic/qwxreg.h
10497
#define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT BIT(5)
sys/dev/ic/qwxreg.h
10498
#define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR BIT(6)
sys/dev/ic/qwxreg.h
10499
#define RX_ATTENTION_INFO2_DA_IS_VALID BIT(7)
sys/dev/ic/qwxreg.h
10500
#define RX_ATTENTION_INFO2_DA_IS_MCBC BIT(8)
sys/dev/ic/qwxreg.h
10501
#define RX_ATTENTION_INFO2_SA_IS_VALID BIT(9)
sys/dev/ic/qwxreg.h
10503
#define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED BIT(13)
sys/dev/ic/qwxreg.h
10504
#define RX_ATTENTION_INFO2_MSDU_DONE BIT(31)
sys/dev/ic/qwxreg.h
10710
#define RX_MPDU_START_INFO0_NDP_FRAME BIT(9)
sys/dev/ic/qwxreg.h
10711
#define RX_MPDU_START_INFO0_PHY_ERR BIT(10)
sys/dev/ic/qwxreg.h
10712
#define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR BIT(11)
sys/dev/ic/qwxreg.h
10713
#define RX_MPDU_START_INFO0_PROTO_VER_ERR BIT(12)
sys/dev/ic/qwxreg.h
10714
#define RX_MPDU_START_INFO0_AST_LOOKUP_VALID BIT(13)
sys/dev/ic/qwxreg.h
10716
#define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID BIT(0)
sys/dev/ic/qwxreg.h
10717
#define RX_MPDU_START_INFO1_MPDU_DUR_VALID BIT(1)
sys/dev/ic/qwxreg.h
10718
#define RX_MPDU_START_INFO1_MAC_ADDR1_VALID BIT(2)
sys/dev/ic/qwxreg.h
10719
#define RX_MPDU_START_INFO1_MAC_ADDR2_VALID BIT(3)
sys/dev/ic/qwxreg.h
10720
#define RX_MPDU_START_INFO1_MAC_ADDR3_VALID BIT(4)
sys/dev/ic/qwxreg.h
10721
#define RX_MPDU_START_INFO1_MAC_ADDR4_VALID BIT(5)
sys/dev/ic/qwxreg.h
10722
#define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID BIT(6)
sys/dev/ic/qwxreg.h
10723
#define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID BIT(7)
sys/dev/ic/qwxreg.h
10724
#define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID BIT(8)
sys/dev/ic/qwxreg.h
10725
#define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID BIT(9)
sys/dev/ic/qwxreg.h
10727
#define RX_MPDU_START_INFO1_MORE_FRAG_FLAG BIT(14)
sys/dev/ic/qwxreg.h
10728
#define RX_MPDU_START_INFO1_FROM_DS BIT(16)
sys/dev/ic/qwxreg.h
10729
#define RX_MPDU_START_INFO1_TO_DS BIT(17)
sys/dev/ic/qwxreg.h
10730
#define RX_MPDU_START_INFO1_ENCRYPTED BIT(18)
sys/dev/ic/qwxreg.h
10731
#define RX_MPDU_START_INFO1_MPDU_RETRY BIT(19)
sys/dev/ic/qwxreg.h
10734
#define RX_MPDU_START_INFO2_EPD_EN BIT(0)
sys/dev/ic/qwxreg.h
10735
#define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1)
sys/dev/ic/qwxreg.h
10738
#define RX_MPDU_START_INFO2_MESH_STA BIT(8)
sys/dev/ic/qwxreg.h
10739
#define RX_MPDU_START_INFO2_BSSID_HIT BIT(9)
sys/dev/ic/qwxreg.h
10745
#define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ BIT(7)
sys/dev/ic/qwxreg.h
10746
#define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA BIT(8)
sys/dev/ic/qwxreg.h
10747
#define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA BIT(9)
sys/dev/ic/qwxreg.h
10748
#define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR BIT(10)
sys/dev/ic/qwxreg.h
10754
#define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN BIT(24)
sys/dev/ic/qwxreg.h
10755
#define RX_MPDU_START_INFO4_FIRST_DELIM_ERR BIT(25)
sys/dev/ic/qwxreg.h
10758
#define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8)
sys/dev/ic/qwxreg.h
10759
#define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9)
sys/dev/ic/qwxreg.h
10761
#define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12)
sys/dev/ic/qwxreg.h
10762
#define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13)
sys/dev/ic/qwxreg.h
10763
#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14)
sys/dev/ic/qwxreg.h
10764
#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15)
sys/dev/ic/qwxreg.h
10766
#define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28)
sys/dev/ic/qwxreg.h
10767
#define RX_MPDU_START_INFO5_BAR_FRAME BIT(29)
sys/dev/ic/qwxreg.h
10770
#define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14)
sys/dev/ic/qwxreg.h
10771
#define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15)
sys/dev/ic/qwxreg.h
10772
#define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16)
sys/dev/ic/qwxreg.h
10773
#define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17)
sys/dev/ic/qwxreg.h
10774
#define RX_MPDU_START_INFO6_POWER_MGMT BIT(18)
sys/dev/ic/qwxreg.h
10775
#define RX_MPDU_START_INFO6_NON_QOS BIT(19)
sys/dev/ic/qwxreg.h
10776
#define RX_MPDU_START_INFO6_NULL_DATA BIT(20)
sys/dev/ic/qwxreg.h
10777
#define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21)
sys/dev/ic/qwxreg.h
10778
#define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22)
sys/dev/ic/qwxreg.h
10779
#define RX_MPDU_START_INFO6_MORE_DATA BIT(23)
sys/dev/ic/qwxreg.h
10780
#define RX_MPDU_START_INFO6_EOSP BIT(24)
sys/dev/ic/qwxreg.h
10781
#define RX_MPDU_START_INFO6_FRAGMENT BIT(25)
sys/dev/ic/qwxreg.h
10782
#define RX_MPDU_START_INFO6_ORDER BIT(26)
sys/dev/ic/qwxreg.h
10783
#define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27)
sys/dev/ic/qwxreg.h
10784
#define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28)
sys/dev/ic/qwxreg.h
10785
#define RX_MPDU_START_INFO6_DIRECTED BIT(29)
sys/dev/ic/qwxreg.h
10787
#define RX_MPDU_START_RAW_MPDU BIT(0)
sys/dev/ic/qwxreg.h
10817
#define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ BIT(7)
sys/dev/ic/qwxreg.h
10818
#define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA BIT(8)
sys/dev/ic/qwxreg.h
10819
#define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA BIT(9)
sys/dev/ic/qwxreg.h
10820
#define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR BIT(10)
sys/dev/ic/qwxreg.h
10826
#define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN BIT(24)
sys/dev/ic/qwxreg.h
10827
#define RX_MPDU_START_INFO8_FIRST_DELIM_ERR BIT(25)
sys/dev/ic/qwxreg.h
10829
#define RX_MPDU_START_INFO9_EPD_EN BIT(0)
sys/dev/ic/qwxreg.h
10830
#define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD BIT(1)
sys/dev/ic/qwxreg.h
10834
#define RX_MPDU_START_INFO9_BSSID_HIT BIT(10)
sys/dev/ic/qwxreg.h
10840
#define RX_MPDU_START_INFO10_NDP_FRAME BIT(9)
sys/dev/ic/qwxreg.h
10841
#define RX_MPDU_START_INFO10_PHY_ERR BIT(10)
sys/dev/ic/qwxreg.h
10842
#define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR BIT(11)
sys/dev/ic/qwxreg.h
10843
#define RX_MPDU_START_INFO10_PROTO_VER_ERR BIT(12)
sys/dev/ic/qwxreg.h
10844
#define RX_MPDU_START_INFO10_AST_LOOKUP_VALID BIT(13)
sys/dev/ic/qwxreg.h
10846
#define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID BIT(0)
sys/dev/ic/qwxreg.h
10847
#define RX_MPDU_START_INFO11_MPDU_DUR_VALID BIT(1)
sys/dev/ic/qwxreg.h
10848
#define RX_MPDU_START_INFO11_MAC_ADDR1_VALID BIT(2)
sys/dev/ic/qwxreg.h
10849
#define RX_MPDU_START_INFO11_MAC_ADDR2_VALID BIT(3)
sys/dev/ic/qwxreg.h
10850
#define RX_MPDU_START_INFO11_MAC_ADDR3_VALID BIT(4)
sys/dev/ic/qwxreg.h
10851
#define RX_MPDU_START_INFO11_MAC_ADDR4_VALID BIT(5)
sys/dev/ic/qwxreg.h
10852
#define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID BIT(6)
sys/dev/ic/qwxreg.h
10853
#define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID BIT(7)
sys/dev/ic/qwxreg.h
10854
#define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID BIT(8)
sys/dev/ic/qwxreg.h
10855
#define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID BIT(9)
sys/dev/ic/qwxreg.h
10857
#define RX_MPDU_START_INFO11_MORE_FRAG_FLAG BIT(14)
sys/dev/ic/qwxreg.h
10858
#define RX_MPDU_START_INFO11_FROM_DS BIT(16)
sys/dev/ic/qwxreg.h
10859
#define RX_MPDU_START_INFO11_TO_DS BIT(17)
sys/dev/ic/qwxreg.h
10860
#define RX_MPDU_START_INFO11_ENCRYPTED BIT(18)
sys/dev/ic/qwxreg.h
10861
#define RX_MPDU_START_INFO11_MPDU_RETRY BIT(19)
sys/dev/ic/qwxreg.h
10865
#define RX_MPDU_START_INFO12_NEW_PEER_ENTRY BIT(8)
sys/dev/ic/qwxreg.h
10866
#define RX_MPDU_START_INFO12_DECRYPT_NEEDED BIT(9)
sys/dev/ic/qwxreg.h
10868
#define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING BIT(12)
sys/dev/ic/qwxreg.h
10869
#define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING BIT(13)
sys/dev/ic/qwxreg.h
10870
#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C BIT(14)
sys/dev/ic/qwxreg.h
10871
#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S BIT(15)
sys/dev/ic/qwxreg.h
10873
#define RX_MPDU_START_INFO12_AMPDU_FLAG BIT(28)
sys/dev/ic/qwxreg.h
10874
#define RX_MPDU_START_INFO12_BAR_FRAME BIT(29)
sys/dev/ic/qwxreg.h
10875
#define RX_MPDU_START_INFO12_RAW_MPDU BIT(30)
sys/dev/ic/qwxreg.h
10878
#define RX_MPDU_START_INFO13_FIRST_MPDU BIT(14)
sys/dev/ic/qwxreg.h
10879
#define RX_MPDU_START_INFO13_MCAST_BCAST BIT(15)
sys/dev/ic/qwxreg.h
10880
#define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND BIT(16)
sys/dev/ic/qwxreg.h
10881
#define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT BIT(17)
sys/dev/ic/qwxreg.h
10882
#define RX_MPDU_START_INFO13_POWER_MGMT BIT(18)
sys/dev/ic/qwxreg.h
10883
#define RX_MPDU_START_INFO13_NON_QOS BIT(19)
sys/dev/ic/qwxreg.h
10884
#define RX_MPDU_START_INFO13_NULL_DATA BIT(20)
sys/dev/ic/qwxreg.h
10885
#define RX_MPDU_START_INFO13_MGMT_TYPE BIT(21)
sys/dev/ic/qwxreg.h
10886
#define RX_MPDU_START_INFO13_CTRL_TYPE BIT(22)
sys/dev/ic/qwxreg.h
10887
#define RX_MPDU_START_INFO13_MORE_DATA BIT(23)
sys/dev/ic/qwxreg.h
10888
#define RX_MPDU_START_INFO13_EOSP BIT(24)
sys/dev/ic/qwxreg.h
10889
#define RX_MPDU_START_INFO13_FRAGMENT BIT(25)
sys/dev/ic/qwxreg.h
10890
#define RX_MPDU_START_INFO13_ORDER BIT(26)
sys/dev/ic/qwxreg.h
10891
#define RX_MPDU_START_INFO13_UAPSD_TRIGGER BIT(27)
sys/dev/ic/qwxreg.h
10892
#define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED BIT(28)
sys/dev/ic/qwxreg.h
10893
#define RX_MPDU_START_INFO13_DIRECTED BIT(29)
sys/dev/ic/qwxreg.h
10894
#define RX_MPDU_START_INFO13_AMSDU_PRESENT BIT(30)
sys/dev/ic/qwxreg.h
11145
#define RX_MSDU_START_INFO1_RSVD_1A BIT(14)
sys/dev/ic/qwxreg.h
11146
#define RX_MSDU_START_INFO1_IPSEC_ESP BIT(15)
sys/dev/ic/qwxreg.h
11148
#define RX_MSDU_START_INFO1_IPSEC_AH BIT(23)
sys/dev/ic/qwxreg.h
11153
#define RX_MSDU_START_INFO2_IPV4 BIT(10)
sys/dev/ic/qwxreg.h
11154
#define RX_MSDU_START_INFO2_IPV6 BIT(11)
sys/dev/ic/qwxreg.h
11155
#define RX_MSDU_START_INFO2_TCP BIT(12)
sys/dev/ic/qwxreg.h
11156
#define RX_MSDU_START_INFO2_UDP BIT(13)
sys/dev/ic/qwxreg.h
11157
#define RX_MSDU_START_INFO2_IP_FRAG BIT(14)
sys/dev/ic/qwxreg.h
11158
#define RX_MSDU_START_INFO2_TCP_ONLY_ACK BIT(15)
sys/dev/ic/qwxreg.h
11159
#define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST BIT(16)
sys/dev/ic/qwxreg.h
11161
#define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID BIT(19)
sys/dev/ic/qwxreg.h
11162
#define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID BIT(20)
sys/dev/ic/qwxreg.h
11163
#define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID BIT(21)
sys/dev/ic/qwxreg.h
11164
#define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT BIT(22)
sys/dev/ic/qwxreg.h
11165
#define RX_MSDU_START_INFO2_LDPC BIT(23)
sys/dev/ic/qwxreg.h
11171
#define RX_MSDU_START_INFO3_STBC BIT(12)
sys/dev/ic/qwxreg.h
11396
#define RX_MSDU_END_INFO1_CCND_TRUNCATE BIT(14)
sys/dev/ic/qwxreg.h
11397
#define RX_MSDU_END_INFO1_CCND_CCE_DIS BIT(15)
sys/dev/ic/qwxreg.h
11401
#define RX_MSDU_END_INFO2_FIRST_MSDU BIT(14)
sys/dev/ic/qwxreg.h
11402
#define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855 BIT(28)
sys/dev/ic/qwxreg.h
11403
#define RX_MSDU_END_INFO2_LAST_MSDU BIT(15)
sys/dev/ic/qwxreg.h
11404
#define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855 BIT(29)
sys/dev/ic/qwxreg.h
11405
#define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT BIT(16)
sys/dev/ic/qwxreg.h
11406
#define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT BIT(17)
sys/dev/ic/qwxreg.h
11407
#define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR BIT(18)
sys/dev/ic/qwxreg.h
11408
#define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT BIT(19)
sys/dev/ic/qwxreg.h
11409
#define RX_MSDU_END_INFO2_FLOW_IDX_INVALID BIT(20)
sys/dev/ic/qwxreg.h
11410
#define RX_MSDU_END_INFO2_WIFI_PARSER_ERR BIT(21)
sys/dev/ic/qwxreg.h
11411
#define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR BIT(22)
sys/dev/ic/qwxreg.h
11412
#define RX_MSDU_END_INFO2_SA_IS_VALID BIT(23)
sys/dev/ic/qwxreg.h
11413
#define RX_MSDU_END_INFO2_DA_IS_VALID BIT(24)
sys/dev/ic/qwxreg.h
11414
#define RX_MSDU_END_INFO2_DA_IS_MCBC BIT(25)
sys/dev/ic/qwxreg.h
11418
#define RX_MSDU_END_INFO3_LRO_ELIGIBLE BIT(9)
sys/dev/ic/qwxreg.h
11422
#define RX_MSDU_END_INFO4_DA_OFFSET_VALID BIT(12)
sys/dev/ic/qwxreg.h
11423
#define RX_MSDU_END_INFO4_SA_OFFSET_VALID BIT(13)
sys/dev/ic/qwxreg.h
11426
#define RX_MSDU_END_INFO5_MSDU_DROP BIT(0)
sys/dev/ic/qwxreg.h
11482
#define RX_MSDU_END_INFO2_DA_OFFSET_VALID BIT(12)
sys/dev/ic/qwxreg.h
11483
#define RX_MSDU_END_INFO2_SA_OFFSET_VALID BIT(13)
sys/dev/ic/qwxreg.h
11486
#define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT BIT(0)
sys/dev/ic/qwxreg.h
11487
#define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT BIT(1)
sys/dev/ic/qwxreg.h
11488
#define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR BIT(2)
sys/dev/ic/qwxreg.h
11489
#define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT BIT(3)
sys/dev/ic/qwxreg.h
11490
#define RX_MSDU_END_INFO4_FLOW_IDX_INVALID BIT(4)
sys/dev/ic/qwxreg.h
11491
#define RX_MSDU_END_INFO4_WIFI_PARSER_ERR BIT(5)
sys/dev/ic/qwxreg.h
11492
#define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR BIT(6)
sys/dev/ic/qwxreg.h
11493
#define RX_MSDU_END_INFO4_SA_IS_VALID BIT(7)
sys/dev/ic/qwxreg.h
11494
#define RX_MSDU_END_INFO4_DA_IS_VALID BIT(8)
sys/dev/ic/qwxreg.h
11495
#define RX_MSDU_END_INFO4_DA_IS_MCBC BIT(9)
sys/dev/ic/qwxreg.h
11497
#define RX_MSDU_END_INFO4_FIRST_MSDU BIT(12)
sys/dev/ic/qwxreg.h
11498
#define RX_MSDU_END_INFO4_LAST_MSDU BIT(13)
sys/dev/ic/qwxreg.h
11501
#define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN BIT(8)
sys/dev/ic/qwxreg.h
11502
#define RX_MSDU_END_INFO6_FISA_TIMEOUT BIT(9)
sys/dev/ic/qwxreg.h
11699
#define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME BIT(11)
sys/dev/ic/qwxreg.h
11700
#define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT BIT(12)
sys/dev/ic/qwxreg.h
11701
#define RX_MPDU_END_INFO1_OVERFLOW_ERR BIT(13)
sys/dev/ic/qwxreg.h
11702
#define RX_MPDU_END_INFO1_MPDU_LEN_ERR BIT(14)
sys/dev/ic/qwxreg.h
11703
#define RX_MPDU_END_INFO1_TKIP_MIC_ERR BIT(15)
sys/dev/ic/qwxreg.h
11704
#define RX_MPDU_END_INFO1_DECRYPT_ERR BIT(16)
sys/dev/ic/qwxreg.h
11705
#define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR BIT(17)
sys/dev/ic/qwxreg.h
11706
#define RX_MPDU_END_INFO1_PN_FIELDS_VALID BIT(18)
sys/dev/ic/qwxreg.h
11707
#define RX_MPDU_END_INFO1_FCS_ERR BIT(19)
sys/dev/ic/qwxreg.h
11708
#define RX_MPDU_END_INFO1_MSDU_LEN_ERR BIT(20)
sys/dev/ic/qwxreg.h
11712
#define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD BIT(28)
sys/dev/ic/qwxreg.h
11882
#define HTT_TCL_META_DATA_TYPE BIT(0)
sys/dev/ic/qwxreg.h
11883
#define HTT_TCL_META_DATA_VALID_HTT BIT(1)
sys/dev/ic/qwxreg.h
11888
#define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
sys/dev/ic/qwxreg.h
11904
#define HTT_TX_WBM_COMP_INFO2_VALID BIT(21)
sys/dev/ic/qwxreg.h
12079
#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
sys/dev/ic/qwxreg.h
12080
#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
sys/dev/ic/qwxreg.h
12081
#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
sys/dev/ic/qwxreg.h
12082
#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
sys/dev/ic/qwxreg.h
12085
#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
sys/dev/ic/qwxreg.h
12089
#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16)
sys/dev/ic/qwxreg.h
12090
#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
sys/dev/ic/qwxreg.h
12146
#define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8)
sys/dev/ic/qwxreg.h
12170
#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
sys/dev/ic/qwxreg.h
12171
| BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
sys/dev/ic/qwxreg.h
12172
| BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
sys/dev/ic/qwxreg.h
12173
| BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
sys/dev/ic/qwxreg.h
12174
| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
sys/dev/ic/qwxreg.h
12175
| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
sys/dev/ic/qwxreg.h
12176
| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
sys/dev/ic/qwxreg.h
12177
| BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
sys/dev/ic/qwxreg.h
12179
#define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
sys/dev/ic/qwxreg.h
12180
BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
sys/dev/ic/qwxreg.h
12181
BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
sys/dev/ic/qwxreg.h
12182
BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
sys/dev/ic/qwxreg.h
12183
BIT(HTT_PPDU_STATS_TAG_INFO) | \
sys/dev/ic/qwxreg.h
12184
BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
sys/dev/ic/qwxreg.h
12260
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
sys/dev/ic/qwxreg.h
12261
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
sys/dev/ic/qwxreg.h
12266
HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
sys/dev/ic/qwxreg.h
12267
HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
sys/dev/ic/qwxreg.h
12268
HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
sys/dev/ic/qwxreg.h
12269
HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
sys/dev/ic/qwxreg.h
12270
HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
sys/dev/ic/qwxreg.h
12271
HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
sys/dev/ic/qwxreg.h
12272
HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
sys/dev/ic/qwxreg.h
12273
HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
sys/dev/ic/qwxreg.h
12274
HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
sys/dev/ic/qwxreg.h
12275
HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
sys/dev/ic/qwxreg.h
12276
HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
sys/dev/ic/qwxreg.h
12277
HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
sys/dev/ic/qwxreg.h
12278
HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
sys/dev/ic/qwxreg.h
12282
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
sys/dev/ic/qwxreg.h
12283
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
sys/dev/ic/qwxreg.h
12284
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
sys/dev/ic/qwxreg.h
12285
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
sys/dev/ic/qwxreg.h
12286
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
sys/dev/ic/qwxreg.h
12287
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
sys/dev/ic/qwxreg.h
12288
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
sys/dev/ic/qwxreg.h
12289
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
sys/dev/ic/qwxreg.h
12290
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
sys/dev/ic/qwxreg.h
12291
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
sys/dev/ic/qwxreg.h
12292
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
sys/dev/ic/qwxreg.h
12293
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
sys/dev/ic/qwxreg.h
12294
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
sys/dev/ic/qwxreg.h
12295
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
sys/dev/ic/qwxreg.h
12296
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
sys/dev/ic/qwxreg.h
12297
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
sys/dev/ic/qwxreg.h
12298
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
sys/dev/ic/qwxreg.h
12299
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
sys/dev/ic/qwxreg.h
12300
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
sys/dev/ic/qwxreg.h
12301
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
sys/dev/ic/qwxreg.h
12302
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
sys/dev/ic/qwxreg.h
12303
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
sys/dev/ic/qwxreg.h
12304
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
sys/dev/ic/qwxreg.h
12305
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
sys/dev/ic/qwxreg.h
12306
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
sys/dev/ic/qwxreg.h
12307
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
sys/dev/ic/qwxreg.h
12308
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
sys/dev/ic/qwxreg.h
12309
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
sys/dev/ic/qwxreg.h
12310
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
sys/dev/ic/qwxreg.h
12311
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
sys/dev/ic/qwxreg.h
12315
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
sys/dev/ic/qwxreg.h
12316
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
sys/dev/ic/qwxreg.h
12317
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
sys/dev/ic/qwxreg.h
12318
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
sys/dev/ic/qwxreg.h
12319
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
sys/dev/ic/qwxreg.h
12320
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
sys/dev/ic/qwxreg.h
12321
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
sys/dev/ic/qwxreg.h
12322
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
sys/dev/ic/qwxreg.h
12323
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
sys/dev/ic/qwxreg.h
12324
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
sys/dev/ic/qwxreg.h
12325
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
sys/dev/ic/qwxreg.h
12326
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
sys/dev/ic/qwxreg.h
12327
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
sys/dev/ic/qwxreg.h
12328
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
sys/dev/ic/qwxreg.h
12329
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
sys/dev/ic/qwxreg.h
12330
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
sys/dev/ic/qwxreg.h
12331
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
sys/dev/ic/qwxreg.h
12332
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
sys/dev/ic/qwxreg.h
12336
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
sys/dev/ic/qwxreg.h
12337
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
sys/dev/ic/qwxreg.h
12338
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
sys/dev/ic/qwxreg.h
12339
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
sys/dev/ic/qwxreg.h
12340
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
sys/dev/ic/qwxreg.h
12341
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
sys/dev/ic/qwxreg.h
12342
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
sys/dev/ic/qwxreg.h
12343
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
sys/dev/ic/qwxreg.h
12344
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
sys/dev/ic/qwxreg.h
12345
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
sys/dev/ic/qwxreg.h
12346
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
sys/dev/ic/qwxreg.h
12347
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
sys/dev/ic/qwxreg.h
12348
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
sys/dev/ic/qwxreg.h
12349
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
sys/dev/ic/qwxreg.h
12350
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
sys/dev/ic/qwxreg.h
12351
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
sys/dev/ic/qwxreg.h
12352
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
sys/dev/ic/qwxreg.h
12353
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
sys/dev/ic/qwxreg.h
12354
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
sys/dev/ic/qwxreg.h
12355
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
sys/dev/ic/qwxreg.h
12356
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
sys/dev/ic/qwxreg.h
12357
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
sys/dev/ic/qwxreg.h
12358
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
sys/dev/ic/qwxreg.h
12359
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
sys/dev/ic/qwxreg.h
12360
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
sys/dev/ic/qwxreg.h
12361
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
sys/dev/ic/qwxreg.h
12362
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
sys/dev/ic/qwxreg.h
12363
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
sys/dev/ic/qwxreg.h
12364
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
sys/dev/ic/qwxreg.h
12365
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
sys/dev/ic/qwxreg.h
12369
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
sys/dev/ic/qwxreg.h
12370
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
sys/dev/ic/qwxreg.h
12371
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
sys/dev/ic/qwxreg.h
12372
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
sys/dev/ic/qwxreg.h
12373
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
sys/dev/ic/qwxreg.h
12374
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
sys/dev/ic/qwxreg.h
12375
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
sys/dev/ic/qwxreg.h
12376
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
sys/dev/ic/qwxreg.h
12377
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
sys/dev/ic/qwxreg.h
12378
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
sys/dev/ic/qwxreg.h
12379
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
sys/dev/ic/qwxreg.h
12380
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
sys/dev/ic/qwxreg.h
12381
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
sys/dev/ic/qwxreg.h
12382
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
sys/dev/ic/qwxreg.h
12383
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
sys/dev/ic/qwxreg.h
12384
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
sys/dev/ic/qwxreg.h
12385
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
sys/dev/ic/qwxreg.h
12386
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
sys/dev/ic/qwxreg.h
12390
HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
sys/dev/ic/qwxreg.h
12391
HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
sys/dev/ic/qwxreg.h
12392
HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
sys/dev/ic/qwxreg.h
12393
HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
sys/dev/ic/qwxreg.h
12394
HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
sys/dev/ic/qwxreg.h
12395
HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
sys/dev/ic/qwxreg.h
12396
HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
sys/dev/ic/qwxreg.h
12397
HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
sys/dev/ic/qwxreg.h
12398
HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
sys/dev/ic/qwxreg.h
12588
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0)
sys/dev/ic/qwxreg.h
12589
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1)
sys/dev/ic/qwxreg.h
12590
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2)
sys/dev/ic/qwxreg.h
12642
#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
sys/dev/ic/qwxreg.h
12826
#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
sys/dev/ic/qwxreg.h
12830
#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
sys/dev/ic/qwxreg.h
12831
#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
sys/dev/ic/qwxreg.h
12838
#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
sys/dev/ic/qwxreg.h
12839
#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
sys/dev/ic/qwxreg.h
12855
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
sys/dev/ic/qwxreg.h
12856
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
sys/dev/ic/qwxreg.h
12863
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
sys/dev/ic/qwxreg.h
12864
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
sys/dev/ic/qwxreg.h
12882
#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
sys/dev/ic/qwxreg.h
12885
#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
sys/dev/ic/qwxreg.h
12919
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
sys/dev/ic/qwxreg.h
13154
#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
sys/dev/ic/qwxreg.h
13239
#define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
sys/dev/ic/qwxreg.h
210
WMI_HE_AUTORATE_LTF_1X = BIT(0),
sys/dev/ic/qwxreg.h
211
WMI_HE_AUTORATE_LTF_2X = BIT(1),
sys/dev/ic/qwxreg.h
212
WMI_HE_AUTORATE_LTF_4X = BIT(2),
sys/dev/ic/qwxreg.h
215
WMI_AUTORATE_400NS_GI = BIT(8),
sys/dev/ic/qwxreg.h
216
WMI_AUTORATE_800NS_GI = BIT(9),
sys/dev/ic/qwxreg.h
217
WMI_AUTORATE_1600NS_GI = BIT(10),
sys/dev/ic/qwxreg.h
218
WMI_AUTORATE_3200NS_GI = BIT(11),
sys/dev/ic/qwxreg.h
2324
#define ATH11K_11B_SUPPORT BIT(0)
sys/dev/ic/qwxreg.h
2325
#define ATH11K_11G_SUPPORT BIT(1)
sys/dev/ic/qwxreg.h
2326
#define ATH11K_11A_SUPPORT BIT(2)
sys/dev/ic/qwxreg.h
2327
#define ATH11K_11N_SUPPORT BIT(3)
sys/dev/ic/qwxreg.h
2328
#define ATH11K_11AC_SUPPORT BIT(4)
sys/dev/ic/qwxreg.h
2329
#define ATH11K_11AX_SUPPORT BIT(5)
sys/dev/ic/qwxreg.h
2410
#define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5)
sys/dev/ic/qwxreg.h
2411
#define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
sys/dev/ic/qwxreg.h
2412
#define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18)
sys/dev/ic/qwxreg.h
2556
#define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0)
sys/dev/ic/qwxreg.h
2719
#define WMI_VDEV_START_HIDDEN_SSID BIT(0)
sys/dev/ic/qwxreg.h
2720
#define WMI_VDEV_START_PMF_ENABLED BIT(1)
sys/dev/ic/qwxreg.h
2721
#define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3)
sys/dev/ic/qwxreg.h
2722
#define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4)
sys/dev/ic/qwxreg.h
2973
#define REG_RULE_PSD_INFO BIT(0)
sys/dev/ic/qwxreg.h
2976
#define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
sys/dev/ic/qwxreg.h
2977
#define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
sys/dev/ic/qwxreg.h
2978
#define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
sys/dev/ic/qwxreg.h
2979
#define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
sys/dev/ic/qwxreg.h
2987
#define HECAP_PHY_SU_BFER BIT(7)
sys/dev/ic/qwxreg.h
2988
#define HECAP_PHY_SU_BFEE BIT(0)
sys/dev/ic/qwxreg.h
2989
#define HECAP_PHY_MU_BFER BIT(1)
sys/dev/ic/qwxreg.h
2990
#define HECAP_PHY_UL_MUMIMO BIT(6)
sys/dev/ic/qwxreg.h
2991
#define HECAP_PHY_UL_MUOFDMA BIT(7)
sys/dev/ic/qwxreg.h
3008
#define HE_MODE_SU_TX_BFEE BIT(0)
sys/dev/ic/qwxreg.h
3009
#define HE_MODE_SU_TX_BFER BIT(1)
sys/dev/ic/qwxreg.h
3010
#define HE_MODE_MU_TX_BFEE BIT(2)
sys/dev/ic/qwxreg.h
3011
#define HE_MODE_MU_TX_BFER BIT(3)
sys/dev/ic/qwxreg.h
3012
#define HE_MODE_DL_OFDMA BIT(4)
sys/dev/ic/qwxreg.h
3013
#define HE_MODE_UL_OFDMA BIT(5)
sys/dev/ic/qwxreg.h
3014
#define HE_MODE_UL_MUMIMO BIT(6)
sys/dev/ic/qwxreg.h
3030
#define HE_VHT_SOUNDING_MODE BIT(0)
sys/dev/ic/qwxreg.h
3032
#define HE_SU_MU_SOUNDING_MODE BIT(2)
sys/dev/ic/qwxreg.h
3034
#define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3)
sys/dev/ic/qwxreg.h
3269
WMI_SCAN_EVENT_STARTED = BIT(0),
sys/dev/ic/qwxreg.h
3270
WMI_SCAN_EVENT_COMPLETED = BIT(1),
sys/dev/ic/qwxreg.h
3271
WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2),
sys/dev/ic/qwxreg.h
3272
WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3),
sys/dev/ic/qwxreg.h
3273
WMI_SCAN_EVENT_DEQUEUED = BIT(4),
sys/dev/ic/qwxreg.h
3275
WMI_SCAN_EVENT_PREEMPTED = BIT(5),
sys/dev/ic/qwxreg.h
3276
WMI_SCAN_EVENT_START_FAILED = BIT(6),
sys/dev/ic/qwxreg.h
3277
WMI_SCAN_EVENT_RESTARTED = BIT(7),
sys/dev/ic/qwxreg.h
3278
WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8),
sys/dev/ic/qwxreg.h
3279
WMI_SCAN_EVENT_SUSPENDED = BIT(9),
sys/dev/ic/qwxreg.h
3280
WMI_SCAN_EVENT_RESUMED = BIT(10),
sys/dev/ic/qwxreg.h
3281
WMI_SCAN_EVENT_MAX = BIT(15),
sys/dev/ic/qwxreg.h
3354
#define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20)
sys/dev/ic/qwxreg.h
3541
#define WMI_CHAN_INFO_HT40_PLUS BIT(6)
sys/dev/ic/qwxreg.h
3542
#define WMI_CHAN_INFO_PASSIVE BIT(7)
sys/dev/ic/qwxreg.h
3543
#define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8)
sys/dev/ic/qwxreg.h
3544
#define WMI_CHAN_INFO_AP_DISABLED BIT(9)
sys/dev/ic/qwxreg.h
3545
#define WMI_CHAN_INFO_DFS BIT(10)
sys/dev/ic/qwxreg.h
3546
#define WMI_CHAN_INFO_ALLOW_HT BIT(11)
sys/dev/ic/qwxreg.h
3547
#define WMI_CHAN_INFO_ALLOW_VHT BIT(12)
sys/dev/ic/qwxreg.h
3548
#define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13)
sys/dev/ic/qwxreg.h
3549
#define WMI_CHAN_INFO_HALF_RATE BIT(14)
sys/dev/ic/qwxreg.h
3550
#define WMI_CHAN_INFO_QUARTER_RATE BIT(15)
sys/dev/ic/qwxreg.h
3551
#define WMI_CHAN_INFO_DFS_FREQ2 BIT(16)
sys/dev/ic/qwxreg.h
3552
#define WMI_CHAN_INFO_ALLOW_HE BIT(17)
sys/dev/ic/qwxreg.h
3553
#define WMI_CHAN_INFO_PSC BIT(18)
sys/dev/ic/qwxreg.h
3613
WMI_REQUEST_PEER_STAT = BIT(0),
sys/dev/ic/qwxreg.h
3614
WMI_REQUEST_AP_STAT = BIT(1),
sys/dev/ic/qwxreg.h
3615
WMI_REQUEST_PDEV_STAT = BIT(2),
sys/dev/ic/qwxreg.h
3616
WMI_REQUEST_VDEV_STAT = BIT(3),
sys/dev/ic/qwxreg.h
3617
WMI_REQUEST_BCNFLT_STAT = BIT(4),
sys/dev/ic/qwxreg.h
3618
WMI_REQUEST_VDEV_RATE_STAT = BIT(5),
sys/dev/ic/qwxreg.h
3619
WMI_REQUEST_INST_STAT = BIT(6),
sys/dev/ic/qwxreg.h
3620
WMI_REQUEST_MIB_STAT = BIT(7),
sys/dev/ic/qwxreg.h
3621
WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8),
sys/dev/ic/qwxreg.h
3622
WMI_REQUEST_CONGESTION_STAT = BIT(9),
sys/dev/ic/qwxreg.h
3623
WMI_REQUEST_PEER_EXTD_STAT = BIT(10),
sys/dev/ic/qwxreg.h
3624
WMI_REQUEST_BCN_STAT = BIT(11),
sys/dev/ic/qwxreg.h
3625
WMI_REQUEST_BCN_STAT_RESET = BIT(12),
sys/dev/ic/qwxreg.h
3626
WMI_REQUEST_PEER_EXTD2_STAT = BIT(13),
sys/dev/ic/qwxreg.h
3869
#define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20)
sys/dev/ic/qwxreg.h
4230
#define REGULATORY_CHAN_DISABLED BIT(0)
sys/dev/ic/qwxreg.h
4231
#define REGULATORY_CHAN_NO_IR BIT(1)
sys/dev/ic/qwxreg.h
4232
#define REGULATORY_CHAN_RADAR BIT(3)
sys/dev/ic/qwxreg.h
4233
#define REGULATORY_CHAN_NO_OFDM BIT(6)
sys/dev/ic/qwxreg.h
4234
#define REGULATORY_CHAN_INDOOR_ONLY BIT(9)
sys/dev/ic/qwxreg.h
4236
#define REGULATORY_CHAN_NO_HT40 BIT(4)
sys/dev/ic/qwxreg.h
4237
#define REGULATORY_CHAN_NO_80MHZ BIT(7)
sys/dev/ic/qwxreg.h
4238
#define REGULATORY_CHAN_NO_160MHZ BIT(8)
sys/dev/ic/qwxreg.h
4239
#define REGULATORY_CHAN_NO_20MHZ BIT(11)
sys/dev/ic/qwxreg.h
4240
#define REGULATORY_CHAN_NO_10MHZ BIT(12)
sys/dev/ic/qwxreg.h
5416
#define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8)
sys/dev/ic/qwxreg.h
5417
#define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9)
sys/dev/ic/qwxreg.h
5418
#define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10)
sys/dev/ic/qwxreg.h
5419
#define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11)
sys/dev/ic/qwxreg.h
5821
WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0),
sys/dev/ic/qwxreg.h
5822
WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1),
sys/dev/ic/qwxreg.h
6085
#define WMI_NLO_CONFIG_STOP BIT(0)
sys/dev/ic/qwxreg.h
6086
#define WMI_NLO_CONFIG_START BIT(1)
sys/dev/ic/qwxreg.h
6087
#define WMI_NLO_CONFIG_RESET BIT(2)
sys/dev/ic/qwxreg.h
6088
#define WMI_NLO_CONFIG_SLOW_SCAN BIT(4)
sys/dev/ic/qwxreg.h
6089
#define WMI_NLO_CONFIG_FAST_SCAN BIT(5)
sys/dev/ic/qwxreg.h
6090
#define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6)
sys/dev/ic/qwxreg.h
6095
#define WMI_NLO_CONFIG_ENLO BIT(7)
sys/dev/ic/qwxreg.h
6096
#define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8)
sys/dev/ic/qwxreg.h
6097
#define WMI_NLO_CONFIG_ENLO_RESET BIT(9)
sys/dev/ic/qwxreg.h
6098
#define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10)
sys/dev/ic/qwxreg.h
6099
#define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11)
sys/dev/ic/qwxreg.h
6100
#define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12)
sys/dev/ic/qwxreg.h
6101
#define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13)
sys/dev/ic/qwxreg.h
6228
#define WMI_ARPOL_FLAGS_VALID BIT(0)
sys/dev/ic/qwxreg.h
6229
#define WMI_ARPOL_FLAGS_MAC_VALID BIT(1)
sys/dev/ic/qwxreg.h
6230
#define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2)
sys/dev/ic/qwxreg.h
6240
#define WMI_NSOL_FLAGS_VALID BIT(0)
sys/dev/ic/qwxreg.h
6241
#define WMI_NSOL_FLAGS_MAC_VALID BIT(1)
sys/dev/ic/qwxreg.h
6242
#define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2)
sys/dev/ic/qwxreg.h
6243
#define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3)
sys/dev/ic/qwxreg.h
7310
#define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1)
sys/dev/ic/qwxreg.h
7311
#define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
sys/dev/ic/qwxreg.h
7312
#define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4)
sys/dev/ic/qwxreg.h
7313
#define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5)
sys/dev/ic/qwxreg.h
7314
#define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6)
sys/dev/ic/qwxreg.h
7318
#define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
sys/dev/ic/qwxreg.h
7320
#define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17)
sys/dev/ic/qwxreg.h
7336
#define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
sys/dev/ic/qwxreg.h
7337
#define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4)
sys/dev/ic/qwxreg.h
7338
#define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5)
sys/dev/ic/qwxreg.h
7339
#define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6)
sys/dev/ic/qwxreg.h
7342
#define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
sys/dev/ic/qwxreg.h
7345
#define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2)
sys/dev/ic/qwxreg.h
7346
#define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
sys/dev/ic/qwxreg.h
7357
#define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1)
sys/dev/ic/qwxreg.h
8167
#define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27)
sys/dev/ic/qwxreg.h
8243
#define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11)
sys/dev/ic/qwxreg.h
8245
#define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16)
sys/dev/ic/qwxreg.h
8260
#define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16)
sys/dev/ic/qwxreg.h
8269
#define HAL_REO_CMD_FLG_NEED_STATUS BIT(0)
sys/dev/ic/qwxreg.h
8270
#define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1)
sys/dev/ic/qwxreg.h
8271
#define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2)
sys/dev/ic/qwxreg.h
8272
#define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
sys/dev/ic/qwxreg.h
8273
#define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4)
sys/dev/ic/qwxreg.h
8274
#define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5)
sys/dev/ic/qwxreg.h
8275
#define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6)
sys/dev/ic/qwxreg.h
8276
#define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7)
sys/dev/ic/qwxreg.h
8277
#define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8)
sys/dev/ic/qwxreg.h
8280
#define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8)
sys/dev/ic/qwxreg.h
8281
#define HAL_REO_CMD_UPD0_VLD BIT(9)
sys/dev/ic/qwxreg.h
8282
#define HAL_REO_CMD_UPD0_ALDC BIT(10)
sys/dev/ic/qwxreg.h
8283
#define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11)
sys/dev/ic/qwxreg.h
8284
#define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12)
sys/dev/ic/qwxreg.h
8285
#define HAL_REO_CMD_UPD0_AC BIT(13)
sys/dev/ic/qwxreg.h
8286
#define HAL_REO_CMD_UPD0_BAR BIT(14)
sys/dev/ic/qwxreg.h
8287
#define HAL_REO_CMD_UPD0_RETRY BIT(15)
sys/dev/ic/qwxreg.h
8288
#define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16)
sys/dev/ic/qwxreg.h
8289
#define HAL_REO_CMD_UPD0_OOR_MODE BIT(17)
sys/dev/ic/qwxreg.h
8290
#define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18)
sys/dev/ic/qwxreg.h
8291
#define HAL_REO_CMD_UPD0_PN_CHECK BIT(19)
sys/dev/ic/qwxreg.h
8292
#define HAL_REO_CMD_UPD0_EVEN_PN BIT(20)
sys/dev/ic/qwxreg.h
8293
#define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21)
sys/dev/ic/qwxreg.h
8294
#define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22)
sys/dev/ic/qwxreg.h
8295
#define HAL_REO_CMD_UPD0_PN_SIZE BIT(23)
sys/dev/ic/qwxreg.h
8296
#define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24)
sys/dev/ic/qwxreg.h
8297
#define HAL_REO_CMD_UPD0_SVLD BIT(25)
sys/dev/ic/qwxreg.h
8298
#define HAL_REO_CMD_UPD0_SSN BIT(26)
sys/dev/ic/qwxreg.h
8299
#define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27)
sys/dev/ic/qwxreg.h
8300
#define HAL_REO_CMD_UPD0_PN_ERR BIT(28)
sys/dev/ic/qwxreg.h
8301
#define HAL_REO_CMD_UPD0_PN_VALID BIT(29)
sys/dev/ic/qwxreg.h
8302
#define HAL_REO_CMD_UPD0_PN BIT(30)
sys/dev/ic/qwxreg.h
8305
#define HAL_REO_CMD_UPD1_VLD BIT(16)
sys/dev/ic/qwxreg.h
8307
#define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19)
sys/dev/ic/qwxreg.h
8308
#define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20)
sys/dev/ic/qwxreg.h
8310
#define HAL_REO_CMD_UPD1_BAR BIT(23)
sys/dev/ic/qwxreg.h
8311
#define HAL_REO_CMD_UPD1_RETRY BIT(24)
sys/dev/ic/qwxreg.h
8312
#define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25)
sys/dev/ic/qwxreg.h
8313
#define HAL_REO_CMD_UPD1_OOR_MODE BIT(26)
sys/dev/ic/qwxreg.h
8314
#define HAL_REO_CMD_UPD1_PN_CHECK BIT(27)
sys/dev/ic/qwxreg.h
8315
#define HAL_REO_CMD_UPD1_EVEN_PN BIT(28)
sys/dev/ic/qwxreg.h
8316
#define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29)
sys/dev/ic/qwxreg.h
8317
#define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30)
sys/dev/ic/qwxreg.h
8318
#define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31)
sys/dev/ic/qwxreg.h
8321
#define HAL_REO_CMD_UPD2_SVLD BIT(10)
sys/dev/ic/qwxreg.h
8323
#define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23)
sys/dev/ic/qwxreg.h
8324
#define HAL_REO_CMD_UPD2_PN_ERR BIT(24)
sys/dev/ic/qwxreg.h
8346
#define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8)
sys/dev/ic/qwxreg.h
8387
#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8)
sys/dev/ic/qwxreg.h
8398
#define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8)
sys/dev/ic/qwxreg.h
8399
#define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9)
sys/dev/ic/qwxreg.h
8401
#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12)
sys/dev/ic/qwxreg.h
8402
#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13)
sys/dev/ic/qwxreg.h
8403
#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14)
sys/dev/ic/qwxreg.h
8412
#define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0)
sys/dev/ic/qwxreg.h
8413
#define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1)
sys/dev/ic/qwxreg.h
8416
#define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8)
sys/dev/ic/qwxreg.h
8417
#define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9)
sys/dev/ic/qwxreg.h
8423
#define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16)
sys/dev/ic/qwxreg.h
8424
#define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17)
sys/dev/ic/qwxreg.h
8425
#define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18)
sys/dev/ic/qwxreg.h
8426
#define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19)
sys/dev/ic/qwxreg.h
8427
#define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20)
sys/dev/ic/qwxreg.h
8428
#define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21)
sys/dev/ic/qwxreg.h
8432
#define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19)
sys/dev/ic/qwxreg.h
8433
#define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20)
sys/dev/ic/qwxreg.h
8434
#define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21)
sys/dev/ic/qwxreg.h
8667
#define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12)
sys/dev/ic/qwxreg.h
8668
#define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13)
sys/dev/ic/qwxreg.h
8669
#define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14)
sys/dev/ic/qwxreg.h
8714
#define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4)
sys/dev/ic/qwxreg.h
8757
#define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8)
sys/dev/ic/qwxreg.h
8758
#define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9)
sys/dev/ic/qwxreg.h
8759
#define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10)
sys/dev/ic/qwxreg.h
8760
#define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11)
sys/dev/ic/qwxreg.h
8902
#define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8)
sys/dev/ic/qwxreg.h
8903
#define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9)
sys/dev/ic/qwxreg.h
8904
#define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10)
sys/dev/ic/qwxreg.h
8905
#define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11)
sys/dev/ic/qwxreg.h
8984
#define HAL_TX_RATE_STATS_INFO0_VALID BIT(0)
sys/dev/ic/qwxreg.h
8987
#define HAL_TX_RATE_STATS_INFO0_STBC BIT(7)
sys/dev/ic/qwxreg.h
8988
#define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8)
sys/dev/ic/qwxreg.h
8991
#define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15)
sys/dev/ic/qwxreg.h
9102
#define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31)
sys/dev/ic/qwxreg.h
9108
#define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8)
sys/dev/ic/qwxreg.h
9109
#define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9)
sys/dev/ic/qwxreg.h
9110
#define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10)
sys/dev/ic/qwxreg.h
9111
#define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11)
sys/dev/ic/qwxreg.h
9112
#define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12)
sys/dev/ic/qwxreg.h
9122
#define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17)
sys/dev/ic/qwxreg.h
9365
#define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16)
sys/dev/ic/qwxreg.h
9400
#define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0)
sys/dev/ic/qwxreg.h
9402
#define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3)
sys/dev/ic/qwxreg.h
9403
#define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4)
sys/dev/ic/qwxreg.h
9405
#define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7)
sys/dev/ic/qwxreg.h
9406
#define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8)
sys/dev/ic/qwxreg.h
9407
#define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9)
sys/dev/ic/qwxreg.h
9408
#define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10)
sys/dev/ic/qwxreg.h
9410
#define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19)
sys/dev/ic/qwxreg.h
9411
#define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20)
sys/dev/ic/qwxreg.h
9412
#define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21)
sys/dev/ic/qwxreg.h
9413
#define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22)
sys/dev/ic/qwxreg.h
9415
#define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25)
sys/dev/ic/qwxreg.h
9417
#define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0)
sys/dev/ic/qwxreg.h
9420
#define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21)
sys/dev/ic/qwxreg.h
9421
#define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22)
sys/dev/ic/qwxreg.h
9422
#define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31)
sys/dev/ic/qwxreg.h
9527
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8)
sys/dev/ic/qwxreg.h
9528
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9)
sys/dev/ic/qwxreg.h
9529
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10)
sys/dev/ic/qwxreg.h
9530
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11)
sys/dev/ic/qwxreg.h
9531
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12)
sys/dev/ic/qwxreg.h
9532
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13)
sys/dev/ic/qwxreg.h
9533
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14)
sys/dev/ic/qwxreg.h
9534
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15)
sys/dev/ic/qwxreg.h
9535
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16)
sys/dev/ic/qwxreg.h
9536
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17)
sys/dev/ic/qwxreg.h
9537
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18)
sys/dev/ic/qwxreg.h
9538
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19)
sys/dev/ic/qwxreg.h
9539
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20)
sys/dev/ic/qwxreg.h
9540
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21)
sys/dev/ic/qwxreg.h
9541
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22)
sys/dev/ic/qwxreg.h
9542
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23)
sys/dev/ic/qwxreg.h
9543
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24)
sys/dev/ic/qwxreg.h
9544
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25)
sys/dev/ic/qwxreg.h
9545
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26)
sys/dev/ic/qwxreg.h
9546
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27)
sys/dev/ic/qwxreg.h
9547
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28)
sys/dev/ic/qwxreg.h
9548
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29)
sys/dev/ic/qwxreg.h
9549
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30)
sys/dev/ic/qwxreg.h
9552
#define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16)
sys/dev/ic/qwxreg.h
9554
#define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19)
sys/dev/ic/qwxreg.h
9555
#define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20)
sys/dev/ic/qwxreg.h
9557
#define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23)
sys/dev/ic/qwxreg.h
9558
#define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24)
sys/dev/ic/qwxreg.h
9559
#define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25)
sys/dev/ic/qwxreg.h
9560
#define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26)
sys/dev/ic/qwxreg.h
9561
#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27)
sys/dev/ic/qwxreg.h
9562
#define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28)
sys/dev/ic/qwxreg.h
9563
#define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29)
sys/dev/ic/qwxreg.h
9564
#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30)
sys/dev/ic/qwxreg.h
9565
#define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31)
sys/dev/ic/qwxreg.h
9569
#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10)
sys/dev/ic/qwxreg.h
9571
#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23)
sys/dev/ic/qwxreg.h
9572
#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24)
sys/dev/ic/qwxreg.h
9573
#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25)
sys/dev/ic/qwxreg.h
9584
#define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0)
sys/dev/ic/qwxreg.h
9745
#define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0)
sys/dev/ic/qwxreg.h
9776
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0)
sys/dev/ic/qwxreg.h
9778
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8)
sys/dev/ic/qwxreg.h
9843
#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0)
sys/dev/ic/qwxreg.h
9844
#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1)
sys/dev/ic/qwxreg.h
9876
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0)
sys/dev/ic/qwxreg.h
9877
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1)
sys/dev/ic/qwxvar.h
140
#define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0)
sys/dev/ic/qwxvar.h
141
#define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1)
sys/dev/ic/qwxvar.h
142
#define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2)
sys/dev/ic/qwxvar.h
143
#define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3)
sys/dev/ic/qwxvar.h
144
#define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4)
sys/dev/ic/qwxvar.h
145
#define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5)
sys/dev/ic/qwxvar.h
146
#define HAL_TX_STATUS_FLAGS_OFDMA BIT(6)
sys/dev/ic/qwz.c
1301
#define ATH12K_TX_RING_MASK_0 BIT(0)
sys/dev/ic/qwz.c
1302
#define ATH12K_TX_RING_MASK_1 BIT(1)
sys/dev/ic/qwz.c
1303
#define ATH12K_TX_RING_MASK_2 BIT(2)
sys/dev/ic/qwz.c
1304
#define ATH12K_TX_RING_MASK_3 BIT(3)
sys/dev/ic/qwz.c
1305
#define ATH12K_TX_RING_MASK_4 BIT(4)
sys/dev/ic/qwz.c
15414
hal->avail_blk_resource |= BIT(hal->current_blk_index);
sys/dev/ic/qwz.c
15455
hal->avail_blk_resource &= ~BIT(hal->current_blk_index);
sys/dev/ic/qwz.c
1735
.qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) |
sys/dev/ic/qwz.c
1736
BIT(CNSS_PCIE_PERST_NO_PULL_V01),
sys/dev/ic/qwz.c
9065
BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
sys/dev/ic/qwz.c
9086
BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
sys/dev/ic/qwz.c
9264
if (wmi_svc_bm[i] & BIT(j % WMI_SERVICE_BITS_IN_SIZE32))
sys/dev/ic/qwzreg.h
10001
#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10)
sys/dev/ic/qwzreg.h
10003
#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23)
sys/dev/ic/qwzreg.h
10004
#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24)
sys/dev/ic/qwzreg.h
10005
#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25)
sys/dev/ic/qwzreg.h
10016
#define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0)
sys/dev/ic/qwzreg.h
10177
#define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0)
sys/dev/ic/qwzreg.h
10208
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0)
sys/dev/ic/qwzreg.h
10210
#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8)
sys/dev/ic/qwzreg.h
10275
#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0)
sys/dev/ic/qwzreg.h
10276
#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1)
sys/dev/ic/qwzreg.h
10308
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0)
sys/dev/ic/qwzreg.h
10309
#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1)
sys/dev/ic/qwzreg.h
10645
#define ATH12K_GLOBAL_DISABLE_CREDIT_FLOW BIT(1)
sys/dev/ic/qwzreg.h
10798
#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
sys/dev/ic/qwzreg.h
10799
#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
sys/dev/ic/qwzreg.h
10888
#define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
sys/dev/ic/qwzreg.h
10889
#define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
sys/dev/ic/qwzreg.h
10890
#define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
sys/dev/ic/qwzreg.h
10891
#define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
sys/dev/ic/qwzreg.h
10894
#define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
sys/dev/ic/qwzreg.h
10895
#define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
sys/dev/ic/qwzreg.h
10896
#define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
sys/dev/ic/qwzreg.h
10897
#define RX_MPDU_START_INFO0_USE_PPE BIT(20)
sys/dev/ic/qwzreg.h
10898
#define RX_MPDU_START_INFO0_PPE_ROUTING_EN BIT(21)
sys/dev/ic/qwzreg.h
10902
#define RX_MPDU_START_INFO1_PRE_DELIM_ERR_WARN BIT(24)
sys/dev/ic/qwzreg.h
10903
#define RX_MPDU_START_INFO1_FIRST_DELIM_ERR BIT(25)
sys/dev/ic/qwzreg.h
10905
#define RX_MPDU_START_INFO2_EPD_EN BIT(0)
sys/dev/ic/qwzreg.h
10906
#define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1)
sys/dev/ic/qwzreg.h
10910
#define RX_MPDU_START_INFO2_BSSID_HIT BIT(10)
sys/dev/ic/qwzreg.h
10916
#define RX_MPDU_START_INFO3_NDP_FRAME BIT(9)
sys/dev/ic/qwzreg.h
10917
#define RX_MPDU_START_INFO3_PHY_ERR BIT(10)
sys/dev/ic/qwzreg.h
10918
#define RX_MPDU_START_INFO3_PHY_ERR_MPDU_HDR BIT(11)
sys/dev/ic/qwzreg.h
10919
#define RX_MPDU_START_INFO3_PROTO_VER_ERR BIT(12)
sys/dev/ic/qwzreg.h
10920
#define RX_MPDU_START_INFO3_AST_LOOKUP_VALID BIT(13)
sys/dev/ic/qwzreg.h
10921
#define RX_MPDU_START_INFO3_RANGING BIT(14)
sys/dev/ic/qwzreg.h
10923
#define RX_MPDU_START_INFO4_MPDU_FCTRL_VALID BIT(0)
sys/dev/ic/qwzreg.h
10924
#define RX_MPDU_START_INFO4_MPDU_DUR_VALID BIT(1)
sys/dev/ic/qwzreg.h
10925
#define RX_MPDU_START_INFO4_MAC_ADDR1_VALID BIT(2)
sys/dev/ic/qwzreg.h
10926
#define RX_MPDU_START_INFO4_MAC_ADDR2_VALID BIT(3)
sys/dev/ic/qwzreg.h
10927
#define RX_MPDU_START_INFO4_MAC_ADDR3_VALID BIT(4)
sys/dev/ic/qwzreg.h
10928
#define RX_MPDU_START_INFO4_MAC_ADDR4_VALID BIT(5)
sys/dev/ic/qwzreg.h
10929
#define RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID BIT(6)
sys/dev/ic/qwzreg.h
10930
#define RX_MPDU_START_INFO4_MPDU_QOS_CTRL_VALID BIT(7)
sys/dev/ic/qwzreg.h
10931
#define RX_MPDU_START_INFO4_MPDU_HT_CTRL_VALID BIT(8)
sys/dev/ic/qwzreg.h
10932
#define RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID BIT(9)
sys/dev/ic/qwzreg.h
10934
#define RX_MPDU_START_INFO4_MORE_FRAG_FLAG BIT(14)
sys/dev/ic/qwzreg.h
10935
#define RX_MPDU_START_INFO4_FROM_DS BIT(16)
sys/dev/ic/qwzreg.h
10936
#define RX_MPDU_START_INFO4_TO_DS BIT(17)
sys/dev/ic/qwzreg.h
10937
#define RX_MPDU_START_INFO4_ENCRYPTED BIT(18)
sys/dev/ic/qwzreg.h
10938
#define RX_MPDU_START_INFO4_MPDU_RETRY BIT(19)
sys/dev/ic/qwzreg.h
10942
#define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8)
sys/dev/ic/qwzreg.h
10943
#define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9)
sys/dev/ic/qwzreg.h
10945
#define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12)
sys/dev/ic/qwzreg.h
10946
#define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13)
sys/dev/ic/qwzreg.h
10947
#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14)
sys/dev/ic/qwzreg.h
10948
#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15)
sys/dev/ic/qwzreg.h
10950
#define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28)
sys/dev/ic/qwzreg.h
10951
#define RX_MPDU_START_INFO5_BAR_FRAME BIT(29)
sys/dev/ic/qwzreg.h
10952
#define RX_MPDU_START_INFO5_RAW_MPDU BIT(30)
sys/dev/ic/qwzreg.h
10955
#define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14)
sys/dev/ic/qwzreg.h
10956
#define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15)
sys/dev/ic/qwzreg.h
10957
#define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16)
sys/dev/ic/qwzreg.h
10958
#define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17)
sys/dev/ic/qwzreg.h
10959
#define RX_MPDU_START_INFO6_POWER_MGMT BIT(18)
sys/dev/ic/qwzreg.h
10960
#define RX_MPDU_START_INFO6_NON_QOS BIT(19)
sys/dev/ic/qwzreg.h
10961
#define RX_MPDU_START_INFO6_NULL_DATA BIT(20)
sys/dev/ic/qwzreg.h
10962
#define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21)
sys/dev/ic/qwzreg.h
10963
#define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22)
sys/dev/ic/qwzreg.h
10964
#define RX_MPDU_START_INFO6_MORE_DATA BIT(23)
sys/dev/ic/qwzreg.h
10965
#define RX_MPDU_START_INFO6_EOSP BIT(24)
sys/dev/ic/qwzreg.h
10966
#define RX_MPDU_START_INFO6_FRAGMENT BIT(25)
sys/dev/ic/qwzreg.h
10967
#define RX_MPDU_START_INFO6_ORDER BIT(26)
sys/dev/ic/qwzreg.h
10968
#define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27)
sys/dev/ic/qwzreg.h
10969
#define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28)
sys/dev/ic/qwzreg.h
10970
#define RX_MPDU_START_INFO6_DIRECTED BIT(29)
sys/dev/ic/qwzreg.h
10971
#define RX_MPDU_START_INFO6_AMSDU_PRESENT BIT(30)
sys/dev/ic/qwzreg.h
10975
#define RX_MPDU_START_INFO7_PRIORITY_VALID BIT(17)
sys/dev/ic/qwzreg.h
10978
#define RX_MPDU_START_INFO8_AUTH_TO_SEND_WDS BIT(0)
sys/dev/ic/qwzreg.h
11011
#define QCN9274_MPDU_START_SELECT_MPDU_START_TAG BIT(0)
sys/dev/ic/qwzreg.h
11012
#define QCN9274_MPDU_START_SELECT_INFO0_REO_QUEUE_DESC_LO BIT(1)
sys/dev/ic/qwzreg.h
11013
#define QCN9274_MPDU_START_SELECT_INFO1_PN_31_0 BIT(2)
sys/dev/ic/qwzreg.h
11014
#define QCN9274_MPDU_START_SELECT_PN_95_32 BIT(3)
sys/dev/ic/qwzreg.h
11015
#define QCN9274_MPDU_START_SELECT_PN_127_96_INFO2 BIT(4)
sys/dev/ic/qwzreg.h
11016
#define QCN9274_MPDU_START_SELECT_PEER_MDATA_INFO3_PHY_PPDU_ID BIT(5)
sys/dev/ic/qwzreg.h
11017
#define QCN9274_MPDU_START_SELECT_AST_IDX_SW_PEER_ID_INFO4 BIT(6)
sys/dev/ic/qwzreg.h
11018
#define QCN9274_MPDU_START_SELECT_INFO5_INFO6 BIT(7)
sys/dev/ic/qwzreg.h
11019
#define QCN9274_MPDU_START_SELECT_FRAME_CTRL_DURATION_ADDR1_31_0 BIT(8)
sys/dev/ic/qwzreg.h
11020
#define QCN9274_MPDU_START_SELECT_ADDR2_47_0_ADDR1_47_32 BIT(9)
sys/dev/ic/qwzreg.h
11021
#define QCN9274_MPDU_START_SELECT_ADDR3_47_0_SEQ_CTRL BIT(10)
sys/dev/ic/qwzreg.h
11022
#define QCN9274_MPDU_START_SELECT_ADDR4_47_0_QOS_CTRL BIT(11)
sys/dev/ic/qwzreg.h
11023
#define QCN9274_MPDU_START_SELECT_HT_CTRL_INFO7 BIT(12)
sys/dev/ic/qwzreg.h
11024
#define QCN9274_MPDU_START_SELECT_ML_ADDR1_47_0_ML_ADDR2_15_0 BIT(13)
sys/dev/ic/qwzreg.h
11025
#define QCN9274_MPDU_START_SELECT_ML_ADDR2_47_16_INFO8 BIT(14)
sys/dev/ic/qwzreg.h
11026
#define QCN9274_MPDU_START_SELECT_RES_0_RES_1 BIT(15)
sys/dev/ic/qwzreg.h
11535
#define RX_MSDU_END_INFO2_CCND_TRUNCATE BIT(14)
sys/dev/ic/qwzreg.h
11536
#define RX_MSDU_END_INFO2_CCND_CCE_DIS BIT(15)
sys/dev/ic/qwzreg.h
11540
#define RX_MSDU_END_INFO3_DA_OFFSET_VALID BIT(12)
sys/dev/ic/qwzreg.h
11541
#define RX_MSDU_END_INFO3_SA_OFFSET_VALID BIT(13)
sys/dev/ic/qwzreg.h
11544
#define RX_MSDU_END_INFO4_LRO_ELIGIBLE BIT(9)
sys/dev/ic/qwzreg.h
11546
#define RX_MSDU_END_INFO5_SA_IDX_TIMEOUT BIT(0)
sys/dev/ic/qwzreg.h
11547
#define RX_MSDU_END_INFO5_DA_IDX_TIMEOUT BIT(1)
sys/dev/ic/qwzreg.h
11548
#define RX_MSDU_END_INFO5_TO_DS BIT(2)
sys/dev/ic/qwzreg.h
11550
#define RX_MSDU_END_INFO5_SA_IS_VALID BIT(7)
sys/dev/ic/qwzreg.h
11551
#define RX_MSDU_END_INFO5_DA_IS_VALID BIT(8)
sys/dev/ic/qwzreg.h
11552
#define RX_MSDU_END_INFO5_DA_IS_MCBC BIT(9)
sys/dev/ic/qwzreg.h
11554
#define RX_MSDU_END_INFO5_FIRST_MSDU BIT(12)
sys/dev/ic/qwzreg.h
11555
#define RX_MSDU_END_INFO5_LAST_MSDU BIT(13)
sys/dev/ic/qwzreg.h
11556
#define RX_MSDU_END_INFO5_FROM_DS BIT(14)
sys/dev/ic/qwzreg.h
11557
#define RX_MSDU_END_INFO5_IP_CHKSUM_FAIL_COPY BIT(15)
sys/dev/ic/qwzreg.h
11559
#define RX_MSDU_END_INFO6_MSDU_DROP BIT(0)
sys/dev/ic/qwzreg.h
11562
#define RX_MSDU_END_INFO6_USE_PPE BIT(26)
sys/dev/ic/qwzreg.h
11564
#define RX_MSDU_END_INFO6_VLAN_CTAG_STRIPPED BIT(29)
sys/dev/ic/qwzreg.h
11565
#define RX_MSDU_END_INFO6_VLAN_STAG_STRIPPED BIT(30)
sys/dev/ic/qwzreg.h
11566
#define RX_MSDU_END_INFO6_FRAGMENT_FLAG BIT(31)
sys/dev/ic/qwzreg.h
11569
#define RX_MSDU_END_INFO7_FLOW_AGGR_CONTN BIT(8)
sys/dev/ic/qwzreg.h
11570
#define RX_MSDU_END_INFO7_FISA_TIMEOUT BIT(9)
sys/dev/ic/qwzreg.h
11572
#define RX_MSDU_END_INFO7_TCPUDP_CSUM_FAIL_CPY BIT(10)
sys/dev/ic/qwzreg.h
11573
#define RX_MSDU_END_INFO7_MSDU_LIMIT_ERROR BIT(11)
sys/dev/ic/qwzreg.h
11574
#define RX_MSDU_END_INFO7_FLOW_IDX_TIMEOUT BIT(12)
sys/dev/ic/qwzreg.h
11575
#define RX_MSDU_END_INFO7_FLOW_IDX_INVALID BIT(13)
sys/dev/ic/qwzreg.h
11576
#define RX_MSDU_END_INFO7_CCE_MATCH BIT(14)
sys/dev/ic/qwzreg.h
11577
#define RX_MSDU_END_INFO7_AMSDU_PARSER_ERR BIT(15)
sys/dev/ic/qwzreg.h
11582
#define RX_MSDU_END_INFO9_PRIORITY_VALID BIT(15)
sys/dev/ic/qwzreg.h
11583
#define RX_MSDU_END_INFO9_INRA_BSS BIT(16)
sys/dev/ic/qwzreg.h
11585
#define RX_MSDU_END_INFO9_MCAST_ECHO BIT(19)
sys/dev/ic/qwzreg.h
11586
#define RX_MSDU_END_INFO9_WDS_LEARN_EVENT BIT(20)
sys/dev/ic/qwzreg.h
11587
#define RX_MSDU_END_INFO9_WDS_ROAM_EVENT BIT(21)
sys/dev/ic/qwzreg.h
11588
#define RX_MSDU_END_INFO9_WDS_KEEP_ALIVE_EVENT BIT(22)
sys/dev/ic/qwzreg.h
11591
#define RX_MSDU_END_INFO10_STBC BIT(14)
sys/dev/ic/qwzreg.h
11592
#define RX_MSDU_END_INFO10_IPSEC_ESP BIT(15)
sys/dev/ic/qwzreg.h
11594
#define RX_MSDU_END_INFO10_IPSEC_AH BIT(23)
sys/dev/ic/qwzreg.h
11599
#define RX_MSDU_END_INFO11_IPV4 BIT(10)
sys/dev/ic/qwzreg.h
11600
#define RX_MSDU_END_INFO11_IPV6 BIT(11)
sys/dev/ic/qwzreg.h
11601
#define RX_MSDU_END_INFO11_TCP BIT(12)
sys/dev/ic/qwzreg.h
11602
#define RX_MSDU_END_INFO11_UDP BIT(13)
sys/dev/ic/qwzreg.h
11603
#define RX_MSDU_END_INFO11_IP_FRAG BIT(14)
sys/dev/ic/qwzreg.h
11604
#define RX_MSDU_END_INFO11_TCP_ONLY_ACK BIT(15)
sys/dev/ic/qwzreg.h
11605
#define RX_MSDU_END_INFO11_DA_IS_BCAST_MCAST BIT(16)
sys/dev/ic/qwzreg.h
11607
#define RX_MSDU_END_INFO11_IP_FIXED_HDR_VALID BIT(19)
sys/dev/ic/qwzreg.h
11608
#define RX_MSDU_END_INFO11_IP_EXTN_HDR_VALID BIT(20)
sys/dev/ic/qwzreg.h
11609
#define RX_MSDU_END_INFO11_IP_TCP_UDP_HDR_VALID BIT(21)
sys/dev/ic/qwzreg.h
11610
#define RX_MSDU_END_INFO11_MESH_CTRL_PRESENT BIT(22)
sys/dev/ic/qwzreg.h
11611
#define RX_MSDU_END_INFO11_LDPC BIT(23)
sys/dev/ic/qwzreg.h
11622
#define RX_MSDU_END_INFO12_MIMO_DONE_COPY BIT(31)
sys/dev/ic/qwzreg.h
11624
#define RX_MSDU_END_INFO13_FIRST_MPDU BIT(0)
sys/dev/ic/qwzreg.h
11625
#define RX_MSDU_END_INFO13_MCAST_BCAST BIT(2)
sys/dev/ic/qwzreg.h
11626
#define RX_MSDU_END_INFO13_AST_IDX_NOT_FOUND BIT(3)
sys/dev/ic/qwzreg.h
11627
#define RX_MSDU_END_INFO13_AST_IDX_TIMEDOUT BIT(4)
sys/dev/ic/qwzreg.h
11628
#define RX_MSDU_END_INFO13_POWER_MGMT BIT(5)
sys/dev/ic/qwzreg.h
11629
#define RX_MSDU_END_INFO13_NON_QOS BIT(6)
sys/dev/ic/qwzreg.h
11630
#define RX_MSDU_END_INFO13_NULL_DATA BIT(7)
sys/dev/ic/qwzreg.h
11631
#define RX_MSDU_END_INFO13_MGMT_TYPE BIT(8)
sys/dev/ic/qwzreg.h
11632
#define RX_MSDU_END_INFO13_CTRL_TYPE BIT(9)
sys/dev/ic/qwzreg.h
11633
#define RX_MSDU_END_INFO13_MORE_DATA BIT(10)
sys/dev/ic/qwzreg.h
11634
#define RX_MSDU_END_INFO13_EOSP BIT(11)
sys/dev/ic/qwzreg.h
11635
#define RX_MSDU_END_INFO13_A_MSDU_ERROR BIT(12)
sys/dev/ic/qwzreg.h
11636
#define RX_MSDU_END_INFO13_ORDER BIT(14)
sys/dev/ic/qwzreg.h
11637
#define RX_MSDU_END_INFO13_OVERFLOW_ERR BIT(16)
sys/dev/ic/qwzreg.h
11638
#define RX_MSDU_END_INFO13_MSDU_LEN_ERR BIT(17)
sys/dev/ic/qwzreg.h
11639
#define RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL BIT(18)
sys/dev/ic/qwzreg.h
11640
#define RX_MSDU_END_INFO13_IP_CKSUM_FAIL BIT(19)
sys/dev/ic/qwzreg.h
11641
#define RX_MSDU_END_INFO13_SA_IDX_INVALID BIT(20)
sys/dev/ic/qwzreg.h
11642
#define RX_MSDU_END_INFO13_DA_IDX_INVALID BIT(21)
sys/dev/ic/qwzreg.h
11643
#define RX_MSDU_END_INFO13_AMSDU_ADDR_MISMATCH BIT(22)
sys/dev/ic/qwzreg.h
11644
#define RX_MSDU_END_INFO13_RX_IN_TX_DECRYPT_BYP BIT(23)
sys/dev/ic/qwzreg.h
11645
#define RX_MSDU_END_INFO13_ENCRYPT_REQUIRED BIT(24)
sys/dev/ic/qwzreg.h
11646
#define RX_MSDU_END_INFO13_DIRECTED BIT(25)
sys/dev/ic/qwzreg.h
11647
#define RX_MSDU_END_INFO13_BUFFER_FRAGMENT BIT(26)
sys/dev/ic/qwzreg.h
11648
#define RX_MSDU_END_INFO13_MPDU_LEN_ERR BIT(27)
sys/dev/ic/qwzreg.h
11649
#define RX_MSDU_END_INFO13_TKIP_MIC_ERR BIT(28)
sys/dev/ic/qwzreg.h
11650
#define RX_MSDU_END_INFO13_DECRYPT_ERR BIT(29)
sys/dev/ic/qwzreg.h
11651
#define RX_MSDU_END_INFO13_UNDECRYPT_FRAME_ERR BIT(30)
sys/dev/ic/qwzreg.h
11652
#define RX_MSDU_END_INFO13_FCS_ERR BIT(31)
sys/dev/ic/qwzreg.h
11654
#define RX_MSDU_END_INFO13_WIFI_PARSER_ERR BIT(15)
sys/dev/ic/qwzreg.h
11657
#define RX_MSDU_END_INFO14_RX_BITMAP_NOT_UPDED BIT(13)
sys/dev/ic/qwzreg.h
11658
#define RX_MSDU_END_INFO14_MSDU_DONE BIT(31)
sys/dev/ic/qwzreg.h
11706
#define QCN9274_MSDU_END_SELECT_MSDU_END_TAG BIT(0)
sys/dev/ic/qwzreg.h
11707
#define QCN9274_MSDU_END_SELECT_INFO0_PHY_PPDUID_IP_HDR_CSUM_INFO1 BIT(1)
sys/dev/ic/qwzreg.h
11708
#define QCN9274_MSDU_END_SELECT_INFO2_CUMULATIVE_CSUM_RULE_IND_0 BIT(2)
sys/dev/ic/qwzreg.h
11709
#define QCN9274_MSDU_END_SELECT_IPV6_OP_CRC_INFO3_TYPE13 BIT(3)
sys/dev/ic/qwzreg.h
11710
#define QCN9274_MSDU_END_SELECT_RULE_IND_1_TCP_SEQ_NUM BIT(4)
sys/dev/ic/qwzreg.h
11711
#define QCN9274_MSDU_END_SELECT_TCP_ACK_NUM_INFO4_WINDOW_SIZE BIT(5)
sys/dev/ic/qwzreg.h
11712
#define QCN9274_MSDU_END_SELECT_SA_SW_PER_ID_INFO5_SA_DA_ID BIT(6)
sys/dev/ic/qwzreg.h
11713
#define QCN9274_MSDU_END_SELECT_INFO6_FSE_METADATA BIT(7)
sys/dev/ic/qwzreg.h
11714
#define QCN9274_MSDU_END_SELECT_CCE_MDATA_TCP_UDP_CSUM_INFO7_IP_LEN BIT(8)
sys/dev/ic/qwzreg.h
11715
#define QCN9274_MSDU_END_SELECT_INFO8_INFO9 BIT(9)
sys/dev/ic/qwzreg.h
11716
#define QCN9274_MSDU_END_SELECT_INFO10_INFO11 BIT(10)
sys/dev/ic/qwzreg.h
11717
#define QCN9274_MSDU_END_SELECT_VLAN_CTAG_STAG_CI_PEER_MDATA BIT(11)
sys/dev/ic/qwzreg.h
11718
#define QCN9274_MSDU_END_SELECT_INFO12_AND_FLOW_ID_TOEPLITZ BIT(12)
sys/dev/ic/qwzreg.h
11719
#define QCN9274_MSDU_END_SELECT_PPDU_START_TS_63_32_PHY_MDATA BIT(13)
sys/dev/ic/qwzreg.h
11720
#define QCN9274_MSDU_END_SELECT_PPDU_START_TS_31_0_TOEPLITZ_HASH_2_4 BIT(14)
sys/dev/ic/qwzreg.h
11721
#define QCN9274_MSDU_END_SELECT_RES0_SA_47_0 BIT(15)
sys/dev/ic/qwzreg.h
11722
#define QCN9274_MSDU_END_SELECT_INFO13_INFO14 BIT(16)
sys/dev/ic/qwzreg.h
12412
#define HTT_TCL_META_DATA_TYPE BIT(0)
sys/dev/ic/qwzreg.h
12413
#define HTT_TCL_META_DATA_VALID_HTT BIT(1)
sys/dev/ic/qwzreg.h
12418
#define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
sys/dev/ic/qwzreg.h
12434
#define HTT_TX_WBM_COMP_INFO2_VALID BIT(21)
sys/dev/ic/qwzreg.h
12609
#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
sys/dev/ic/qwzreg.h
12610
#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
sys/dev/ic/qwzreg.h
12611
#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
sys/dev/ic/qwzreg.h
12612
#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
sys/dev/ic/qwzreg.h
12615
#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
sys/dev/ic/qwzreg.h
12619
#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16)
sys/dev/ic/qwzreg.h
12620
#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
sys/dev/ic/qwzreg.h
12676
#define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8)
sys/dev/ic/qwzreg.h
12700
#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
sys/dev/ic/qwzreg.h
12701
| BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
sys/dev/ic/qwzreg.h
12702
| BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
sys/dev/ic/qwzreg.h
12703
| BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
sys/dev/ic/qwzreg.h
12704
| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
sys/dev/ic/qwzreg.h
12705
| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
sys/dev/ic/qwzreg.h
12706
| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
sys/dev/ic/qwzreg.h
12707
| BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
sys/dev/ic/qwzreg.h
12709
#define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
sys/dev/ic/qwzreg.h
12710
BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
sys/dev/ic/qwzreg.h
12711
BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
sys/dev/ic/qwzreg.h
12712
BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
sys/dev/ic/qwzreg.h
12713
BIT(HTT_PPDU_STATS_TAG_INFO) | \
sys/dev/ic/qwzreg.h
12714
BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
sys/dev/ic/qwzreg.h
12790
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
sys/dev/ic/qwzreg.h
12791
#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
sys/dev/ic/qwzreg.h
12796
HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
sys/dev/ic/qwzreg.h
12797
HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
sys/dev/ic/qwzreg.h
12798
HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
sys/dev/ic/qwzreg.h
12799
HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
sys/dev/ic/qwzreg.h
12800
HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
sys/dev/ic/qwzreg.h
12801
HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
sys/dev/ic/qwzreg.h
12802
HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
sys/dev/ic/qwzreg.h
12803
HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
sys/dev/ic/qwzreg.h
12804
HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
sys/dev/ic/qwzreg.h
12805
HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
sys/dev/ic/qwzreg.h
12806
HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
sys/dev/ic/qwzreg.h
12807
HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
sys/dev/ic/qwzreg.h
12808
HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
sys/dev/ic/qwzreg.h
12812
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
sys/dev/ic/qwzreg.h
12813
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
sys/dev/ic/qwzreg.h
12814
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
sys/dev/ic/qwzreg.h
12815
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
sys/dev/ic/qwzreg.h
12816
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
sys/dev/ic/qwzreg.h
12817
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
sys/dev/ic/qwzreg.h
12818
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
sys/dev/ic/qwzreg.h
12819
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
sys/dev/ic/qwzreg.h
12820
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
sys/dev/ic/qwzreg.h
12821
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
sys/dev/ic/qwzreg.h
12822
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
sys/dev/ic/qwzreg.h
12823
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
sys/dev/ic/qwzreg.h
12824
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
sys/dev/ic/qwzreg.h
12825
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
sys/dev/ic/qwzreg.h
12826
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
sys/dev/ic/qwzreg.h
12827
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
sys/dev/ic/qwzreg.h
12828
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
sys/dev/ic/qwzreg.h
12829
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
sys/dev/ic/qwzreg.h
12830
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
sys/dev/ic/qwzreg.h
12831
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
sys/dev/ic/qwzreg.h
12832
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
sys/dev/ic/qwzreg.h
12833
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
sys/dev/ic/qwzreg.h
12834
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
sys/dev/ic/qwzreg.h
12835
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
sys/dev/ic/qwzreg.h
12836
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
sys/dev/ic/qwzreg.h
12837
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
sys/dev/ic/qwzreg.h
12838
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
sys/dev/ic/qwzreg.h
12839
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
sys/dev/ic/qwzreg.h
12840
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
sys/dev/ic/qwzreg.h
12841
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
sys/dev/ic/qwzreg.h
12845
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
sys/dev/ic/qwzreg.h
12846
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
sys/dev/ic/qwzreg.h
12847
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
sys/dev/ic/qwzreg.h
12848
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
sys/dev/ic/qwzreg.h
12849
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
sys/dev/ic/qwzreg.h
12850
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
sys/dev/ic/qwzreg.h
12851
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
sys/dev/ic/qwzreg.h
12852
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
sys/dev/ic/qwzreg.h
12853
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
sys/dev/ic/qwzreg.h
12854
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
sys/dev/ic/qwzreg.h
12855
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
sys/dev/ic/qwzreg.h
12856
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
sys/dev/ic/qwzreg.h
12857
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
sys/dev/ic/qwzreg.h
12858
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
sys/dev/ic/qwzreg.h
12859
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
sys/dev/ic/qwzreg.h
12860
HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
sys/dev/ic/qwzreg.h
12861
HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
sys/dev/ic/qwzreg.h
12862
HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
sys/dev/ic/qwzreg.h
12866
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
sys/dev/ic/qwzreg.h
12867
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
sys/dev/ic/qwzreg.h
12868
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
sys/dev/ic/qwzreg.h
12869
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
sys/dev/ic/qwzreg.h
12870
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
sys/dev/ic/qwzreg.h
12871
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
sys/dev/ic/qwzreg.h
12872
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
sys/dev/ic/qwzreg.h
12873
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
sys/dev/ic/qwzreg.h
12874
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
sys/dev/ic/qwzreg.h
12875
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
sys/dev/ic/qwzreg.h
12876
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
sys/dev/ic/qwzreg.h
12877
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
sys/dev/ic/qwzreg.h
12878
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
sys/dev/ic/qwzreg.h
12879
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
sys/dev/ic/qwzreg.h
12880
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
sys/dev/ic/qwzreg.h
12881
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
sys/dev/ic/qwzreg.h
12882
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
sys/dev/ic/qwzreg.h
12883
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
sys/dev/ic/qwzreg.h
12884
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
sys/dev/ic/qwzreg.h
12885
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
sys/dev/ic/qwzreg.h
12886
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
sys/dev/ic/qwzreg.h
12887
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
sys/dev/ic/qwzreg.h
12888
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
sys/dev/ic/qwzreg.h
12889
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
sys/dev/ic/qwzreg.h
12890
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
sys/dev/ic/qwzreg.h
12891
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
sys/dev/ic/qwzreg.h
12892
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
sys/dev/ic/qwzreg.h
12893
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
sys/dev/ic/qwzreg.h
12894
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
sys/dev/ic/qwzreg.h
12895
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
sys/dev/ic/qwzreg.h
12899
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
sys/dev/ic/qwzreg.h
12900
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
sys/dev/ic/qwzreg.h
12901
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
sys/dev/ic/qwzreg.h
12902
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
sys/dev/ic/qwzreg.h
12903
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
sys/dev/ic/qwzreg.h
12904
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
sys/dev/ic/qwzreg.h
12905
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
sys/dev/ic/qwzreg.h
12906
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
sys/dev/ic/qwzreg.h
12907
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
sys/dev/ic/qwzreg.h
12908
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
sys/dev/ic/qwzreg.h
12909
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
sys/dev/ic/qwzreg.h
12910
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
sys/dev/ic/qwzreg.h
12911
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
sys/dev/ic/qwzreg.h
12912
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
sys/dev/ic/qwzreg.h
12913
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
sys/dev/ic/qwzreg.h
12914
HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
sys/dev/ic/qwzreg.h
12915
HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
sys/dev/ic/qwzreg.h
12916
HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
sys/dev/ic/qwzreg.h
12920
HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
sys/dev/ic/qwzreg.h
12921
HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
sys/dev/ic/qwzreg.h
12922
HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
sys/dev/ic/qwzreg.h
12923
HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
sys/dev/ic/qwzreg.h
12924
HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
sys/dev/ic/qwzreg.h
12925
HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
sys/dev/ic/qwzreg.h
12926
HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
sys/dev/ic/qwzreg.h
12927
HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
sys/dev/ic/qwzreg.h
12928
HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
sys/dev/ic/qwzreg.h
13118
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0)
sys/dev/ic/qwzreg.h
13119
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1)
sys/dev/ic/qwzreg.h
13120
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2)
sys/dev/ic/qwzreg.h
13172
#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
sys/dev/ic/qwzreg.h
13356
#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
sys/dev/ic/qwzreg.h
13360
#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
sys/dev/ic/qwzreg.h
13361
#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
sys/dev/ic/qwzreg.h
13368
#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
sys/dev/ic/qwzreg.h
13369
#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
sys/dev/ic/qwzreg.h
13385
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
sys/dev/ic/qwzreg.h
13386
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
sys/dev/ic/qwzreg.h
13393
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
sys/dev/ic/qwzreg.h
13394
#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
sys/dev/ic/qwzreg.h
13412
#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
sys/dev/ic/qwzreg.h
13415
#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
sys/dev/ic/qwzreg.h
13449
#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
sys/dev/ic/qwzreg.h
13684
#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
sys/dev/ic/qwzreg.h
13769
#define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
sys/dev/ic/qwzreg.h
13790
#define HAL_RX_MPDU_ERR_FCS BIT(0)
sys/dev/ic/qwzreg.h
13791
#define HAL_RX_MPDU_ERR_DECRYPT BIT(1)
sys/dev/ic/qwzreg.h
13792
#define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2)
sys/dev/ic/qwzreg.h
13793
#define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3)
sys/dev/ic/qwzreg.h
13794
#define HAL_RX_MPDU_ERR_OVERFLOW BIT(4)
sys/dev/ic/qwzreg.h
13795
#define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5)
sys/dev/ic/qwzreg.h
13796
#define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6)
sys/dev/ic/qwzreg.h
13797
#define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)
sys/dev/ic/qwzreg.h
204
WMI_HE_AUTORATE_LTF_1X = BIT(0),
sys/dev/ic/qwzreg.h
205
WMI_HE_AUTORATE_LTF_2X = BIT(1),
sys/dev/ic/qwzreg.h
206
WMI_HE_AUTORATE_LTF_4X = BIT(2),
sys/dev/ic/qwzreg.h
209
WMI_AUTORATE_400NS_GI = BIT(8),
sys/dev/ic/qwzreg.h
210
WMI_AUTORATE_800NS_GI = BIT(9),
sys/dev/ic/qwzreg.h
211
WMI_AUTORATE_1600NS_GI = BIT(10),
sys/dev/ic/qwzreg.h
212
WMI_AUTORATE_3200NS_GI = BIT(11),
sys/dev/ic/qwzreg.h
2319
#define ATH12K_11B_SUPPORT BIT(0)
sys/dev/ic/qwzreg.h
2320
#define ATH12K_11G_SUPPORT BIT(1)
sys/dev/ic/qwzreg.h
2321
#define ATH12K_11A_SUPPORT BIT(2)
sys/dev/ic/qwzreg.h
2322
#define ATH12K_11N_SUPPORT BIT(3)
sys/dev/ic/qwzreg.h
2323
#define ATH12K_11AC_SUPPORT BIT(4)
sys/dev/ic/qwzreg.h
2324
#define ATH12K_11AX_SUPPORT BIT(5)
sys/dev/ic/qwzreg.h
2479
#define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5)
sys/dev/ic/qwzreg.h
2480
#define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
sys/dev/ic/qwzreg.h
2481
#define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18)
sys/dev/ic/qwzreg.h
2625
#define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0)
sys/dev/ic/qwzreg.h
2788
#define WMI_VDEV_START_HIDDEN_SSID BIT(0)
sys/dev/ic/qwzreg.h
2789
#define WMI_VDEV_START_PMF_ENABLED BIT(1)
sys/dev/ic/qwzreg.h
2790
#define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3)
sys/dev/ic/qwzreg.h
2791
#define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4)
sys/dev/ic/qwzreg.h
3042
#define REG_RULE_PSD_INFO BIT(0)
sys/dev/ic/qwzreg.h
3045
#define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
sys/dev/ic/qwzreg.h
3046
#define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
sys/dev/ic/qwzreg.h
3047
#define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
sys/dev/ic/qwzreg.h
3048
#define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
sys/dev/ic/qwzreg.h
3056
#define HECAP_PHY_SU_BFER BIT(7)
sys/dev/ic/qwzreg.h
3057
#define HECAP_PHY_SU_BFEE BIT(0)
sys/dev/ic/qwzreg.h
3058
#define HECAP_PHY_MU_BFER BIT(1)
sys/dev/ic/qwzreg.h
3059
#define HECAP_PHY_UL_MUMIMO BIT(6)
sys/dev/ic/qwzreg.h
3060
#define HECAP_PHY_UL_MUOFDMA BIT(7)
sys/dev/ic/qwzreg.h
3077
#define HE_MODE_SU_TX_BFEE BIT(0)
sys/dev/ic/qwzreg.h
3078
#define HE_MODE_SU_TX_BFER BIT(1)
sys/dev/ic/qwzreg.h
3079
#define HE_MODE_MU_TX_BFEE BIT(2)
sys/dev/ic/qwzreg.h
3080
#define HE_MODE_MU_TX_BFER BIT(3)
sys/dev/ic/qwzreg.h
3081
#define HE_MODE_DL_OFDMA BIT(4)
sys/dev/ic/qwzreg.h
3082
#define HE_MODE_UL_OFDMA BIT(5)
sys/dev/ic/qwzreg.h
3083
#define HE_MODE_UL_MUMIMO BIT(6)
sys/dev/ic/qwzreg.h
3099
#define HE_VHT_SOUNDING_MODE BIT(0)
sys/dev/ic/qwzreg.h
3101
#define HE_SU_MU_SOUNDING_MODE BIT(2)
sys/dev/ic/qwzreg.h
3103
#define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3)
sys/dev/ic/qwzreg.h
3338
WMI_SCAN_EVENT_STARTED = BIT(0),
sys/dev/ic/qwzreg.h
3339
WMI_SCAN_EVENT_COMPLETED = BIT(1),
sys/dev/ic/qwzreg.h
3340
WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2),
sys/dev/ic/qwzreg.h
3341
WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3),
sys/dev/ic/qwzreg.h
3342
WMI_SCAN_EVENT_DEQUEUED = BIT(4),
sys/dev/ic/qwzreg.h
3344
WMI_SCAN_EVENT_PREEMPTED = BIT(5),
sys/dev/ic/qwzreg.h
3345
WMI_SCAN_EVENT_START_FAILED = BIT(6),
sys/dev/ic/qwzreg.h
3346
WMI_SCAN_EVENT_RESTARTED = BIT(7),
sys/dev/ic/qwzreg.h
3347
WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8),
sys/dev/ic/qwzreg.h
3348
WMI_SCAN_EVENT_SUSPENDED = BIT(9),
sys/dev/ic/qwzreg.h
3349
WMI_SCAN_EVENT_RESUMED = BIT(10),
sys/dev/ic/qwzreg.h
3350
WMI_SCAN_EVENT_MAX = BIT(15),
sys/dev/ic/qwzreg.h
3601
#define WMI_CHAN_INFO_HT40_PLUS BIT(6)
sys/dev/ic/qwzreg.h
3602
#define WMI_CHAN_INFO_PASSIVE BIT(7)
sys/dev/ic/qwzreg.h
3603
#define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8)
sys/dev/ic/qwzreg.h
3604
#define WMI_CHAN_INFO_AP_DISABLED BIT(9)
sys/dev/ic/qwzreg.h
3605
#define WMI_CHAN_INFO_DFS BIT(10)
sys/dev/ic/qwzreg.h
3606
#define WMI_CHAN_INFO_ALLOW_HT BIT(11)
sys/dev/ic/qwzreg.h
3607
#define WMI_CHAN_INFO_ALLOW_VHT BIT(12)
sys/dev/ic/qwzreg.h
3608
#define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13)
sys/dev/ic/qwzreg.h
3609
#define WMI_CHAN_INFO_HALF_RATE BIT(14)
sys/dev/ic/qwzreg.h
3610
#define WMI_CHAN_INFO_QUARTER_RATE BIT(15)
sys/dev/ic/qwzreg.h
3611
#define WMI_CHAN_INFO_DFS_FREQ2 BIT(16)
sys/dev/ic/qwzreg.h
3612
#define WMI_CHAN_INFO_ALLOW_HE BIT(17)
sys/dev/ic/qwzreg.h
3613
#define WMI_CHAN_INFO_PSC BIT(18)
sys/dev/ic/qwzreg.h
3673
WMI_REQUEST_PEER_STAT = BIT(0),
sys/dev/ic/qwzreg.h
3674
WMI_REQUEST_AP_STAT = BIT(1),
sys/dev/ic/qwzreg.h
3675
WMI_REQUEST_PDEV_STAT = BIT(2),
sys/dev/ic/qwzreg.h
3676
WMI_REQUEST_VDEV_STAT = BIT(3),
sys/dev/ic/qwzreg.h
3677
WMI_REQUEST_BCNFLT_STAT = BIT(4),
sys/dev/ic/qwzreg.h
3678
WMI_REQUEST_VDEV_RATE_STAT = BIT(5),
sys/dev/ic/qwzreg.h
3679
WMI_REQUEST_INST_STAT = BIT(6),
sys/dev/ic/qwzreg.h
3680
WMI_REQUEST_MIB_STAT = BIT(7),
sys/dev/ic/qwzreg.h
3681
WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8),
sys/dev/ic/qwzreg.h
3682
WMI_REQUEST_CONGESTION_STAT = BIT(9),
sys/dev/ic/qwzreg.h
3683
WMI_REQUEST_PEER_EXTD_STAT = BIT(10),
sys/dev/ic/qwzreg.h
3684
WMI_REQUEST_BCN_STAT = BIT(11),
sys/dev/ic/qwzreg.h
3685
WMI_REQUEST_BCN_STAT_RESET = BIT(12),
sys/dev/ic/qwzreg.h
3686
WMI_REQUEST_PEER_EXTD2_STAT = BIT(13),
sys/dev/ic/qwzreg.h
3924
#define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20)
sys/dev/ic/qwzreg.h
4285
#define REGULATORY_CHAN_DISABLED BIT(0)
sys/dev/ic/qwzreg.h
4286
#define REGULATORY_CHAN_NO_IR BIT(1)
sys/dev/ic/qwzreg.h
4287
#define REGULATORY_CHAN_RADAR BIT(3)
sys/dev/ic/qwzreg.h
4288
#define REGULATORY_CHAN_NO_OFDM BIT(6)
sys/dev/ic/qwzreg.h
4289
#define REGULATORY_CHAN_INDOOR_ONLY BIT(9)
sys/dev/ic/qwzreg.h
4291
#define REGULATORY_CHAN_NO_HT40 BIT(4)
sys/dev/ic/qwzreg.h
4292
#define REGULATORY_CHAN_NO_80MHZ BIT(7)
sys/dev/ic/qwzreg.h
4293
#define REGULATORY_CHAN_NO_160MHZ BIT(8)
sys/dev/ic/qwzreg.h
4294
#define REGULATORY_CHAN_NO_20MHZ BIT(11)
sys/dev/ic/qwzreg.h
4295
#define REGULATORY_CHAN_NO_10MHZ BIT(12)
sys/dev/ic/qwzreg.h
5470
#define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8)
sys/dev/ic/qwzreg.h
5471
#define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9)
sys/dev/ic/qwzreg.h
5472
#define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10)
sys/dev/ic/qwzreg.h
5473
#define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11)
sys/dev/ic/qwzreg.h
5875
WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0),
sys/dev/ic/qwzreg.h
5876
WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1),
sys/dev/ic/qwzreg.h
6139
#define WMI_NLO_CONFIG_STOP BIT(0)
sys/dev/ic/qwzreg.h
6140
#define WMI_NLO_CONFIG_START BIT(1)
sys/dev/ic/qwzreg.h
6141
#define WMI_NLO_CONFIG_RESET BIT(2)
sys/dev/ic/qwzreg.h
6142
#define WMI_NLO_CONFIG_SLOW_SCAN BIT(4)
sys/dev/ic/qwzreg.h
6143
#define WMI_NLO_CONFIG_FAST_SCAN BIT(5)
sys/dev/ic/qwzreg.h
6144
#define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6)
sys/dev/ic/qwzreg.h
6149
#define WMI_NLO_CONFIG_ENLO BIT(7)
sys/dev/ic/qwzreg.h
6150
#define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8)
sys/dev/ic/qwzreg.h
6151
#define WMI_NLO_CONFIG_ENLO_RESET BIT(9)
sys/dev/ic/qwzreg.h
6152
#define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10)
sys/dev/ic/qwzreg.h
6153
#define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11)
sys/dev/ic/qwzreg.h
6154
#define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12)
sys/dev/ic/qwzreg.h
6155
#define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13)
sys/dev/ic/qwzreg.h
6282
#define WMI_ARPOL_FLAGS_VALID BIT(0)
sys/dev/ic/qwzreg.h
6283
#define WMI_ARPOL_FLAGS_MAC_VALID BIT(1)
sys/dev/ic/qwzreg.h
6284
#define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2)
sys/dev/ic/qwzreg.h
6294
#define WMI_NSOL_FLAGS_VALID BIT(0)
sys/dev/ic/qwzreg.h
6295
#define WMI_NSOL_FLAGS_MAC_VALID BIT(1)
sys/dev/ic/qwzreg.h
6296
#define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2)
sys/dev/ic/qwzreg.h
6297
#define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3)
sys/dev/ic/qwzreg.h
7532
#define HAL_WBM_SW_COOKIE_CFG_ALIGN BIT(18)
sys/dev/ic/qwzreg.h
7533
#define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN BIT(0)
sys/dev/ic/qwzreg.h
7534
#define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN BIT(1)
sys/dev/ic/qwzreg.h
7535
#define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN BIT(3)
sys/dev/ic/qwzreg.h
7537
#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1)
sys/dev/ic/qwzreg.h
7538
#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2)
sys/dev/ic/qwzreg.h
7539
#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3)
sys/dev/ic/qwzreg.h
7540
#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4)
sys/dev/ic/qwzreg.h
7541
#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5)
sys/dev/ic/qwzreg.h
7542
#define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8)
sys/dev/ic/qwzreg.h
7548
#define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0)
sys/dev/ic/qwzreg.h
7549
#define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1)
sys/dev/ic/qwzreg.h
7550
#define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
sys/dev/ic/qwzreg.h
7551
#define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4)
sys/dev/ic/qwzreg.h
7552
#define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5)
sys/dev/ic/qwzreg.h
7553
#define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6)
sys/dev/ic/qwzreg.h
7557
#define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
sys/dev/ic/qwzreg.h
7559
#define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(23)
sys/dev/ic/qwzreg.h
7575
#define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
sys/dev/ic/qwzreg.h
7576
#define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4)
sys/dev/ic/qwzreg.h
7577
#define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5)
sys/dev/ic/qwzreg.h
7578
#define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6)
sys/dev/ic/qwzreg.h
7581
#define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
sys/dev/ic/qwzreg.h
7585
#define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2)
sys/dev/ic/qwzreg.h
7586
#define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
sys/dev/ic/qwzreg.h
7590
#define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18)
sys/dev/ic/qwzreg.h
7591
#define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19)
sys/dev/ic/qwzreg.h
7592
#define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20)
sys/dev/ic/qwzreg.h
7602
#define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1)
sys/dev/ic/qwzreg.h
7611
#define HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE BIT(6)
sys/dev/ic/qwzreg.h
7612
#define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE BIT(0)
sys/dev/ic/qwzreg.h
8586
#define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27)
sys/dev/ic/qwzreg.h
8661
#define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11)
sys/dev/ic/qwzreg.h
8663
#define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16)
sys/dev/ic/qwzreg.h
8678
#define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16)
sys/dev/ic/qwzreg.h
8687
#define HAL_REO_CMD_FLG_NEED_STATUS BIT(0)
sys/dev/ic/qwzreg.h
8688
#define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1)
sys/dev/ic/qwzreg.h
8689
#define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2)
sys/dev/ic/qwzreg.h
8690
#define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
sys/dev/ic/qwzreg.h
8691
#define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4)
sys/dev/ic/qwzreg.h
8692
#define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5)
sys/dev/ic/qwzreg.h
8693
#define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6)
sys/dev/ic/qwzreg.h
8694
#define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7)
sys/dev/ic/qwzreg.h
8695
#define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8)
sys/dev/ic/qwzreg.h
8698
#define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8)
sys/dev/ic/qwzreg.h
8699
#define HAL_REO_CMD_UPD0_VLD BIT(9)
sys/dev/ic/qwzreg.h
8700
#define HAL_REO_CMD_UPD0_ALDC BIT(10)
sys/dev/ic/qwzreg.h
8701
#define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11)
sys/dev/ic/qwzreg.h
8702
#define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12)
sys/dev/ic/qwzreg.h
8703
#define HAL_REO_CMD_UPD0_AC BIT(13)
sys/dev/ic/qwzreg.h
8704
#define HAL_REO_CMD_UPD0_BAR BIT(14)
sys/dev/ic/qwzreg.h
8705
#define HAL_REO_CMD_UPD0_RETRY BIT(15)
sys/dev/ic/qwzreg.h
8706
#define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16)
sys/dev/ic/qwzreg.h
8707
#define HAL_REO_CMD_UPD0_OOR_MODE BIT(17)
sys/dev/ic/qwzreg.h
8708
#define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18)
sys/dev/ic/qwzreg.h
8709
#define HAL_REO_CMD_UPD0_PN_CHECK BIT(19)
sys/dev/ic/qwzreg.h
8710
#define HAL_REO_CMD_UPD0_EVEN_PN BIT(20)
sys/dev/ic/qwzreg.h
8711
#define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21)
sys/dev/ic/qwzreg.h
8712
#define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22)
sys/dev/ic/qwzreg.h
8713
#define HAL_REO_CMD_UPD0_PN_SIZE BIT(23)
sys/dev/ic/qwzreg.h
8714
#define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24)
sys/dev/ic/qwzreg.h
8715
#define HAL_REO_CMD_UPD0_SVLD BIT(25)
sys/dev/ic/qwzreg.h
8716
#define HAL_REO_CMD_UPD0_SSN BIT(26)
sys/dev/ic/qwzreg.h
8717
#define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27)
sys/dev/ic/qwzreg.h
8718
#define HAL_REO_CMD_UPD0_PN_ERR BIT(28)
sys/dev/ic/qwzreg.h
8719
#define HAL_REO_CMD_UPD0_PN_VALID BIT(29)
sys/dev/ic/qwzreg.h
8720
#define HAL_REO_CMD_UPD0_PN BIT(30)
sys/dev/ic/qwzreg.h
8723
#define HAL_REO_CMD_UPD1_VLD BIT(16)
sys/dev/ic/qwzreg.h
8725
#define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19)
sys/dev/ic/qwzreg.h
8726
#define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20)
sys/dev/ic/qwzreg.h
8728
#define HAL_REO_CMD_UPD1_BAR BIT(23)
sys/dev/ic/qwzreg.h
8729
#define HAL_REO_CMD_UPD1_RETRY BIT(24)
sys/dev/ic/qwzreg.h
8730
#define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25)
sys/dev/ic/qwzreg.h
8731
#define HAL_REO_CMD_UPD1_OOR_MODE BIT(26)
sys/dev/ic/qwzreg.h
8732
#define HAL_REO_CMD_UPD1_PN_CHECK BIT(27)
sys/dev/ic/qwzreg.h
8733
#define HAL_REO_CMD_UPD1_EVEN_PN BIT(28)
sys/dev/ic/qwzreg.h
8734
#define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29)
sys/dev/ic/qwzreg.h
8735
#define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30)
sys/dev/ic/qwzreg.h
8736
#define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31)
sys/dev/ic/qwzreg.h
8739
#define HAL_REO_CMD_UPD2_SVLD BIT(10)
sys/dev/ic/qwzreg.h
8741
#define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23)
sys/dev/ic/qwzreg.h
8742
#define HAL_REO_CMD_UPD2_PN_ERR BIT(24)
sys/dev/ic/qwzreg.h
8764
#define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8)
sys/dev/ic/qwzreg.h
8806
#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8)
sys/dev/ic/qwzreg.h
8817
#define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8)
sys/dev/ic/qwzreg.h
8818
#define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9)
sys/dev/ic/qwzreg.h
8820
#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12)
sys/dev/ic/qwzreg.h
8821
#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13)
sys/dev/ic/qwzreg.h
8822
#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14)
sys/dev/ic/qwzreg.h
8831
#define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0)
sys/dev/ic/qwzreg.h
8832
#define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1)
sys/dev/ic/qwzreg.h
8835
#define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8)
sys/dev/ic/qwzreg.h
8836
#define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9)
sys/dev/ic/qwzreg.h
8842
#define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16)
sys/dev/ic/qwzreg.h
8843
#define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17)
sys/dev/ic/qwzreg.h
8844
#define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18)
sys/dev/ic/qwzreg.h
8845
#define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19)
sys/dev/ic/qwzreg.h
8846
#define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20)
sys/dev/ic/qwzreg.h
8847
#define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21)
sys/dev/ic/qwzreg.h
8851
#define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19)
sys/dev/ic/qwzreg.h
8852
#define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20)
sys/dev/ic/qwzreg.h
8853
#define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21)
sys/dev/ic/qwzreg.h
9099
#define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12)
sys/dev/ic/qwzreg.h
9100
#define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13)
sys/dev/ic/qwzreg.h
9101
#define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14)
sys/dev/ic/qwzreg.h
9146
#define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4)
sys/dev/ic/qwzreg.h
9189
#define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8)
sys/dev/ic/qwzreg.h
9190
#define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9)
sys/dev/ic/qwzreg.h
9191
#define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10)
sys/dev/ic/qwzreg.h
9192
#define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11)
sys/dev/ic/qwzreg.h
9334
#define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8)
sys/dev/ic/qwzreg.h
9335
#define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9)
sys/dev/ic/qwzreg.h
9336
#define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10)
sys/dev/ic/qwzreg.h
9337
#define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11)
sys/dev/ic/qwzreg.h
9416
#define HAL_TX_RATE_STATS_INFO0_VALID BIT(0)
sys/dev/ic/qwzreg.h
9419
#define HAL_TX_RATE_STATS_INFO0_STBC BIT(7)
sys/dev/ic/qwzreg.h
9420
#define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8)
sys/dev/ic/qwzreg.h
9423
#define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15)
sys/dev/ic/qwzreg.h
9534
#define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31)
sys/dev/ic/qwzreg.h
9540
#define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8)
sys/dev/ic/qwzreg.h
9541
#define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9)
sys/dev/ic/qwzreg.h
9542
#define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10)
sys/dev/ic/qwzreg.h
9543
#define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11)
sys/dev/ic/qwzreg.h
9544
#define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12)
sys/dev/ic/qwzreg.h
9554
#define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17)
sys/dev/ic/qwzreg.h
9797
#define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16)
sys/dev/ic/qwzreg.h
9832
#define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0)
sys/dev/ic/qwzreg.h
9834
#define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3)
sys/dev/ic/qwzreg.h
9835
#define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4)
sys/dev/ic/qwzreg.h
9837
#define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7)
sys/dev/ic/qwzreg.h
9838
#define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8)
sys/dev/ic/qwzreg.h
9839
#define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9)
sys/dev/ic/qwzreg.h
9840
#define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10)
sys/dev/ic/qwzreg.h
9842
#define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19)
sys/dev/ic/qwzreg.h
9843
#define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20)
sys/dev/ic/qwzreg.h
9844
#define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21)
sys/dev/ic/qwzreg.h
9845
#define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22)
sys/dev/ic/qwzreg.h
9847
#define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25)
sys/dev/ic/qwzreg.h
9849
#define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0)
sys/dev/ic/qwzreg.h
9852
#define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21)
sys/dev/ic/qwzreg.h
9853
#define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22)
sys/dev/ic/qwzreg.h
9854
#define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31)
sys/dev/ic/qwzreg.h
9959
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8)
sys/dev/ic/qwzreg.h
9960
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9)
sys/dev/ic/qwzreg.h
9961
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10)
sys/dev/ic/qwzreg.h
9962
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11)
sys/dev/ic/qwzreg.h
9963
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12)
sys/dev/ic/qwzreg.h
9964
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13)
sys/dev/ic/qwzreg.h
9965
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14)
sys/dev/ic/qwzreg.h
9966
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15)
sys/dev/ic/qwzreg.h
9967
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16)
sys/dev/ic/qwzreg.h
9968
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17)
sys/dev/ic/qwzreg.h
9969
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18)
sys/dev/ic/qwzreg.h
9970
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19)
sys/dev/ic/qwzreg.h
9971
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20)
sys/dev/ic/qwzreg.h
9972
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21)
sys/dev/ic/qwzreg.h
9973
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22)
sys/dev/ic/qwzreg.h
9974
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23)
sys/dev/ic/qwzreg.h
9975
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24)
sys/dev/ic/qwzreg.h
9976
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25)
sys/dev/ic/qwzreg.h
9977
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26)
sys/dev/ic/qwzreg.h
9978
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27)
sys/dev/ic/qwzreg.h
9979
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28)
sys/dev/ic/qwzreg.h
9980
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29)
sys/dev/ic/qwzreg.h
9981
#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30)
sys/dev/ic/qwzreg.h
9984
#define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16)
sys/dev/ic/qwzreg.h
9986
#define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19)
sys/dev/ic/qwzreg.h
9987
#define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20)
sys/dev/ic/qwzreg.h
9989
#define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23)
sys/dev/ic/qwzreg.h
9990
#define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24)
sys/dev/ic/qwzreg.h
9991
#define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25)
sys/dev/ic/qwzreg.h
9992
#define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26)
sys/dev/ic/qwzreg.h
9993
#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27)
sys/dev/ic/qwzreg.h
9994
#define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28)
sys/dev/ic/qwzreg.h
9995
#define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29)
sys/dev/ic/qwzreg.h
9996
#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30)
sys/dev/ic/qwzreg.h
9997
#define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31)
sys/dev/ic/qwzvar.h
147
#define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0)
sys/dev/ic/qwzvar.h
148
#define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1)
sys/dev/ic/qwzvar.h
149
#define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2)
sys/dev/ic/qwzvar.h
150
#define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3)
sys/dev/ic/qwzvar.h
151
#define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4)
sys/dev/ic/qwzvar.h
152
#define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5)
sys/dev/ic/qwzvar.h
153
#define HAL_TX_STATUS_FLAGS_OFDMA BIT(6)
sys/dev/ic/rtwreg.h
135
#define RTW8185_RR_MAX BIT(7, 4)
sys/dev/ic/rtwreg.h
148
#define RTW8185_RR_MIN_MASK BIT(3, 0)
sys/dev/pci/drm/amd/amdgpu/aldebaran.c
259
if (ip_block_mask & BIT(AMD_IP_BLOCK_TYPE_IH)) {
sys/dev/pci/drm/amd/amdgpu/aldebaran.c
76
uint32_t ip_block_mask = BIT(AMD_IP_BLOCK_TYPE_GFX) |
sys/dev/pci/drm/amd/amdgpu/aldebaran.c
77
BIT(AMD_IP_BLOCK_TYPE_SDMA);
sys/dev/pci/drm/amd/amdgpu/aldebaran.c
80
ip_block_mask |= BIT(AMD_IP_BLOCK_TYPE_IH);
sys/dev/pci/drm/amd/amdgpu/aldebaran.c
95
ip_block = BIT(adev->ip_blocks[i].version->type);
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
609
if ((type < 0) || (!(BIT(type) & handle->mask)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
177
BIT(AMD_IP_BLOCK_TYPE_GMC) | BIT(AMD_IP_BLOCK_TYPE_SMC) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
178
BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
179
BIT(AMD_IP_BLOCK_TYPE_PSP)
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
138
AMDGPU_DEBUG_VM = BIT(0),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
139
AMDGPU_DEBUG_LARGEBAR = BIT(1),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
140
AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
141
AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
142
AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
143
AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
144
AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
145
AMDGPU_DEBUG_SMU_POOL = BIT(7),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
146
AMDGPU_DEBUG_VM_USERPTR = BIT(8),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
147
AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9),
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
148
AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1285
(BIT(mode) & AMDGPU_ALL_NPS_MASK) != BIT(mode))
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1428
return (((BIT(req_nps_mode) & adev->gmc.supported_nps_modes) ==
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1429
BIT(req_nps_mode)) &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1532
!(BIT(mode - 1) & supp_modes))
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
66
#define AMDGPU_GMC_XNACK_FLAG_CHAIN BIT(0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
81
(BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
82
BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
83
BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE))
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
85
#define AMDGPU_GMC_INIT_RESET_NPS BIT(0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
108
#define AMDGPU_JPEG_CAPS(caps) BIT(AMDGPU_JPEG_##caps)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
137
#define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
138
#define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4127
con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4733
if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4734
con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
817
return adev->ras_hw_enabled & BIT(head->block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
825
return con->features & BIT(head->block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
856
con->features |= BIT(head->block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
859
con->features &= ~BIT(head->block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
962
con->features |= BIT(head->block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
968
con->features &= ~BIT(head->block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
567
if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
246
#define AMDGPU_VCN_CAPS(caps) BIT(AMDGPU_VCN_##caps)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1208
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1210
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1212
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1214
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1216
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1218
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1220
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1222
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1224
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1226
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1228
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1230
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1232
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1234
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1236
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1238
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1240
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1242
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1244
adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
390
(amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk))
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
369
(xcp->ip[ip].inst_mask & BIT(instance)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
370
id_mask |= BIT(i);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
641
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
642
BIT(AMDGPU_DPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
643
BIT(AMDGPU_QPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
644
BIT(AMDGPU_CPX_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
647
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
648
BIT(AMDGPU_TPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
649
BIT(AMDGPU_CPX_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
652
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
653
BIT(AMDGPU_DPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
654
BIT(AMDGPU_CPX_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
657
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
658
BIT(AMDGPU_CPX_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
661
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
662
BIT(AMDGPU_CPX_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
232
if (!num_xcp || !nps_modes || !(xcp_mgr->supp_xcp_modes & BIT(px_mode)))
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
238
*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
242
*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
243
BIT(AMDGPU_NPS2_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
247
*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
248
BIT(AMDGPU_NPS4_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
252
*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
253
BIT(AMDGPU_NPS4_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
255
*nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
259
*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
260
BIT(AMDGPU_NPS4_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
262
*nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
281
if (!(xcp_mgr->supp_xcp_modes & BIT(mode)))
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
352
comp_mode = !!(BIT(nps_mode) & supp_nps_modes);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
381
xcp_mgr->avail_xcp_modes |= BIT(mode);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1563
if (AMDGPU_ALL_NPS_MASK & BIT(i))
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1564
adev->gmc.supported_nps_modes |= BIT(i);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1575
BIT(AMDGPU_NPS1_PARTITION_MODE) |
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1576
BIT(AMDGPU_NPS4_PARTITION_MODE);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1370
mqd->reserved_184 = BIT(15);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
282
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4) & ~BIT(23);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
282
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
251
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
45
#define I2C_X_RESTART BIT(31)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
409
if (pdd->alloc_watch_ids & BIT(watch_id)) {
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
410
pdd->alloc_watch_ids &= ~BIT(watch_id);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
411
pdd->dev->alloc_watch_ids &= ~BIT(watch_id);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
422
owns_watch_id = pdd->alloc_watch_ids & BIT(watch_id);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
153
KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0),
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
2176
((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
2179
((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8728
BIT(DRM_MODE_COLORIMETRY_OPRGB) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8729
BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8730
BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
701
MST_PROBE = BIT(0),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
702
MST_REMOTE_EDID = BIT(1),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
703
MST_ALLOCATE_NEW_PAYLOAD = BIT(2),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
704
MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
182
BIT(AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
183
BIT(AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
184
BIT(AMDGPU_TRANSFER_FUNCTION_PQ_EOTF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
185
BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
186
BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
187
BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
191
BIT(AMDGPU_TRANSFER_FUNCTION_BT709_OETF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
192
BIT(AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
193
BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
194
BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
195
BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
203
BIT(AMDGPU_TRANSFER_FUNCTION_DEFAULT) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
204
BIT(AMDGPU_TRANSFER_FUNCTION_IDENTITY);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
210
if ((transfer_functions & BIT(i)) == 0)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2826
aconnector->mst_status & BIT(i) ? "done" : "not_done");
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1837
unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1838
BIT(DRM_MODE_BLEND_PREMULTI) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1839
BIT(DRM_MODE_BLEND_COVERAGE);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1870
BIT(DRM_COLOR_YCBCR_BT601) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1871
BIT(DRM_COLOR_YCBCR_BT709) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1872
BIT(DRM_COLOR_YCBCR_BT2020),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1873
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1874
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
294
#define SMU_DEBUG_HALT_ON_ERROR BIT(0)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
295
#define SMU_DEBUG_POOL_USE_VRAM BIT(1)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
318
#define OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE BIT(0)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
319
#define OD_OPS_SUPPORT_FAN_CURVE_SET BIT(1)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
320
#define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE BIT(2)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
321
#define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET BIT(3)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
322
#define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE BIT(4)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
323
#define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET BIT(5)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
324
#define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE BIT(6)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
325
#define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET BIT(7)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
326
#define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE BIT(8)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
327
#define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET BIT(9)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
328
#define OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE BIT(10)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
329
#define OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET BIT(11)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
330
#define OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE BIT(12)
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
331
#define OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET BIT(13)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
1306
~BIT(PP_PM_POLICY_XGMI_PLPD);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
469
smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
472
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
476
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
479
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
483
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
527
if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
324
policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT);
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
328
smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
445
~BIT(PP_PM_POLICY_XGMI_PLPD);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
309
policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
313
smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1560
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1566
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1572
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1578
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1584
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1589
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1594
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1760
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1798
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1820
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1842
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1864
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1886
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1907
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1928
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2295
user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2296
BIT(PP_OD_FEATURE_UCLK_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2297
BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2298
BIT(PP_OD_FEATURE_FAN_CURVE_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2299
BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1095
~BIT(PP_PM_POLICY_SOC_PSTATE);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
695
policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
696
BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
697
BIT(SOC_PSTATE_2);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
702
BIT(PP_PM_POLICY_SOC_PSTATE);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
707
policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
708
BIT(XGMI_PLPD_OPTIMIZED);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
712
smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1548
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1554
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1560
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1566
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1572
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1577
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1582
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1748
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1786
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1808
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1830
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1852
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1874
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1895
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1916
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2276
user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2277
BIT(PP_OD_FEATURE_UCLK_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2278
BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2279
BIT(PP_OD_FEATURE_FAN_CURVE_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2280
BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2414
user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2415
BIT(PP_OD_FEATURE_UCLK_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2416
BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2417
BIT(PP_OD_FEATURE_FAN_CURVE_BIT) |
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2418
BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2446
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2451
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2457
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2463
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2469
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2475
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2606
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2644
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2666
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2688
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2710
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2732
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2753
od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1123
if (level < 0 || !(policy->level_mask & BIT(level)))
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1153
if (level < 0 || !(policy->level_mask & BIT(level)))
sys/dev/pci/drm/apple/dcp.c
41
#define APPLE_DCP_COPROC_CPU_CONTROL_RUN BIT(4)
sys/dev/pci/drm/apple/dptxep.h
38
#define DCPDPTX_REMOTE_PORT_CONNECTED BIT(15)
sys/dev/pci/drm/apple/iomfb.h
112
#define IOMFB_SET_BACKGROUND BIT(31)
sys/dev/pci/drm/apple/iomfb_template.c
1302
req->swap.swap_enabled |= BIT(l);
sys/dev/pci/drm/display/drm_dp_helper.c
2537
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
sys/dev/pci/drm/display/drm_dp_helper.c
2539
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
sys/dev/pci/drm/display/drm_dp_helper.c
2541
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
sys/dev/pci/drm/display/drm_dp_helper.c
2543
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
sys/dev/pci/drm/display/drm_dp_helper.c
2545
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
sys/dev/pci/drm/display/drm_dp_helper.c
2547
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
sys/dev/pci/drm/display/drm_dp_helper.c
2549
{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
sys/dev/pci/drm/display/drm_dp_helper.c
2551
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1010
reply->reply_signed = raw->msg[2] & BIT(0);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1020
reply->hdcp_1x_device_present = raw->msg[2] & BIT(4);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1021
reply->hdcp_2x_device_present = raw->msg[2] & BIT(3);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1023
reply->query_capable_device_present = raw->msg[2] & BIT(5);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1024
reply->legacy_device_present = raw->msg[2] & BIT(6);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1025
reply->unauthorizable_device_present = raw->msg[2] & BIT(7);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1027
reply->auth_completed = !!(raw->msg[1] & BIT(3));
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1028
reply->encryption_enabled = !!(raw->msg[1] & BIT(4));
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1029
reply->repeater_present = !!(raw->msg[1] & BIT(5));
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2972
port_mask |= BIT(reply->ports[i].port_number);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2988
if (port_mask & BIT(port->port_num))
sys/dev/pci/drm/display/drm_dp_mst_topology.c
455
buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
457
buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4586
topology_state->payload_mask &= ~BIT(payload->vcpi - 1);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5400
mst_state->payload_mask |= BIT(payload->vcpi - 1);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
596
req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2),
sys/dev/pci/drm/display/drm_dp_mst_topology.c
600
req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5),
sys/dev/pci/drm/display/drm_dp_tunnel.c
1632
return hweight32(stream_mask & (BIT(stream_id) - 1));
sys/dev/pci/drm/display/drm_dp_tunnel.c
1669
tunnel_state->stream_mask | BIT(stream_id));
sys/dev/pci/drm/display/drm_dp_tunnel.c
1681
if (!(tunnel_state->stream_mask & ~BIT(stream_id))) {
sys/dev/pci/drm/display/drm_dp_tunnel.c
1688
tunnel_state->stream_mask & ~BIT(stream_id));
sys/dev/pci/drm/display/drm_dp_tunnel.c
548
#define SKIP_DPRX_CAPS_CHECK BIT(0)
sys/dev/pci/drm/display/drm_dp_tunnel.c
549
#define ALLOW_ALLOCATED_BW_CHANGE BIT(1)
sys/dev/pci/drm/display/drm_hdmi_helper.c
15
return sink_eotf & BIT(output_eotf);
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
408
if (!(connector->hdmi.supported_formats & BIT(format))) {
sys/dev/pci/drm/drm_atomic_helper.c
2072
new_self_refresh_mask |= BIT(i);
sys/dev/pci/drm/drm_atomic_helper.c
659
user_connectors_mask |= BIT(i);
sys/dev/pci/drm/drm_atomic_helper.c
726
BIT(i) & user_connectors_mask);
sys/dev/pci/drm/drm_atomic_helper.c
750
connectors_mask |= BIT(i);
sys/dev/pci/drm/drm_atomic_helper.c
789
if (connectors_mask & BIT(i))
sys/dev/pci/drm/drm_blend.c
337
BIT((ffs(rotation & DRM_MODE_ROTATE_MASK) + 1)
sys/dev/pci/drm/drm_blend.c
587
unsigned int valid_mode_mask = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
sys/dev/pci/drm/drm_blend.c
588
BIT(DRM_MODE_BLEND_PREMULTI) |
sys/dev/pci/drm/drm_blend.c
589
BIT(DRM_MODE_BLEND_COVERAGE);
sys/dev/pci/drm/drm_blend.c
593
((supported_modes & BIT(DRM_MODE_BLEND_PREMULTI)) == 0)))
sys/dev/pci/drm/drm_blend.c
605
if (!(BIT(props[i].type) & supported_modes))
sys/dev/pci/drm/drm_bridge.c
313
BIT(HDMI_COLORSPACE_YUV420));
sys/dev/pci/drm/drm_buddy.c
1226
pages -= BIT(order);
sys/dev/pci/drm/drm_client_modeset.c
670
if (conn_configured & BIT(i))
sys/dev/pci/drm/drm_client_modeset.c
682
conn_configured |= BIT(i);
sys/dev/pci/drm/drm_client_modeset.c
701
conn_configured |= BIT(i);
sys/dev/pci/drm/drm_client_modeset.c
763
conn_configured |= BIT(i);
sys/dev/pci/drm/drm_color_mgmt.c
544
(supported_encodings & -BIT(DRM_COLOR_ENCODING_MAX)) != 0 ||
sys/dev/pci/drm/drm_color_mgmt.c
545
(supported_encodings & BIT(default_encoding)) == 0))
sys/dev/pci/drm/drm_color_mgmt.c
549
(supported_ranges & -BIT(DRM_COLOR_RANGE_MAX)) != 0 ||
sys/dev/pci/drm/drm_color_mgmt.c
550
(supported_ranges & BIT(default_range)) == 0))
sys/dev/pci/drm/drm_color_mgmt.c
555
if ((supported_encodings & BIT(i)) == 0)
sys/dev/pci/drm/drm_color_mgmt.c
574
if ((supported_ranges & BIT(i)) == 0)
sys/dev/pci/drm/drm_connector.c
1379
BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) |
sys/dev/pci/drm/drm_connector.c
1380
BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
sys/dev/pci/drm/drm_connector.c
1381
BIT(DRM_MODE_COLORIMETRY_XVYCC_601) |
sys/dev/pci/drm/drm_connector.c
1382
BIT(DRM_MODE_COLORIMETRY_XVYCC_709) |
sys/dev/pci/drm/drm_connector.c
1383
BIT(DRM_MODE_COLORIMETRY_SYCC_601) |
sys/dev/pci/drm/drm_connector.c
1384
BIT(DRM_MODE_COLORIMETRY_OPYCC_601) |
sys/dev/pci/drm/drm_connector.c
1385
BIT(DRM_MODE_COLORIMETRY_OPRGB) |
sys/dev/pci/drm/drm_connector.c
1386
BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) |
sys/dev/pci/drm/drm_connector.c
1387
BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
sys/dev/pci/drm/drm_connector.c
1388
BIT(DRM_MODE_COLORIMETRY_BT2020_YCC) |
sys/dev/pci/drm/drm_connector.c
1389
BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) |
sys/dev/pci/drm/drm_connector.c
1390
BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER);
sys/dev/pci/drm/drm_connector.c
1397
BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED) |
sys/dev/pci/drm/drm_connector.c
1398
BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT) |
sys/dev/pci/drm/drm_connector.c
1399
BIT(DRM_MODE_COLORIMETRY_OPRGB) |
sys/dev/pci/drm/drm_connector.c
1400
BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) |
sys/dev/pci/drm/drm_connector.c
1401
BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
sys/dev/pci/drm/drm_connector.c
1402
BIT(DRM_MODE_COLORIMETRY_BT601_YCC) |
sys/dev/pci/drm/drm_connector.c
1403
BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
sys/dev/pci/drm/drm_connector.c
1404
BIT(DRM_MODE_COLORIMETRY_XVYCC_601) |
sys/dev/pci/drm/drm_connector.c
1405
BIT(DRM_MODE_COLORIMETRY_XVYCC_709) |
sys/dev/pci/drm/drm_connector.c
1406
BIT(DRM_MODE_COLORIMETRY_SYCC_601) |
sys/dev/pci/drm/drm_connector.c
1407
BIT(DRM_MODE_COLORIMETRY_OPYCC_601) |
sys/dev/pci/drm/drm_connector.c
1408
BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) |
sys/dev/pci/drm/drm_connector.c
1409
BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
sys/dev/pci/drm/drm_connector.c
2269
if (!(supported_tv_modes & BIT(i)))
sys/dev/pci/drm/drm_connector.c
2449
if (!(BIT(i) & scaling_mode_mask))
sys/dev/pci/drm/drm_connector.c
2578
u32 colorspaces = supported_colorspaces | BIT(DRM_MODE_COLORIMETRY_DEFAULT);
sys/dev/pci/drm/drm_connector.c
2591
if ((supported_colorspaces & -BIT(DRM_MODE_COLORIMETRY_COUNT)) != 0) {
sys/dev/pci/drm/drm_connector.c
2599
if ((colorspaces & BIT(i)) == 0)
sys/dev/pci/drm/drm_connector.c
595
if (!supported_formats || !(supported_formats & BIT(HDMI_COLORSPACE_RGB)))
sys/dev/pci/drm/drm_connector.c
598
if (connector->ycbcr_420_allowed != !!(supported_formats & BIT(HDMI_COLORSPACE_YUV420)))
sys/dev/pci/drm/drm_displayid.c
24
.quirks = BIT(QUIRK_IGNORE_CHECKSUM),
sys/dev/pci/drm/drm_displayid.c
86
bool ignore_checksum = iter->quirks & BIT(QUIRK_IGNORE_CHECKSUM);
sys/dev/pci/drm/drm_drv.c
611
switch (BIT(opt)) {
sys/dev/pci/drm/drm_edid.c
134
EDID_QUIRK('A', 'C', 'R', 44358, BIT(EDID_QUIRK_PREFER_LARGE_60)),
sys/dev/pci/drm/drm_edid.c
136
EDID_QUIRK('A', 'P', 'I', 0x7602, BIT(EDID_QUIRK_PREFER_LARGE_60)),
sys/dev/pci/drm/drm_edid.c
139
EDID_QUIRK('A', 'E', 'O', 0, BIT(EDID_QUIRK_FORCE_6BPC)),
sys/dev/pci/drm/drm_edid.c
142
EDID_QUIRK('B', 'N', 'Q', 0x78d6, BIT(EDID_QUIRK_FORCE_8BPC)),
sys/dev/pci/drm/drm_edid.c
145
EDID_QUIRK('B', 'O', 'E', 0x78b, BIT(EDID_QUIRK_FORCE_6BPC)),
sys/dev/pci/drm/drm_edid.c
148
EDID_QUIRK('C', 'P', 'T', 0x17df, BIT(EDID_QUIRK_FORCE_6BPC)),
sys/dev/pci/drm/drm_edid.c
151
EDID_QUIRK('S', 'D', 'C', 0x3652, BIT(EDID_QUIRK_FORCE_6BPC)),
sys/dev/pci/drm/drm_edid.c
154
EDID_QUIRK('B', 'O', 'E', 0x0771, BIT(EDID_QUIRK_FORCE_6BPC)),
sys/dev/pci/drm/drm_edid.c
157
EDID_QUIRK('M', 'A', 'X', 1516, BIT(EDID_QUIRK_PREFER_LARGE_60)),
sys/dev/pci/drm/drm_edid.c
158
EDID_QUIRK('M', 'A', 'X', 0x77e, BIT(EDID_QUIRK_PREFER_LARGE_60)),
sys/dev/pci/drm/drm_edid.c
161
EDID_QUIRK('E', 'P', 'I', 59264, BIT(EDID_QUIRK_135_CLOCK_TOO_HIGH)),
sys/dev/pci/drm/drm_edid.c
163
EDID_QUIRK('E', 'P', 'I', 8232, BIT(EDID_QUIRK_PREFER_LARGE_60)),
sys/dev/pci/drm/drm_edid.c
166
EDID_QUIRK('F', 'C', 'M', 13600, BIT(EDID_QUIRK_PREFER_LARGE_75) |
sys/dev/pci/drm/drm_edid.c
167
BIT(EDID_QUIRK_DETAILED_IN_CM)),
sys/dev/pci/drm/drm_edid.c
170
EDID_QUIRK('G', 'S', 'M', 0x5bbf, BIT(EDID_QUIRK_CAP_DSC_15BPP)),
sys/dev/pci/drm/drm_edid.c
173
EDID_QUIRK('G', 'S', 'M', 0x5b9a, BIT(EDID_QUIRK_CAP_DSC_15BPP)),
sys/dev/pci/drm/drm_edid.c
176
EDID_QUIRK('L', 'G', 'D', 764, BIT(EDID_QUIRK_FORCE_10BPC)),
sys/dev/pci/drm/drm_edid.c
179
EDID_QUIRK('L', 'P', 'L', 0, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)),
sys/dev/pci/drm/drm_edid.c
180
EDID_QUIRK('L', 'P', 'L', 0x2a00, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)),
sys/dev/pci/drm/drm_edid.c
183
EDID_QUIRK('S', 'A', 'M', 541, BIT(EDID_QUIRK_DETAILED_SYNC_PP)),
sys/dev/pci/drm/drm_edid.c
185
EDID_QUIRK('S', 'A', 'M', 596, BIT(EDID_QUIRK_PREFER_LARGE_60)),
sys/dev/pci/drm/drm_edid.c
186
EDID_QUIRK('S', 'A', 'M', 638, BIT(EDID_QUIRK_PREFER_LARGE_60)),
sys/dev/pci/drm/drm_edid.c
189
EDID_QUIRK('S', 'N', 'Y', 0x2541, BIT(EDID_QUIRK_FORCE_12BPC)),
sys/dev/pci/drm/drm_edid.c
192
EDID_QUIRK('V', 'S', 'C', 5020, BIT(EDID_QUIRK_FORCE_REDUCED_BLANKING)),
sys/dev/pci/drm/drm_edid.c
195
EDID_QUIRK('M', 'E', 'D', 0x7b8, BIT(EDID_QUIRK_PREFER_LARGE_75)),
sys/dev/pci/drm/drm_edid.c
198
EDID_QUIRK('S', 'D', 'C', 18514, BIT(EDID_QUIRK_FORCE_6BPC)),
sys/dev/pci/drm/drm_edid.c
201
EDID_QUIRK('S', 'E', 'C', 0xd033, BIT(EDID_QUIRK_FORCE_8BPC)),
sys/dev/pci/drm/drm_edid.c
204
EDID_QUIRK('E', 'T', 'R', 13896, BIT(EDID_QUIRK_FORCE_8BPC)),
sys/dev/pci/drm/drm_edid.c
207
EDID_QUIRK('V', 'L', 'V', 0x91a8, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
208
EDID_QUIRK('V', 'L', 'V', 0x91b0, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
209
EDID_QUIRK('V', 'L', 'V', 0x91b1, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
210
EDID_QUIRK('V', 'L', 'V', 0x91b2, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
211
EDID_QUIRK('V', 'L', 'V', 0x91b3, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
212
EDID_QUIRK('V', 'L', 'V', 0x91b4, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
213
EDID_QUIRK('V', 'L', 'V', 0x91b5, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
214
EDID_QUIRK('V', 'L', 'V', 0x91b6, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
215
EDID_QUIRK('V', 'L', 'V', 0x91b7, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
216
EDID_QUIRK('V', 'L', 'V', 0x91b8, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
217
EDID_QUIRK('V', 'L', 'V', 0x91b9, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
218
EDID_QUIRK('V', 'L', 'V', 0x91ba, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
219
EDID_QUIRK('V', 'L', 'V', 0x91bb, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
220
EDID_QUIRK('V', 'L', 'V', 0x91bc, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
221
EDID_QUIRK('V', 'L', 'V', 0x91bd, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
222
EDID_QUIRK('V', 'L', 'V', 0x91be, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
223
EDID_QUIRK('V', 'L', 'V', 0x91bf, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
226
EDID_QUIRK('H', 'V', 'R', 0xaa01, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
227
EDID_QUIRK('H', 'V', 'R', 0xaa02, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
230
EDID_QUIRK('O', 'V', 'R', 0x0001, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
231
EDID_QUIRK('O', 'V', 'R', 0x0003, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
232
EDID_QUIRK('O', 'V', 'R', 0x0004, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
233
EDID_QUIRK('O', 'V', 'R', 0x0012, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
236
EDID_QUIRK('A', 'C', 'R', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
237
EDID_QUIRK('L', 'E', 'N', 0x0408, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
238
EDID_QUIRK('F', 'U', 'J', 0x1970, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
239
EDID_QUIRK('D', 'E', 'L', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
240
EDID_QUIRK('S', 'E', 'C', 0x144a, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
241
EDID_QUIRK('A', 'U', 'S', 0xc102, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
244
EDID_QUIRK('S', 'N', 'Y', 0x0704, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
247
EDID_QUIRK('S', 'E', 'N', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
250
EDID_QUIRK('S', 'V', 'R', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
251
EDID_QUIRK('A', 'U', 'O', 0x1111, BIT(EDID_QUIRK_NON_DESKTOP)),
sys/dev/pci/drm/drm_edid.c
259
EDID_QUIRK('H', 'W', 'P', 0x2869, BIT(DRM_EDID_QUIRK_DP_DPCD_PROBE)),
sys/dev/pci/drm/drm_edid.c
3002
return connector->display_info.quirks & BIT(quirk);
sys/dev/pci/drm/drm_edid.c
3007
return connector->display_info.quirks & BIT(quirk);
sys/dev/pci/drm/drm_edid.c
4834
return db[8] & BIT(7);
sys/dev/pci/drm/drm_edid.c
4839
return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
sys/dev/pci/drm/drm_edid.c
5443
if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
sys/dev/pci/drm/drm_edid.c
5480
(BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
sys/dev/pci/drm/drm_edid.c
5481
BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
sys/dev/pci/drm/drm_edid.c
5482
BIT(HDMI_EOTF_SMPTE_ST2084) |
sys/dev/pci/drm/drm_edid.c
5483
BIT(HDMI_EOTF_BT_2100_HLG));
sys/dev/pci/drm/drm_edid.c
5489
BIT(HDMI_STATIC_METADATA_TYPE1);
sys/dev/pci/drm/drm_edid.c
6415
if (len >= 8 && db[8] & BIT(5))
sys/dev/pci/drm/drm_edid.c
6434
bool desktop_usage = db[5] & BIT(6);
sys/dev/pci/drm/drm_format_helper.c
1297
byte |= BIT(i);
sys/dev/pci/drm/drm_format_internal.h
78
BIT(0); /* set alpha bit */
sys/dev/pci/drm/drm_format_internal.h
90
return BIT(15) | /* set alpha bit */
sys/dev/pci/drm/drm_plane.c
1723
unsigned int valid_mode_mask = BIT(DRM_SCALING_FILTER_DEFAULT) |
sys/dev/pci/drm/drm_plane.c
1724
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR);
sys/dev/pci/drm/drm_plane.c
1728
((supported_filters & BIT(DRM_SCALING_FILTER_DEFAULT)) == 0)))
sys/dev/pci/drm/drm_plane.c
1740
if (!(BIT(props[i].type) & supported_filters))
sys/dev/pci/drm/drm_print.c
44
unsigned long __drm_debug = BIT(DRM_UT_CORE) | BIT(DRM_UT_DRIVER);
sys/dev/pci/drm/drm_probe_helper.c
1244
unsigned int ntsc_modes = BIT(DRM_MODE_TV_MODE_NTSC) |
sys/dev/pci/drm/drm_probe_helper.c
1245
BIT(DRM_MODE_TV_MODE_NTSC_443) |
sys/dev/pci/drm/drm_probe_helper.c
1246
BIT(DRM_MODE_TV_MODE_NTSC_J) |
sys/dev/pci/drm/drm_probe_helper.c
1247
BIT(DRM_MODE_TV_MODE_PAL_M);
sys/dev/pci/drm/drm_probe_helper.c
1248
unsigned int pal_modes = BIT(DRM_MODE_TV_MODE_PAL) |
sys/dev/pci/drm/drm_probe_helper.c
1249
BIT(DRM_MODE_TV_MODE_PAL_N) |
sys/dev/pci/drm/drm_probe_helper.c
1250
BIT(DRM_MODE_TV_MODE_SECAM);
sys/dev/pci/drm/drm_probe_helper.c
1258
supported_tv_modes |= BIT(tv_mode_property->values[i]);
sys/dev/pci/drm/drm_probe_helper.c
1262
(supported_tv_modes & BIT(DRM_MODE_TV_MODE_MONOCHROME))) {
sys/dev/pci/drm/drm_probe_helper.c
1273
if (BIT(default_mode) & ntsc_modes) {
sys/dev/pci/drm/drm_self_refresh_helper.c
155
bool new_self_refresh_active = new_self_refresh_mask & BIT(i);
sys/dev/pci/drm/hdmi.c
143
ptr[0] |= BIT(4);
sys/dev/pci/drm/hdmi.c
147
ptr[0] |= BIT(3);
sys/dev/pci/drm/hdmi.c
150
ptr[0] |= BIT(2);
sys/dev/pci/drm/hdmi.c
161
ptr[2] |= BIT(7);
sys/dev/pci/drm/hdmi.c
410
buffer[4] |= BIT(7);
sys/dev/pci/drm/i915/display/g4x_dp.c
1390
intel_encoder->pipe_mask = BIT(PIPE_C);
sys/dev/pci/drm/i915/display/g4x_dp.c
1392
intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
sys/dev/pci/drm/i915/display/g4x_dp.c
346
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
sys/dev/pci/drm/i915/display/g4x_dp.c
348
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
158
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
746
intel_encoder->pipe_mask = BIT(PIPE_C);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
748
intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
752
intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
760
intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/hsw_ips.c
257
if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
sys/dev/pci/drm/i915/display/hsw_ips.c
33
!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
sys/dev/pci/drm/i915/display/i9xx_plane.c
484
crtc_state->async_flip_planes & BIT(plane->id))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1203
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1225
wm_state->cxsr = active_planes == BIT(PLANE_PRIMARY);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1278
dirty |= BIT(plane->id);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1549
return (active_planes & (BIT(PLANE_SPRITE0) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
1550
BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1560
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1593
if ((active_planes & BIT(plane_id)) == 0) {
sys/dev/pci/drm/i915/display/i9xx_wm.c
1617
if ((active_planes & BIT(plane_id)) == 0)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1748
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1817
dirty |= BIT(plane->id);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1836
if (dirty & ~BIT(PLANE_CURSOR)) {
sys/dev/pci/drm/i915/display/i9xx_wm.c
2949
pipe_wm->sprites_enabled = crtc_state->active_planes & BIT(PLANE_SPRITE0);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2950
pipe_wm->sprites_scaled = crtc_state->scaled_planes & BIT(PLANE_SPRITE0);
sys/dev/pci/drm/i915/display/icl_dsi.c
1117
if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
sys/dev/pci/drm/i915/display/icl_dsi.c
1547
if (intel_dsi->ports == BIT(PORT_B))
sys/dev/pci/drm/i915/display/icl_dsi.c
1559
if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
sys/dev/pci/drm/i915/display/icl_dsi.c
1562
else if (intel_dsi->ports == BIT(PORT_B))
sys/dev/pci/drm/i915/display/icl_dsi.c
1581
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
sys/dev/pci/drm/i915/display/icl_dsi.c
1688
if (intel_dsi->ports == BIT(PORT_B))
sys/dev/pci/drm/i915/display/icl_dsi.c
2011
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
sys/dev/pci/drm/i915/display/icl_dsi.c
2013
intel_dsi->ports = BIT(port);
sys/dev/pci/drm/i915/display/intel_audio.c
1314
#define AUD_FREQ_BCLK_96M BIT(4)
sys/dev/pci/drm/i915/display/intel_bios.c
1655
panel->vbt.dsi.bl_ports = BIT(port);
sys/dev/pci/drm/i915/display/intel_bios.c
1657
panel->vbt.dsi.cabc_ports = BIT(port);
sys/dev/pci/drm/i915/display/intel_bios.c
1664
panel->vbt.dsi.bl_ports = BIT(PORT_A);
sys/dev/pci/drm/i915/display/intel_bios.c
1667
panel->vbt.dsi.bl_ports = BIT(port_bc);
sys/dev/pci/drm/i915/display/intel_bios.c
1671
panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(port_bc);
sys/dev/pci/drm/i915/display/intel_bios.c
1680
panel->vbt.dsi.cabc_ports = BIT(PORT_A);
sys/dev/pci/drm/i915/display/intel_bios.c
1683
panel->vbt.dsi.cabc_ports = BIT(port_bc);
sys/dev/pci/drm/i915/display/intel_bios.c
1688
BIT(PORT_A) | BIT(port_bc);
sys/dev/pci/drm/i915/display/intel_bios.c
3528
if (dsc->slices_per_line & BIT(2)) {
sys/dev/pci/drm/i915/display/intel_bios.c
3530
} else if (dsc->slices_per_line & BIT(1)) {
sys/dev/pci/drm/i915/display/intel_bios.c
3534
if (!(dsc->slices_per_line & BIT(0)))
sys/dev/pci/drm/i915/display/intel_bios.c
785
return (value >> (panel_type * num_bits)) & (BIT(num_bits) - 1);
sys/dev/pci/drm/i915/display/intel_bw.c
1001
max_bw_point_mask |= BIT(i);
sys/dev/pci/drm/i915/display/intel_bw.c
1180
qgv_points |= BIT(i);
sys/dev/pci/drm/i915/display/intel_bw.c
1190
psf_points |= BIT(i);
sys/dev/pci/drm/i915/display/intel_bw.c
1319
dbuf_bw->active_planes[slice] |= BIT(plane_id);
sys/dev/pci/drm/i915/display/intel_bw.c
1580
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_bw.c
1582
new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_bw.c
1688
bw_state->active_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_bw.c
1696
bw_state->pipe_sagv_reject |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_bw.c
845
return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
sys/dev/pci/drm/i915/display/intel_bw.c
971
max_bw_point = BIT(i);
sys/dev/pci/drm/i915/display/intel_bw.c
998
max_bw_point_mask = BIT(i);
sys/dev/pci/drm/i915/display/intel_cdclk.c
3393
cdclk_state->active_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_cdclk.c
611
vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/display/intel_cdclk.c
621
BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/display/intel_cdclk.c
700
BIT(VLV_IOSF_SB_CCK) |
sys/dev/pci/drm/i915/display/intel_cdclk.c
701
BIT(VLV_IOSF_SB_BUNIT) |
sys/dev/pci/drm/i915/display/intel_cdclk.c
702
BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/display/intel_cdclk.c
749
BIT(VLV_IOSF_SB_CCK) |
sys/dev/pci/drm/i915/display/intel_cdclk.c
750
BIT(VLV_IOSF_SB_BUNIT) |
sys/dev/pci/drm/i915/display/intel_cdclk.c
751
BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/display/intel_color.c
2146
return crtc_state->active_planes & BIT(plane->id) ||
sys/dev/pci/drm/i915/display/intel_color.c
2179
new_crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_color.c
612
c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
sys/dev/pci/drm/i915/display/intel_color.c
613
(s64)(BIT(int_bits + frac_bits - 1) - 1));
sys/dev/pci/drm/i915/display/intel_color.c
615
return c & (BIT(int_bits + frac_bits) - 1);
sys/dev/pci/drm/i915/display/intel_connector.c
341
scaling_modes = BIT(DRM_MODE_SCALE_ASPECT) |
sys/dev/pci/drm/i915/display/intel_connector.c
342
BIT(DRM_MODE_SCALE_FULLSCREEN);
sys/dev/pci/drm/i915/display/intel_connector.c
346
scaling_modes |= BIT(DRM_MODE_SCALE_CENTER);
sys/dev/pci/drm/i915/display/intel_crt.c
1063
crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_crt.c
1065
crt->base.pipe_mask = BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_crt.c
151
crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
sys/dev/pci/drm/i915/display/intel_crtc.c
112
(crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
sys/dev/pci/drm/i915/display/intel_crtc.c
328
crtc->plane_ids_mask |= BIT(primary->id);
sys/dev/pci/drm/i915/display/intel_crtc.c
343
crtc->plane_ids_mask |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_crtc.c
351
crtc->plane_ids_mask |= BIT(cursor->id);
sys/dev/pci/drm/i915/display/intel_crtc.c
382
BIT(DRM_SCALING_FILTER_DEFAULT) |
sys/dev/pci/drm/i915/display/intel_crtc.c
383
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c
85
if ((output_types & BIT(i)) == 0)
sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c
95
output_types &= ~BIT(i);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2641
cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2713
BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2714
BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(port_clock)),
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2718
BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2719
is_hdmi_frl(port_clock) ? BIT(7) : 0,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2732
BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2986
disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
31
for_each_if((__lane_mask) & BIT(__lane))
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
33
#define INTEL_CX0_LANE0 BIT(0)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
34
#define INTEL_CX0_LANE1 BIT(1)
sys/dev/pci/drm/i915/display/intel_ddi.c
2118
port_mask = BIT(encoder->port);
sys/dev/pci/drm/i915/display/intel_ddi.c
2134
port_mask & BIT(other_encoder->port)))
sys/dev/pci/drm/i915/display/intel_ddi.c
2483
return BIT(PIPE_A) | BIT(PIPE_B);
sys/dev/pci/drm/i915/display/intel_ddi.c
2485
return BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_ddi.c
2505
if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3955
u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_ddi.c
3956
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
sys/dev/pci/drm/i915/display/intel_ddi.c
3975
crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
3991
crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_ddi.c
4025
crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
sys/dev/pci/drm/i915/display/intel_ddi.c
4041
crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);
sys/dev/pci/drm/i915/display/intel_ddi.c
4043
crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);
sys/dev/pci/drm/i915/display/intel_ddi.c
4080
crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
4549
transcoders |= BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
4575
if (port_sync_transcoders & BIT(TRANSCODER_EDP))
sys/dev/pci/drm/i915/display/intel_ddi.c
4583
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
4743
return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);
sys/dev/pci/drm/i915/display/intel_ddi.c
5182
display->snps.phy_failed_calibration & BIT(phy)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
832
*pipe_mask = BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_ddi.c
835
*pipe_mask = BIT(PIPE_B);
sys/dev/pci/drm/i915/display/intel_ddi.c
838
*pipe_mask = BIT(PIPE_C);
sys/dev/pci/drm/i915/display/intel_ddi.c
874
mst_pipe_mask |= BIT(p);
sys/dev/pci/drm/i915/display/intel_ddi.c
876
dp128b132b_pipe_mask |= BIT(p);
sys/dev/pci/drm/i915/display/intel_ddi.c
878
*pipe_mask |= BIT(p);
sys/dev/pci/drm/i915/display/intel_ddi.c
909
*pipe_mask = BIT(ffs(*pipe_mask) - 1);
sys/dev/pci/drm/i915/display/intel_display.c
1123
update_planes & BIT(plane->id))
sys/dev/pci/drm/i915/display/intel_display.c
1140
update_planes & BIT(plane->id))
sys/dev/pci/drm/i915/display/intel_display.c
1162
disable_async_flip_planes & BIT(plane->id)) {
sys/dev/pci/drm/i915/display/intel_display.c
1308
!(update_mask & BIT(plane->id)))
sys/dev/pci/drm/i915/display/intel_display.c
206
~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
sys/dev/pci/drm/i915/display/intel_display.c
294
return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
304
return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
312
return BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_display.c
340
BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
3443
pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
sys/dev/pci/drm/i915/display/intel_display.c
3445
pipes = BIT(PIPE_B) | BIT(PIPE_C);
sys/dev/pci/drm/i915/display/intel_display.c
3490
*primary_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
3492
*secondary_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
3522
*primary_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
3524
*secondary_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
3553
return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;
sys/dev/pci/drm/i915/display/intel_display.c
3592
*primary_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
3594
*secondary_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
361
BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
367
return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
3672
if (ultrajoiner_pipes & BIT(pipe)) {
sys/dev/pci/drm/i915/display/intel_display.c
3687
if (uncompressed_joiner_pipes & BIT(pipe)) {
sys/dev/pci/drm/i915/display/intel_display.c
3702
if (bigjoiner_pipes & BIT(pipe)) {
sys/dev/pci/drm/i915/display/intel_display.c
3720
u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
sys/dev/pci/drm/i915/display/intel_display.c
3723
panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
sys/dev/pci/drm/i915/display/intel_display.c
3777
enabled_transcoders |= BIT(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_display.c
3783
enabled_transcoders |= BIT(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_display.c
3787
if (secondary_pipes & BIT(crtc->pipe)) {
sys/dev/pci/drm/i915/display/intel_display.c
3790
enabled_transcoders |= BIT(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_display.c
3798
return enabled_transcoders & BIT(TRANSCODER_EDP);
sys/dev/pci/drm/i915/display/intel_display.c
3803
return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
sys/dev/pci/drm/i915/display/intel_display.c
3804
BIT(TRANSCODER_DSI_1));
sys/dev/pci/drm/i915/display/intel_display.c
3809
return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
sys/dev/pci/drm/i915/display/intel_display.c
3810
BIT(TRANSCODER_DSI_0) |
sys/dev/pci/drm/i915/display/intel_display.c
3811
BIT(TRANSCODER_DSI_1));
sys/dev/pci/drm/i915/display/intel_display.c
3854
if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {
sys/dev/pci/drm/i915/display/intel_display.c
3877
for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
sys/dev/pci/drm/i915/display/intel_display.c
3922
if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
397
return BIT(crtc->pipe) | crtc_state->joiner_pipes;
sys/dev/pci/drm/i915/display/intel_display.c
4124
return a == b || (a->cloneable & BIT(b->type) &&
sys/dev/pci/drm/i915/display/intel_display.c
4125
b->cloneable & BIT(a->type));
sys/dev/pci/drm/i915/display/intel_display.c
4426
if (used_ports & BIT(encoder->port))
sys/dev/pci/drm/i915/display/intel_display.c
4429
used_ports |= BIT(encoder->port);
sys/dev/pci/drm/i915/display/intel_display.c
4646
crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_display.c
4692
BIT(encoder->compute_output_type(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
4695
crtc_state->output_types |= BIT(encoder->type);
sys/dev/pci/drm/i915/display/intel_display.c
5705
active_pipes |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_display.c
5707
active_pipes &= ~BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_display.c
5797
transcoders & BIT(new_crtc_state->cpu_transcoder) &&
sys/dev/pci/drm/i915/display/intel_display.c
5814
pipes & BIT(crtc->pipe) &&
sys/dev/pci/drm/i915/display/intel_display.c
6440
if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
sys/dev/pci/drm/i915/display/intel_display.c
6448
trans |= BIT(new_crtc_state->master_transcoder);
sys/dev/pci/drm/i915/display/intel_display.c
662
crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
sys/dev/pci/drm/i915/display/intel_display.c
663
crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
sys/dev/pci/drm/i915/display/intel_display.c
687
if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
sys/dev/pci/drm/i915/display/intel_display.c
6878
disable_pipes |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_display.c
6882
if ((disable_pipes & BIT(crtc->pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
6892
if ((disable_pipes & BIT(crtc->pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
6914
if ((disable_pipes & BIT(crtc->pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
6968
update_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
6970
modeset_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
6986
if ((update_pipes & BIT(pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
7003
if ((update_pipes & BIT(pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
7011
update_pipes &= ~BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
7039
if ((modeset_pipes & BIT(pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
7061
if ((modeset_pipes & BIT(pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
7078
if ((update_pipes & BIT(pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
7091
if ((update_pipes & BIT(pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
7099
update_pipes &= ~BIT(pipe);
sys/dev/pci/drm/i915/display/intel_display.c
7754
return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
sys/dev/pci/drm/i915/display/intel_display.c
865
crtc_state->active_planes & BIT(PLANE_CURSOR) &&
sys/dev/pci/drm/i915/display/intel_display.h
192
for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
sys/dev/pci/drm/i915/display/intel_display.h
196
for_each_if((__mask) & BIT(__p))
sys/dev/pci/drm/i915/display/intel_display.h
200
for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
sys/dev/pci/drm/i915/display/intel_display.h
204
for_each_if ((__mask) & BIT(__t))
sys/dev/pci/drm/i915/display/intel_display.h
216
for_each_if((__ports_mask) & BIT(__port))
sys/dev/pci/drm/i915/display/intel_display.h
220
for_each_if((__phys_mask) & BIT(__phy))
sys/dev/pci/drm/i915/display/intel_display.h
249
for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
sys/dev/pci/drm/i915/display/intel_display.h
255
for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
sys/dev/pci/drm/i915/display/intel_display.h
376
for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
sys/dev/pci/drm/i915/display/intel_display.h
382
for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
sys/dev/pci/drm/i915/display/intel_display.h
82
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
sys/dev/pci/drm/i915/display/intel_display.h
86
for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
sys/dev/pci/drm/i915/display/intel_display.h
90
for_each_if((__mask) & BIT(__slice))
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
463
DIV_ROUND_CLOSEST(BIT(row + 9), x), units);
sys/dev/pci/drm/i915/display/intel_display_device.c
1000
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1001
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
sys/dev/pci/drm/i915/display/intel_display_device.c
1037
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1038
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
sys/dev/pci/drm/i915/display/intel_display_device.c
1054
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1055
BIT(PORT_TC1) | BIT(PORT_TC2),
sys/dev/pci/drm/i915/display/intel_display_device.c
1070
.abox_mask = BIT(0),
sys/dev/pci/drm/i915/display/intel_display_device.c
1074
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
1076
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
1077
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1078
BIT(PORT_TC1) | BIT(PORT_TC2),
sys/dev/pci/drm/i915/display/intel_display_device.c
1116
.__runtime_defaults.port_mask = BIT(PORT_A) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1117
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
sys/dev/pci/drm/i915/display/intel_display_device.c
1130
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
1131
BIT(DBUF_S4), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1160
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1163
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
sys/dev/pci/drm/i915/display/intel_display_device.c
1171
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1172
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1173
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
sys/dev/pci/drm/i915/display/intel_display_device.c
1174
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1175
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
sys/dev/pci/drm/i915/display/intel_display_device.c
1237
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1238
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
sys/dev/pci/drm/i915/display/intel_display_device.c
1239
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1240
BIT(PORT_TC1),
sys/dev/pci/drm/i915/display/intel_display_device.c
1308
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
1309
BIT(DBUF_S4), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1334
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
1335
BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1336
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1341
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1342
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
1343
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
sys/dev/pci/drm/i915/display/intel_display_device.c
1353
BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1354
BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
sys/dev/pci/drm/i915/display/intel_display_device.c
1362
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
1364
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
1366
BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) | BIT(INTEL_FBC_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
1368
BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2),
sys/dev/pci/drm/i915/display/intel_display_device.c
1373
.__runtime_defaults.port_mask = BIT(PORT_A) |
sys/dev/pci/drm/i915/display/intel_display_device.c
1374
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
sys/dev/pci/drm/i915/display/intel_display_device.c
1783
display_runtime->port_mask &= ~BIT(PORT_D);
sys/dev/pci/drm/i915/display/intel_display_device.c
1786
display_runtime->port_mask |= BIT(PORT_F);
sys/dev/pci/drm/i915/display/intel_display_device.c
1859
display_runtime->pipe_mask &= ~BIT(PIPE_C);
sys/dev/pci/drm/i915/display/intel_display_device.c
1860
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
sys/dev/pci/drm/i915/display/intel_display_device.c
1866
display_runtime->pipe_mask &= ~BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_display_device.c
1867
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
sys/dev/pci/drm/i915/display/intel_display_device.c
1868
display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
sys/dev/pci/drm/i915/display/intel_display_device.c
1871
display_runtime->pipe_mask &= ~BIT(PIPE_B);
sys/dev/pci/drm/i915/display/intel_display_device.c
1872
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
sys/dev/pci/drm/i915/display/intel_display_device.c
1873
display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
sys/dev/pci/drm/i915/display/intel_display_device.c
1876
display_runtime->pipe_mask &= ~BIT(PIPE_C);
sys/dev/pci/drm/i915/display/intel_display_device.c
1877
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
sys/dev/pci/drm/i915/display/intel_display_device.c
1878
display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
sys/dev/pci/drm/i915/display/intel_display_device.c
1883
display_runtime->pipe_mask &= ~BIT(PIPE_D);
sys/dev/pci/drm/i915/display/intel_display_device.c
1884
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
sys/dev/pci/drm/i915/display/intel_display_device.c
1885
display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
sys/dev/pci/drm/i915/display/intel_display_device.c
242
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
244
BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
sys/dev/pci/drm/i915/display/intel_display_device.c
255
.__runtime_defaults.pipe_mask = BIT(PIPE_A), \
sys/dev/pci/drm/i915/display/intel_display_device.c
256
.__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
sys/dev/pci/drm/i915/display/intel_display_device.c
264
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
273
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
283
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
284
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
293
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
294
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
305
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
307
BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
308
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
330
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
356
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
394
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
396
BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
sys/dev/pci/drm/i915/display/intel_display_device.c
404
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
416
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
417
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
427
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
sys/dev/pci/drm/i915/display/intel_display_device.c
439
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
sys/dev/pci/drm/i915/display/intel_display_device.c
440
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
451
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
453
BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
454
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
sys/dev/pci/drm/i915/display/intel_display_device.c
469
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
480
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_device.c
482
BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
sys/dev/pci/drm/i915/display/intel_display_device.c
483
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
sys/dev/pci/drm/i915/display/intel_display_device.c
484
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
505
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
507
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
508
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
sys/dev/pci/drm/i915/display/intel_display_device.c
509
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
534
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_device.c
536
BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
sys/dev/pci/drm/i915/display/intel_display_device.c
537
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
sys/dev/pci/drm/i915/display/intel_display_device.c
582
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
584
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
585
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
sys/dev/pci/drm/i915/display/intel_display_device.c
586
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
sys/dev/pci/drm/i915/display/intel_display_device.c
587
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
635
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
637
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
638
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
sys/dev/pci/drm/i915/display/intel_display_device.c
639
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
sys/dev/pci/drm/i915/display/intel_display_device.c
640
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
655
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
657
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
658
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
sys/dev/pci/drm/i915/display/intel_display_device.c
664
.dbuf.slice_mask = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/intel_display_device.c
679
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
681
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_display_device.c
682
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
sys/dev/pci/drm/i915/display/intel_display_device.c
683
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
sys/dev/pci/drm/i915/display/intel_display_device.c
684
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
sys/dev/pci/drm/i915/display/intel_display_device.c
814
.dbuf.slice_mask = BIT(DBUF_S1), \
sys/dev/pci/drm/i915/display/intel_display_device.c
828
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
sys/dev/pci/drm/i915/display/intel_display_device.c
829
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
sys/dev/pci/drm/i915/display/intel_display_device.c
831
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
832
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
833
BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
sys/dev/pci/drm/i915/display/intel_display_device.c
834
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
sys/dev/pci/drm/i915/display/intel_display_device.c
871
.abox_mask = BIT(0), \
sys/dev/pci/drm/i915/display/intel_display_device.c
873
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
sys/dev/pci/drm/i915/display/intel_display_device.c
904
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
sys/dev/pci/drm/i915/display/intel_display_device.c
906
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
907
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
908
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
sys/dev/pci/drm/i915/display/intel_display_device.c
909
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
sys/dev/pci/drm/i915/display/intel_display_device.c
932
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
sys/dev/pci/drm/i915/display/intel_display_device.c
940
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
sys/dev/pci/drm/i915/display/intel_display_device.c
963
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
sys/dev/pci/drm/i915/display/intel_display_device.c
996
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
sys/dev/pci/drm/i915/display/intel_display_device.c
998
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
sys/dev/pci/drm/i915/display/intel_display_device.c
999
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
sys/dev/pci/drm/i915/display/intel_display_device.h
194
BIT(trans)) != 0)
sys/dev/pci/drm/i915/display/intel_display_irq.c
2027
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_display_irq.c
2028
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
sys/dev/pci/drm/i915/display/intel_display_irq.c
2238
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
sys/dev/pci/drm/i915/display/intel_display_irq.c
2239
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
sys/dev/pci/drm/i915/display/intel_display_power.c
1111
gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice));
sys/dev/pci/drm/i915/display/intel_display_power.c
1124
slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;
sys/dev/pci/drm/i915/display/intel_display_power.c
1177
abox_regs |= BIT(0);
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1073
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1083
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1168
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1178
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1186
.irq_pipe_mask = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1336
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1344
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1352
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1360
.irq_pipe_mask = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1493
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
150
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1501
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1509
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1517
.irq_pipe_mask = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1654
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1662
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1670
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1678
.irq_pipe_mask = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1736
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1744
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1752
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
394
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
473
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
576
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
752
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
789
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
918
.irq_pipe_mask = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
940
.irq_pipe_mask = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
948
.irq_pipe_mask = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/intel_display_types.h
2128
return crtc_state->output_types & BIT(type);
sys/dev/pci/drm/i915/display/intel_display_types.h
2135
(BIT(INTEL_OUTPUT_DP) |
sys/dev/pci/drm/i915/display/intel_display_types.h
2136
BIT(INTEL_OUTPUT_DP_MST) |
sys/dev/pci/drm/i915/display/intel_display_types.h
2137
BIT(INTEL_OUTPUT_EDP));
sys/dev/pci/drm/i915/display/intel_display_types.h
645
#define PLANE_HAS_FENCE BIT(0)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
460
#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
461
#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART BIT(15)
sys/dev/pci/drm/i915/display/intel_dp.c
5393
*pipe_mask |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dp.c
6258
if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
sys/dev/pci/drm/i915/display/intel_dp.c
6271
transcoders &= ~BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp.c
6300
transcoders |= BIT(old_crtc_state->master_transcoder);
sys/dev/pci/drm/i915/display/intel_dp.c
6364
display->hotplug.event_bits |= BIT(hpd_pin);
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
150
BIT(HDMI_STATIC_METADATA_TYPE1))) {
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
53
# define INTEL_EDP_HDR_TCON_2084_DECODE_CAP BIT(0)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
54
# define INTEL_EDP_HDR_TCON_2020_GAMUT_CAP BIT(1)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
55
# define INTEL_EDP_HDR_TCON_TONE_MAPPING_CAP BIT(2)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
56
# define INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP BIT(3)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
57
# define INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP BIT(4)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
58
# define INTEL_EDP_HDR_TCON_OPTIMIZATION_CAP BIT(5)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
59
# define INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP BIT(6)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
60
# define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_CONVERSION_CAP BIT(7)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
63
# define INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP BIT(0)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
68
# define INTEL_EDP_HDR_TCON_2084_DECODE_ENABLE BIT(0)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
69
# define INTEL_EDP_HDR_TCON_2020_GAMUT_ENABLE BIT(1)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
70
# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE BIT(2)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
71
# define INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_ENABLE BIT(3)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
72
# define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
73
# define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLE BIT(5)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
75
# define INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX BIT(7)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
91
# define INTEL_EDP_TCON_POWER_MASK BIT(4)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
780
transcoders |= BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
808
mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
835
fec_pipe_mask |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dp_test.c
443
*pipe_mask |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
342
pipe_mask |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
173
.pwron_mask = BIT(0),
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
183
.pwron_mask = BIT(1),
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
195
.pwron_mask = BIT(0),
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
205
.pwron_mask = BIT(3),
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
215
.pwron_mask = BIT(1),
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
603
return BIT(2) | BIT(0);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
605
return BIT(3) | BIT(2) | BIT(0);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
631
lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
653
mask |= BIT(lane);
sys/dev/pci/drm/i915/display/intel_dpll.c
2214
crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1071
BIT(DPLL_ID_WRPLL2) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1072
BIT(DPLL_ID_WRPLL1));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1173
BIT(DPLL_ID_SPLL));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1947
BIT(DPLL_ID_SKL_DPLL0));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1951
BIT(DPLL_ID_SKL_DPLL3) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1952
BIT(DPLL_ID_SKL_DPLL2) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1953
BIT(DPLL_ID_SKL_DPLL1));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3366
BIT(DPLL_ID_DG1_DPLL3) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3367
BIT(DPLL_ID_DG1_DPLL2) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3368
BIT(DPLL_ID_ICL_DPLL1) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3369
BIT(DPLL_ID_ICL_DPLL0);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3373
BIT(DPLL_ID_DG1_DPLL2) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3374
BIT(DPLL_ID_DG1_DPLL3);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3377
BIT(DPLL_ID_DG1_DPLL0) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3378
BIT(DPLL_ID_DG1_DPLL1);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3382
BIT(DPLL_ID_EHL_DPLL4) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3383
BIT(DPLL_ID_ICL_DPLL1) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3384
BIT(DPLL_ID_ICL_DPLL0);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3389
BIT(DPLL_ID_EHL_DPLL4) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3390
BIT(DPLL_ID_ICL_DPLL1) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3391
BIT(DPLL_ID_ICL_DPLL0);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3393
dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3465
BIT(DPLL_ID_ICL_TBTPLL));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3475
BIT(dpll_id));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
352
drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
354
dpll_mask |= BIT(pll->info->id);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
429
drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
431
dpll_state->pipe_mask |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4664
pipe_mask = BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
468
drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
470
dpll_state->pipe_mask &= ~BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4708
u8 pipe_mask = BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
632
BIT(DPLL_ID_PCH_PLL_B) |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
633
BIT(DPLL_ID_PCH_PLL_A));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
729
if (display->dpll.pch_ssc_use & BIT(id))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
745
if (display->dpll.pch_ssc_use & BIT(id))
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
413
value = data[2] & BIT(0);
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
415
if (connector->panel.vbt.dsi.seq_version >= 4 && data[2] & BIT(1))
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
421
value = data[1] & BIT(0);
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
96
if (intel_dsi->ports & BIT(PORT_B))
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
98
if (intel_dsi->ports & BIT(PORT_C))
sys/dev/pci/drm/i915/display/intel_dvo.c
168
pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
sys/dev/pci/drm/i915/display/intel_dvo.c
533
encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG) |
sys/dev/pci/drm/i915/display/intel_dvo.c
534
BIT(INTEL_OUTPUT_DVO);
sys/dev/pci/drm/i915/display/intel_fb.c
262
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
263
.ccs.planar_aux_planes = BIT(2) | BIT(3),
sys/dev/pci/drm/i915/display/intel_fb.c
271
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
279
.ccs.cc_planes = BIT(2),
sys/dev/pci/drm/i915/display/intel_fb.c
280
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
292
.ccs.cc_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
308
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
309
.ccs.planar_aux_planes = BIT(2) | BIT(3),
sys/dev/pci/drm/i915/display/intel_fb.c
317
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
325
.ccs.cc_planes = BIT(2),
sys/dev/pci/drm/i915/display/intel_fb.c
326
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
334
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
342
.ccs.packed_aux_planes = BIT(1),
sys/dev/pci/drm/i915/display/intel_fb.c
678
return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
sys/dev/pci/drm/i915/display/intel_fb.c
694
ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
sys/dev/pci/drm/i915/display/intel_fb.h
26
#define INTEL_PLANE_CAP_CCS_RC BIT(0)
sys/dev/pci/drm/i915/display/intel_fb.h
27
#define INTEL_PLANE_CAP_CCS_RC_CC BIT(1)
sys/dev/pci/drm/i915/display/intel_fb.h
28
#define INTEL_PLANE_CAP_CCS_MC BIT(2)
sys/dev/pci/drm/i915/display/intel_fb.h
29
#define INTEL_PLANE_CAP_TILING_X BIT(3)
sys/dev/pci/drm/i915/display/intel_fb.h
30
#define INTEL_PLANE_CAP_TILING_Y BIT(4)
sys/dev/pci/drm/i915/display/intel_fb.h
31
#define INTEL_PLANE_CAP_TILING_Yf BIT(5)
sys/dev/pci/drm/i915/display/intel_fb.h
32
#define INTEL_PLANE_CAP_TILING_4 BIT(6)
sys/dev/pci/drm/i915/display/intel_fb.h
33
#define INTEL_PLANE_CAP_NEED64K_PHYS BIT(7)
sys/dev/pci/drm/i915/display/intel_fbc.c
70
for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id))
sys/dev/pci/drm/i915/display/intel_fdi.c
173
BIT(PIPE_B));
sys/dev/pci/drm/i915/display/intel_fdi.c
342
BIT(pipe_to_reduce),
sys/dev/pci/drm/i915/display/intel_frontbuffer.h
64
BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));
sys/dev/pci/drm/i915/display/intel_frontbuffer.h
66
BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
sys/dev/pci/drm/i915/display/intel_hdmi.c
601
return BIT(i);
sys/dev/pci/drm/i915/display/intel_hdmi.c
623
ret |= BIT(i);
sys/dev/pci/drm/i915/display/intel_hdmi.c
626
ret |= BIT(i);
sys/dev/pci/drm/i915/display/intel_hotplug.c
1138
hotplug->event_bits &= ~BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
1139
hotplug->retry_bits &= ~BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
1140
hotplug->short_hpd_pin_mask &= ~BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
1141
hotplug->long_hpd_pin_mask &= ~BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
384
hpd_pin_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
419
long_hpd = long_hpd_pin_mask & BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
420
short_hpd = short_hpd_pin_mask & BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
430
old_bits |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
458
hotplug->short_hpd_pin_mask |= BIT(encoder->hpd_pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
514
hpd_bit = BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
612
if (!(BIT(pin) & pin_mask))
sys/dev/pci/drm/i915/display/intel_hotplug.c
618
long_hpd = long_mask & BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
629
long_hpd_pulse_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
630
display->hotplug.long_hpd_pin_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
632
short_hpd_pulse_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
633
display->hotplug.short_hpd_pin_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
641
if (!(BIT(pin) & pin_mask))
sys/dev/pci/drm/i915/display/intel_hotplug.c
665
if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
sys/dev/pci/drm/i915/display/intel_hotplug.c
666
long_hpd = long_hpd_pulse_mask & BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
668
display->hotplug.event_bits |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug.c
676
display->hotplug.event_bits &= ~BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
1123
available_pins |= BIT(encoder->hpd_pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
1126
_xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin));
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
358
*pin_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
361
*long_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
531
pin_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
537
long_mask |= BIT(pin);
sys/dev/pci/drm/i915/display/intel_link_bw.c
114
if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe))
sys/dev/pci/drm/i915/display/intel_link_bw.c
149
BIT(max_bpp_pipe));
sys/dev/pci/drm/i915/display/intel_link_bw.c
229
new_limits->bpp_limit_reached_pipes & BIT(pipe)))
sys/dev/pci/drm/i915/display/intel_link_bw.c
234
new_limits->bpp_limit_reached_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_link_bw.c
69
limits->force_fec_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/intel_lvds.c
129
crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
sys/dev/pci/drm/i915/display/intel_lvds.c
932
encoder->pipe_mask = BIT(PIPE_B);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
204
if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
205
pipes |= BIT(temp_crtc->pipe);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
226
*master_pipe_mask = BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
237
*master_pipe_mask = get_transcoder_pipes(display, BIT(master_transcoder));
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
75
BIT(pipe) |
sys/dev/pci/drm/i915/display/intel_opregion.c
56
#define MBOX_ACPI BIT(0) /* Mailbox #1 */
sys/dev/pci/drm/i915/display/intel_opregion.c
57
#define MBOX_SWSCI BIT(1) /* Mailbox #2 (obsolete from v2.x) */
sys/dev/pci/drm/i915/display/intel_opregion.c
58
#define MBOX_ASLE BIT(2) /* Mailbox #3 */
sys/dev/pci/drm/i915/display/intel_opregion.c
59
#define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */
sys/dev/pci/drm/i915/display/intel_opregion.c
60
#define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x) */
sys/dev/pci/drm/i915/display/intel_opregion.c
62
#define PCON_HEADLESS_SKU BIT(13)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
477
display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
482
display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
487
display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
sys/dev/pci/drm/i915/display/intel_plane.c
1480
crtc_state->enabled_planes |= BIT(y_plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1481
crtc_state->active_planes |= BIT(y_plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1482
crtc_state->update_planes |= BIT(y_plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1518
crtc_state->enabled_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1519
crtc_state->active_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1520
crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1559
if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)
sys/dev/pci/drm/i915/display/intel_plane.c
1566
if (crtc_state->active_planes & BIT(y_plane->id))
sys/dev/pci/drm/i915/display/intel_plane.c
1600
if ((plane_ids_mask & BIT(plane->id)) == 0)
sys/dev/pci/drm/i915/display/intel_plane.c
1643
if ((joined_pipes & BIT(plane->pipe)) == 0)
sys/dev/pci/drm/i915/display/intel_plane.c
1646
affected_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1648
affected_planes |= BIT(linked->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1745
old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_plane.c
1746
new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_plane.c
434
crtc_state->active_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
435
crtc_state->scaled_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
436
crtc_state->nv12_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
437
crtc_state->c8_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
438
crtc_state->async_flip_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
649
new_crtc_state->async_flip_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
660
new_crtc_state->async_flip_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
676
new_crtc_state->enabled_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
686
new_crtc_state->enabled_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
690
new_crtc_state->active_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
694
new_crtc_state->scaled_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
698
new_crtc_state->nv12_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
702
new_crtc_state->c8_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
705
new_crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
816
!(*update_mask & BIT(plane_id)))
sys/dev/pci/drm/i915/display/intel_plane.c
825
*update_mask &= ~BIT(plane_id);
sys/dev/pci/drm/i915/display/intel_plane.c
912
!(update_mask & BIT(plane->id)))
sys/dev/pci/drm/i915/display/intel_plane.c
970
!(update_mask & BIT(plane->id)))
sys/dev/pci/drm/i915/display/intel_pmdemand.c
164
pmdemand_state->active_combo_phys_mask |= BIT(phy);
sys/dev/pci/drm/i915/display/intel_pmdemand.c
166
pmdemand_state->active_combo_phys_mask &= ~BIT(phy);
sys/dev/pci/drm/i915/display/intel_psr.c
1732
active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
sys/dev/pci/drm/i915/display/intel_psr.c
1737
~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
2885
crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_psr.c
2898
crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_psr.c
2915
crtc_state->update_planes |= BIT(linked->id);
sys/dev/pci/drm/i915/display/intel_psr.c
3910
active_non_psr_pipes |= BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
3912
active_non_psr_pipes &= ~BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_psr_regs.h
271
#define PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU BIT(6)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
272
#define PR_ALPM_CTL_RFB_UPDATE_CONTROL BIT(5)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
273
#define PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE BIT(4)
sys/dev/pci/drm/i915/display/intel_quirks.c
16
display->quirks.mask |= BIT(quirk);
sys/dev/pci/drm/i915/display/intel_quirks.c
21
intel_dp->quirks.mask |= BIT(quirk);
sys/dev/pci/drm/i915/display/intel_quirks.c
303
return display->quirks.mask & BIT(quirk);
sys/dev/pci/drm/i915/display/intel_quirks.c
308
return intel_dp->quirks.mask & BIT(quirk);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1712
pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
47
display->snps.phy_failed_calibration |= BIT(phy);
sys/dev/pci/drm/i915/display/intel_sprite.c
1717
BIT(DRM_COLOR_YCBCR_BT601) |
sys/dev/pci/drm/i915/display/intel_sprite.c
1718
BIT(DRM_COLOR_YCBCR_BT709),
sys/dev/pci/drm/i915/display/intel_sprite.c
1719
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
sys/dev/pci/drm/i915/display/intel_sprite.c
1720
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
sys/dev/pci/drm/i915/display/intel_sprite.c
183
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_sprite.c
486
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_sprite.c
600
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_tc.c
1029
mask |= BIT(TC_PORT_DP_ALT);
sys/dev/pci/drm/i915/display/intel_tc.c
1031
mask |= BIT(TC_PORT_TBT_ALT);
sys/dev/pci/drm/i915/display/intel_tc.c
1034
mask |= BIT(TC_PORT_LEGACY);
sys/dev/pci/drm/i915/display/intel_tc.c
1726
mask = BIT(tc->mode);
sys/dev/pci/drm/i915/display/intel_tc.c
476
valid_hpd_mask = BIT(TC_PORT_LEGACY);
sys/dev/pci/drm/i915/display/intel_tc.c
478
valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
sys/dev/pci/drm/i915/display/intel_tc.c
479
BIT(TC_PORT_TBT_ALT);
sys/dev/pci/drm/i915/display/intel_tc.c
548
mask |= BIT(TC_PORT_TBT_ALT);
sys/dev/pci/drm/i915/display/intel_tc.c
550
mask |= BIT(TC_PORT_DP_ALT);
sys/dev/pci/drm/i915/display/intel_tc.c
553
mask |= BIT(TC_PORT_LEGACY);
sys/dev/pci/drm/i915/display/intel_tc.c
675
if (!(tc_phy_hpd_live_status(tc) & BIT(TC_PORT_DP_ALT))) {
sys/dev/pci/drm/i915/display/intel_tc.c
833
mask |= BIT(TC_PORT_DP_ALT);
sys/dev/pci/drm/i915/display/intel_tc.c
835
mask |= BIT(TC_PORT_TBT_ALT);
sys/dev/pci/drm/i915/display/intel_tc.c
838
mask |= BIT(TC_PORT_LEGACY);
sys/dev/pci/drm/i915/display/intel_tv.c
1104
pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1426
crtc_state->async_flip_planes & BIT(plane->id))
sys/dev/pci/drm/i915/display/skl_universal_plane.c
241
return BIT(PLANE_4) | BIT(PLANE_5);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2415
if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
243
return BIT(PLANE_6) | BIT(PLANE_7);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
250
icl_nv12_y_plane_mask(display) & BIT(plane_id);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
255
return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
261
icl_hdr_plane_mask() & BIT(plane_id);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2966
supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2969
supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2973
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2974
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2980
BIT(DRM_MODE_BLEND_PIXEL_NONE) |
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2981
BIT(DRM_MODE_BLEND_PREMULTI) |
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2982
BIT(DRM_MODE_BLEND_COVERAGE));
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2991
BIT(DRM_SCALING_FILTER_DEFAULT) |
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2992
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
sys/dev/pci/drm/i915/display/skl_watermark.c
1001
[PIPE_C] = BIT(DBUF_S3),
sys/dev/pci/drm/i915/display/skl_watermark.c
1002
[PIPE_D] = BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1006
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1008
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1009
[PIPE_C] = BIT(DBUF_S3),
sys/dev/pci/drm/i915/display/skl_watermark.c
1010
[PIPE_D] = BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1014
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1016
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1017
[PIPE_C] = BIT(DBUF_S3),
sys/dev/pci/drm/i915/display/skl_watermark.c
1018
[PIPE_D] = BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1022
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1024
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
1025
[PIPE_B] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1026
[PIPE_C] = BIT(DBUF_S3),
sys/dev/pci/drm/i915/display/skl_watermark.c
1027
[PIPE_D] = BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1039
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
1041
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1046
.active_pipes = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
1048
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1053
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
1055
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1060
.active_pipes = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
1062
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1067
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
1069
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1070
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1074
.active_pipes = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
1076
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1080
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
1082
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1083
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1087
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
1089
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1090
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1094
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
1096
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1097
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1098
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1102
.active_pipes = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1104
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1108
.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1110
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1111
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1115
.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1117
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1118
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1122
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1124
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1125
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1126
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1130
.active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1132
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1133
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1137
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1139
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1140
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1141
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1145
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1147
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1148
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1149
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1153
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1155
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1156
[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1157
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1158
[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1253
return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
sys/dev/pci/drm/i915/display/skl_watermark.c
1516
crtc_state->nv12_planes & BIT(plane_id)) {
sys/dev/pci/drm/i915/display/skl_watermark.c
1549
crtc_state->nv12_planes & BIT(plane_id))
sys/dev/pci/drm/i915/display/skl_watermark.c
1579
crtc_state->nv12_planes & BIT(plane_id)) {
sys/dev/pci/drm/i915/display/skl_watermark.c
2487
new_crtc_state->update_planes |= BIT(plane_id);
sys/dev/pci/drm/i915/display/skl_watermark.c
2505
enabled_slices = BIT(DBUF_S1);
sys/dev/pci/drm/i915/display/skl_watermark.c
2857
new_crtc_state->update_planes |= BIT(plane_id);
sys/dev/pci/drm/i915/display/skl_watermark.c
3081
dbuf_state->active_pipes |= BIT(pipe);
sys/dev/pci/drm/i915/display/skl_watermark.c
3347
active_pipes &= BIT(PIPE_A) | BIT(PIPE_D);
sys/dev/pci/drm/i915/display/skl_watermark.c
3351
active_pipes &= BIT(PIPE_B) | BIT(PIPE_C);
sys/dev/pci/drm/i915/display/skl_watermark.c
3797
dbuf_state->active_pipes &= ~BIT(pipe);
sys/dev/pci/drm/i915/display/skl_watermark.c
433
if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
sys/dev/pci/drm/i915/display/skl_watermark.c
434
slice_mask = BIT(DBUF_S1);
sys/dev/pci/drm/i915/display/skl_watermark.c
435
else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
sys/dev/pci/drm/i915/display/skl_watermark.c
436
slice_mask = BIT(DBUF_S3);
sys/dev/pci/drm/i915/display/skl_watermark.c
461
slice_mask |= BIT(start_slice);
sys/dev/pci/drm/i915/display/skl_watermark.c
750
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
752
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
756
.active_pipes = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
758
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
762
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
764
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
765
[PIPE_B] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
769
.active_pipes = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
771
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
775
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
777
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
778
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
782
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
784
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
785
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
789
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
791
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
792
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
793
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
81
enabled_slices |= BIT(slice);
sys/dev/pci/drm/i915/display/skl_watermark.c
813
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
815
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
819
.active_pipes = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
821
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
825
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
827
[PIPE_A] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
828
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
832
.active_pipes = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
834
[PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
838
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
840
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
841
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
845
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
847
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
848
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
852
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
854
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
855
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
856
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
860
.active_pipes = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
862
[PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
866
.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
868
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
869
[PIPE_D] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
873
.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
875
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
876
[PIPE_D] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
880
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
882
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
883
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
884
[PIPE_D] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
888
.active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
890
[PIPE_C] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
891
[PIPE_D] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
895
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
897
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
898
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
899
[PIPE_D] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
903
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
905
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
906
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
907
[PIPE_D] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
911
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
913
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
914
[PIPE_B] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
915
[PIPE_C] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
916
[PIPE_D] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
924
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
926
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
930
.active_pipes = BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
932
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
936
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
938
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
939
[PIPE_B] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
943
.active_pipes = BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
945
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
949
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
951
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
952
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
956
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
958
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
959
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
963
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
965
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
966
[PIPE_B] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
967
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
971
.active_pipes = BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
973
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
977
.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
979
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
980
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
984
.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
986
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
987
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
991
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
993
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
994
[PIPE_B] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
995
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
999
.active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
228
#define DPIO_ALLDL_POWERDOWN BIT(1)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
229
#define DPIO_ANYDL_POWERDOWN BIT(0)
sys/dev/pci/drm/i915/display/vlv_dsi.c
1184
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1963
encoder->pipe_mask = BIT(PIPE_A);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1965
encoder->pipe_mask = BIT(PIPE_B);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1972
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1974
intel_dsi->ports = BIT(port);
sys/dev/pci/drm/i915/display/vlv_dsi.c
309
if (intel_dsi->ports == BIT(PORT_C))
sys/dev/pci/drm/i915/display/vlv_dsi.c
643
if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
sys/dev/pci/drm/i915/display/vlv_sideband.h
103
vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_FLISDSI));
sys/dev/pci/drm/i915/display/vlv_sideband.h
118
vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_FLISDSI));
sys/dev/pci/drm/i915/display/vlv_sideband.h
123
vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_NC));
sys/dev/pci/drm/i915/display/vlv_sideband.h
133
vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_NC));
sys/dev/pci/drm/i915/display/vlv_sideband.h
138
vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/display/vlv_sideband.h
153
vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/display/vlv_sideband.h
18
vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_BUNIT));
sys/dev/pci/drm/i915/display/vlv_sideband.h
33
vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_BUNIT));
sys/dev/pci/drm/i915/display/vlv_sideband.h
38
vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/display/vlv_sideband.h
53
vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/display/vlv_sideband.h
58
vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_CCU));
sys/dev/pci/drm/i915/display/vlv_sideband.h
73
vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_CCU));
sys/dev/pci/drm/i915/display/vlv_sideband.h
78
vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
sys/dev/pci/drm/i915/display/vlv_sideband.h
98
vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
sys/dev/pci/drm/i915/gem/i915_gem_clflush.h
16
#define I915_CLFLUSH_FORCE BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_clflush.h
17
#define I915_CLFLUSH_SYNC BIT(1)
sys/dev/pci/drm/i915/gem/i915_gem_context.c
156
#define LOOKUP_USER_INDEX BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_context.c
232
pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
254
pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
270
} else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
sys/dev/pci/drm/i915/gem/i915_gem_context.c
271
!(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
sys/dev/pci/drm/i915/gem/i915_gem_context.c
302
pc->user_flags = BIT(UCONTEXT_BANNABLE) |
sys/dev/pci/drm/i915/gem/i915_gem_context.c
303
BIT(UCONTEXT_RECOVERABLE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
305
pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
898
pc->user_flags |= BIT(UCONTEXT_NO_ERROR_CAPTURE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
900
pc->user_flags &= ~BIT(UCONTEXT_NO_ERROR_CAPTURE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
909
pc->user_flags |= BIT(UCONTEXT_BANNABLE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
913
pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
918
pc->user_flags |= BIT(UCONTEXT_LOW_LATENCY);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
927
pc->user_flags &= ~BIT(UCONTEXT_RECOVERABLE);
sys/dev/pci/drm/i915/gem/i915_gem_context.c
931
pc->user_flags |= BIT(UCONTEXT_RECOVERABLE);
sys/dev/pci/drm/i915/gem/i915_gem_create.c
321
if (mask & BIT(mr->id)) {
sys/dev/pci/drm/i915/gem/i915_gem_create.c
330
mask |= BIT(mr->id);
sys/dev/pci/drm/i915/gem/i915_gem_create.c
476
if (!(ext_data.placement_mask & BIT(INTEL_REGION_SMEM)))
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
56
#define __EXEC_OBJECT_HAS_PIN BIT(29)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
57
#define __EXEC_OBJECT_HAS_FENCE BIT(28)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
58
#define __EXEC_OBJECT_USERPTR_INIT BIT(27)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
59
#define __EXEC_OBJECT_NEEDS_MAP BIT(26)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
60
#define __EXEC_OBJECT_NEEDS_BIAS BIT(25)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
64
#define __EXEC_HAS_RELOC BIT(31)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
65
#define __EXEC_ENGINE_PINNED BIT(30)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
66
#define __EXEC_USERPTR_USED BIT(29)
sys/dev/pci/drm/i915/gem/i915_gem_object.h
751
#define CLFLUSH_BEFORE BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_object.h
752
#define CLFLUSH_AFTER BIT(1)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
340
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
341
#define I915_BO_ALLOC_VOLATILE BIT(1)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
342
#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
343
#define I915_BO_ALLOC_USER BIT(3)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
345
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
347
#define I915_BO_ALLOC_PM_EARLY BIT(5)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
353
#define I915_BO_ALLOC_GPU_ONLY BIT(6)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
354
#define I915_BO_ALLOC_CCS_AUX BIT(7)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
360
#define I915_BO_PREALLOC BIT(8)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
370
#define I915_BO_READONLY BIT(9)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
372
#define I915_BO_PROTECTED BIT(11)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
381
#define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
382
#define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
39
#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
41
#define I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST BIT(2)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
42
#define I915_GEM_OBJECT_IS_PROXY BIT(3)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
43
#define I915_GEM_OBJECT_NO_MMAP BIT(4)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
487
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
488
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
79
#define I915_GEM_OBJECT_SHRINK_WRITEBACK BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
80
#define I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT BIT(1)
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
64
obj->mm.page_sizes.sg |= BIT(i);
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.h
21
#define I915_SHRINK_UNBOUND BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.h
22
#define I915_SHRINK_BOUND BIT(1)
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.h
23
#define I915_SHRINK_ACTIVE BIT(2)
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.h
24
#define I915_SHRINK_VMAPS BIT(3)
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.h
25
#define I915_SHRINK_WRITEBACK BIT(4)
sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.h
14
#define I915_TTM_BACKUP_ALLOW_GPU BIT(0)
sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.h
15
#define I915_TTM_BACKUP_PINNED BIT(1)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
112
unsigned int page_size = BIT(bit);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
183
GEM_BUG_ON(!IS_ALIGNED(size, BIT(__ffs(page_mask))));
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
437
for (i = 1; i < BIT(ARRAY_SIZE(page_sizes)); i++) {
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
441
if (i & BIT(j))
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
516
unsigned int page_size = BIT(bit);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
596
unsigned int page_size = BIT(bit);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
778
err = i915_vma_pin(vma, 0, BIT(21), PIN_USER);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1039
#define TEST_IDLE BIT(0)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1040
#define TEST_BUSY BIT(1)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1041
#define TEST_RESET BIT(2)
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
506
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
563
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
588
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
73
if (pat_index & BIT(0))
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
76
if (pat_index & BIT(1))
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
79
if (pat_index & BIT(2))
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
82
if (pat_index & BIT(3))
sys/dev/pci/drm/i915/gt/intel_context_types.h
36
#define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT)
sys/dev/pci/drm/i915/gt/intel_context_types.h
39
#define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
sys/dev/pci/drm/i915/gt/intel_engine.h
309
#define FORCE_VIRTUAL BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine.h
82
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1231
val = BIT(val);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
457
BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
458
BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
483
engine->mask = BIT(id);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
497
engine->logical_mask = BIT(logical_instance);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
553
if (WARN_ON(engine->context_size > BIT(20)))
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
640
BIT(engine->instance))) ||
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
646
engine->gt->info.sfc_mask & BIT(engine->instance))
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
744
if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
748
!(BIT(physical_vdbox - 1) & vdbox_mask);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
788
vdbox_mask &= ~BIT(i);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
792
if (!(BIT(i) & vdbox_mask)) {
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
793
gt->info.engine_mask &= ~BIT(_VCS(i));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
799
gt->info.vdbox_sfc_access |= BIT(i);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
807
vebox_mask &= ~BIT(i);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
811
if (!(BIT(i) & vebox_mask)) {
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
812
gt->info.engine_mask &= ~BIT(_VECS(i));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
841
info->engine_mask &= ~BIT(_CCS(i));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
879
info->engine_mask &= ~BIT(GSC0);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
902
info->engine_mask |= BIT(_CCS(first_ccs));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
988
mask |= BIT(i);
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
117
#define CCID_EN BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
118
#define CCID_EXTENDED_STATE_RESTORE BIT(2)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
119
#define CCID_EXTENDED_STATE_SAVE BIT(3)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
121
#define PER_CTX_BB_FORCE BIT(2)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
122
#define PER_CTX_BB_VALID BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
213
#define ERROR_CSB BIT(31)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
214
#define ERROR_PREEMPT BIT(30)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
538
#define EMIT_INVALIDATE BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
539
#define EMIT_FLUSH BIT(1)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
544
#define I915_DISPATCH_SECURE BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
545
#define I915_DISPATCH_PINNED BIT(1)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
588
#define I915_ENGINE_USING_CMD_PARSER BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
589
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
590
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
591
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
592
#define I915_ENGINE_HAS_TIMESLICES BIT(4)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
593
#define I915_ENGINE_IS_VIRTUAL BIT(5)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
594
#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
595
#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
596
#define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
597
#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
598
#define I915_ENGINE_HAS_EU_PRIORITY BIT(10)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
599
#define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
600
#define I915_ENGINE_USES_WA_HOLD_SWITCHOUT BIT(12)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
61
#define VIRTUAL_ENGINES BIT(BITS_PER_TYPE(intel_engine_mask_t) - 1)
sys/dev/pci/drm/i915/gt/intel_engine_user.c
126
if (engine->flags & BIT(map[i].engine))
sys/dev/pci/drm/i915/gt/intel_engine_user.c
127
enabled |= BIT(map[i].sched);
sys/dev/pci/drm/i915/gt/intel_engine_user.c
129
disabled |= BIT(map[i].sched);
sys/dev/pci/drm/i915/gt/intel_engine_user.c
343
unsigned int bit = BIT(engine->uabi_class);
sys/dev/pci/drm/i915/gt/intel_engine_user.c
369
which |= BIT(engine->uabi_class);
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
165
#define XEHP_CTX_STATUS_SWITCHED_TO_NEW_QUEUE BIT(1) /* upper csb dword */
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
983
(BIT(I915_FENCE_FLAG_NOPREEMPT) |
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
984
BIT(I915_FENCE_FLAG_SENTINEL))))
sys/dev/pci/drm/i915/gt/intel_ggtt.c
301
if (pat_index & BIT(0))
sys/dev/pci/drm/i915/gt/intel_ggtt.c
304
if (pat_index & BIT(1))
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
131
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
157
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
87
val |= BIT(I965_FENCE_TILING_Y_SHIFT);
sys/dev/pci/drm/i915/gt/intel_gsc.h
19
#define GSC_IRQ_INTF(_x) BIT(15 - (_x))
sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c
22
if (gt->ccs.cslices & BIT(cslice))
sys/dev/pci/drm/i915/gt/intel_gt_irq.c
192
if (dw & BIT(bit)) {
sys/dev/pci/drm/i915/gt/intel_gt_irq.c
205
raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
sys/dev/pci/drm/i915/gt/intel_gt_irq.c
40
raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
636
if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0))
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
371
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
373
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1497
#define FORCEWAKE_KERNEL BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1498
#define FORCEWAKE_USER BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1499
#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
sys/dev/pci/drm/i915/gt/intel_gtt.h
103
#define GEN12_PDE_64K BIT(6)
sys/dev/pci/drm/i915/gt/intel_gtt.h
104
#define GEN12_PTE_PS64 BIT(8)
sys/dev/pci/drm/i915/gt/intel_gtt.h
155
#define GEN8_PDE_IPS_64K BIT(11)
sys/dev/pci/drm/i915/gt/intel_gtt.h
156
#define GEN8_PDE_PS_2M BIT(7)
sys/dev/pci/drm/i915/gt/intel_gtt.h
316
#define PTE_READ_ONLY BIT(0)
sys/dev/pci/drm/i915/gt/intel_gtt.h
317
#define PTE_LM BIT(1)
sys/dev/pci/drm/i915/gt/intel_lrc.c
102
*regs |= BIT(0);
sys/dev/pci/drm/i915/gt/intel_lrc.c
1060
*cs++ = MI_BATCH_BUFFER_END | BIT(15);
sys/dev/pci/drm/i915/gt/intel_lrc.c
51
#define NOP(x) (BIT(7) | (x))
sys/dev/pci/drm/i915/gt/intel_lrc.c
52
#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6)))
sys/dev/pci/drm/i915/gt/intel_lrc.c
53
#define POSTED BIT(0)
sys/dev/pci/drm/i915/gt/intel_lrc.c
56
(((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \
sys/dev/pci/drm/i915/gt/intel_lrc.c
65
if (*data & BIT(7)) { /* skip */
sys/dev/pci/drm/i915/gt/intel_lrc.c
66
count = *data++ & ~BIT(7);
sys/dev/pci/drm/i915/gt/intel_lrc.c
90
offset |= v & ~BIT(7);
sys/dev/pci/drm/i915/gt/intel_lrc.c
91
} while (v & BIT(7));
sys/dev/pci/drm/i915/gt/intel_mocs.c
432
HAS_GLOBAL_MOCS = BIT(0),
sys/dev/pci/drm/i915/gt/intel_mocs.c
433
HAS_ENGINE_MOCS = BIT(1),
sys/dev/pci/drm/i915/gt/intel_mocs.c
434
HAS_RENDER_L3CC = BIT(2),
sys/dev/pci/drm/i915/gt/intel_region_lmem.c
81
if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
sys/dev/pci/drm/i915/gt/intel_reset.c
420
if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
sys/dev/pci/drm/i915/gt/intel_reset.c
511
(BIT(engine->instance) & vdbox_sfc_access) == 0)
sys/dev/pci/drm/i915/gt/intel_reset.c
737
engine_mask = gt->info.engine_mask & ~BIT(GSC0);
sys/dev/pci/drm/i915/gt/intel_reset.h
29
#define I915_ERROR_CAPTURE BIT(0)
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
45
mask &= ~BIT(0);
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
887
if (!(ctx->remap_slice & BIT(i)))
sys/dev/pci/drm/i915/gt/intel_rps.c
1374
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_rps.c
1381
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_rps.c
1475
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_rps.c
1483
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_rps.c
1709
BIT(VLV_IOSF_SB_PUNIT) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1710
BIT(VLV_IOSF_SB_NC) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1711
BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/gt/intel_rps.c
1733
BIT(VLV_IOSF_SB_PUNIT) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1734
BIT(VLV_IOSF_SB_NC) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1735
BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/gt/intel_rps.c
1743
BIT(VLV_IOSF_SB_PUNIT) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1744
BIT(VLV_IOSF_SB_NC) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1745
BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/gt/intel_rps.c
1767
BIT(VLV_IOSF_SB_PUNIT) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1768
BIT(VLV_IOSF_SB_NC) |
sys/dev/pci/drm/i915/gt/intel_rps.c
1769
BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/gt/intel_rps.c
2036
if (params & BIT(31)) { /* OC supported */
sys/dev/pci/drm/i915/gt/intel_rps.c
2135
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_rps.c
2137
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_rps.c
832
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_rps.c
834
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/gt/intel_sseu.c
143
ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
sys/dev/pci/drm/i915/gt/intel_sseu.c
156
sseu->slice_mask |= BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
172
sseu->slice_mask |= BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
246
if (eu_en_fuse & BIT(eu))
sys/dev/pci/drm/i915/gt/intel_sseu.c
247
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
sys/dev/pci/drm/i915/gt/intel_sseu.c
284
if (eu_en_fuse & BIT(eu))
sys/dev/pci/drm/i915/gt/intel_sseu.c
285
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
sys/dev/pci/drm/i915/gt/intel_sseu.c
334
sseu->slice_mask = BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
342
sseu->subslice_mask.hsw[0] |= BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
351
sseu->subslice_mask.hsw[0] |= BIT(1);
sys/dev/pci/drm/i915/gt/intel_sseu.c
403
if (!(sseu->slice_mask & BIT(s)))
sys/dev/pci/drm/i915/gt/intel_sseu.c
431
sseu->subslice_7eu[s] |= BIT(ss);
sys/dev/pci/drm/i915/gt/intel_sseu.c
464
#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
sys/dev/pci/drm/i915/gt/intel_sseu.c
515
if (!(sseu->slice_mask & BIT(s)))
sys/dev/pci/drm/i915/gt/intel_sseu.c
582
sseu->slice_mask = BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
583
subslice_mask = BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
586
sseu->slice_mask = BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu.c
587
subslice_mask = BIT(0) | BIT(1);
sys/dev/pci/drm/i915/gt/intel_sseu.c
590
sseu->slice_mask = BIT(0) | BIT(1);
sys/dev/pci/drm/i915/gt/intel_sseu.c
591
subslice_mask = BIT(0) | BIT(1);
sys/dev/pci/drm/i915/gt/intel_sseu.c
887
slice_mask |= BIT(i);
sys/dev/pci/drm/i915/gt/intel_sseu.h
132
return sseu->subslice_mask.hsw[slice] & BIT(subslice);
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
140
sseu->slice_mask |= BIT(s);
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
153
sseu->subslice_mask.hsw[s] |= BIT(ss);
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
36
sseu->slice_mask = BIT(0);
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
37
sseu->subslice_mask.hsw[0] |= BIT(ss);
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
87
sseu->slice_mask |= BIT(s);
sys/dev/pci/drm/i915/gt/intel_timeline.c
314
if (TIMELINE_SEQNO_BYTES <= BIT(5) && (next_ofs & BIT(5)))
sys/dev/pci/drm/i915/gt/intel_timeline.c
315
next_ofs = offset_in_page(next_ofs + BIT(5));
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1326
if (gt->info.l3bank_mask & BIT(subslice))
sys/dev/pci/drm/i915/gt/mock_engine.c
360
engine->base.mask = BIT(id);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3555
#define BATCH BIT(0)
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3716
#define CHAIN BIT(0)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1736
reset_count = fake_hangcheck(gt, BIT(id));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
863
#define TEST_ACTIVE BIT(0)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
864
#define TEST_OTHERS BIT(1)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
865
#define TEST_SELF BIT(2)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
866
#define TEST_PRIORITY BIT(3)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1047
(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1107
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1123
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1205
(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1245
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1370
(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
256
} while (!err && (lrc[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
413
unsigned int mask = BIT(order) - 1;
sys/dev/pci/drm/i915/gt/selftest_timeline.c
74
SHUFFLE = BIT(0),
sys/dev/pci/drm/i915/gt/selftest_tlb.c
118
*cs++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
53
#define GUC_CTB_STATUS_OVERFLOW BIT(0)
sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
54
#define GUC_CTB_STATUS_UNDERFLOW BIT(1)
sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
55
#define GUC_CTB_STATUS_MISMATCH BIT(2)
sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
56
#define GUC_CTB_STATUS_UNUSED BIT(3)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
56
#define GCAP_PARSED_REGLIST_INDEX_GLOBAL BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
57
#define GCAP_PARSED_REGLIST_INDEX_ENGCLASS BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
58
#define GCAP_PARSED_REGLIST_INDEX_ENGINST BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h
103
#define INTEL_GSC_CPD_ENTRY_HUFFMAN_COMP BIT(25)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h
47
#define GSC_ACTION_FW_LOAD BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h
48
#define GSC_ACTION_SW_PROXY BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
61
#define GSC_OUTFLAG_MSG_PENDING BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
62
#define GSC_INFLAG_MSG_CLEANUP BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
532
BIT(gt->engine[GSC0]->instance));
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1023
if (keep_reglist_mask & BIT(i)) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h
125
#define INTEL_GUC_CT_SEND_NB BIT(31)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
100
#define GUC_WA_CONTEXT_ISOLATION BIT(15)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
101
#define GUC_WA_RCS_CCS_SWITCHOUT BIT(16)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
102
#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
103
#define GUC_WA_POLLCS BIT(18)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
104
#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
105
#define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
108
#define GUC_CTL_ENABLE_GUC_PXP_CTL BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
109
#define GUC_CTL_ENABLE_SLPC BIT(2)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
110
#define GUC_CTL_DISABLE_SCHEDULER BIT(14)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
148
#define GUC_ENGINE_ALL_INSTANCES BIT(7)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
243
#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
246
#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE_V69 BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
326
#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
374
#define GUC_REGSET_MASKED BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
375
#define GUC_REGSET_NEEDS_STEERING BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
376
#define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
377
#define GUC_REGSET_RESTORE_ONLY BIT(3)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
504
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
505
INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30),
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
73
#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
74
#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
75
#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
76
#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
77
#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
78
#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
79
#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
80
#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
83
#define GUC_LOG_VALID BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
84
#define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
85
#define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
86
#define GUC_LOG_LOG_ALLOC_UNITS BIT(3)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
96
#define GUC_WA_GAM_CREDITS BIT(10)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
97
#define GUC_WA_DUAL_QUEUE BIT(11)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
98
#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h
99
#define GUC_WA_PRE_PARSER BIT(14)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
109
#define GUC_SEM_INTR_ROUTE_TO_GUC BIT(31)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
141
#define GUC_INTR_GUC2HOST BIT(15)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
142
#define GUC_INTR_EXEC_ERROR BIT(14)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
143
#define GUC_INTR_DISPLAY_EVENT BIT(13)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
144
#define GUC_INTR_SEM_SIG BIT(12)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
145
#define GUC_INTR_IOMMU2GUC BIT(11)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
146
#define GUC_INTR_DOORBELL_RANG BIT(10)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
147
#define GUC_INTR_DMA_DONE BIT(9)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
148
#define GUC_INTR_FATAL_ERROR BIT(8)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
149
#define GUC_INTR_NOTIF_ERROR BIT(7)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
150
#define GUC_INTR_SW_INT_6 BIT(6)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
151
#define GUC_INTR_SW_INT_5 BIT(5)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
152
#define GUC_INTR_SW_INT_4 BIT(4)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
153
#define GUC_INTR_SW_INT_3 BIT(3)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
154
#define GUC_INTR_SW_INT_2 BIT(2)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
155
#define GUC_INTR_SW_INT_1 BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h
156
#define GUC_INTR_SW_INT_0 BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
168
#define SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER BIT(0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
169
#define SCHED_STATE_DESTROYED BIT(1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
170
#define SCHED_STATE_PENDING_DISABLE BIT(2)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
171
#define SCHED_STATE_BANNED BIT(3)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
172
#define SCHED_STATE_ENABLED BIT(4)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
173
#define SCHED_STATE_PENDING_ENABLE BIT(5)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
174
#define SCHED_STATE_REGISTERED BIT(6)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
175
#define SCHED_STATE_POLICY_REQUIRED BIT(7)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
176
#define SCHED_STATE_CLOSED BIT(8)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
178
#define SCHED_STATE_BLOCKED BIT(SCHED_STATE_BLOCKED_SHIFT)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2733
if (ce->flags & BIT(CONTEXT_LOW_LATENCY))
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5675
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5720
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
sys/dev/pci/drm/i915/gt/uc/selftest_guc_multi_lrc.c
20
if (engines[j]->logical_mask & BIT(i)) {
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1677
if (cmd_val(s, 0) & BIT(18))
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1802
if (cmd_val(s, 0) & BIT(8) &&
sys/dev/pci/drm/i915/gvt/cmd_parser.c
428
#define R_RCS BIT(RCS0)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
429
#define R_VCS1 BIT(VCS0)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
430
#define R_VCS2 BIT(VCS1)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
432
#define R_BCS BIT(BCS0)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
433
#define R_VECS BIT(VECS0)
sys/dev/pci/drm/i915/gvt/display.c
246
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
sys/dev/pci/drm/i915/gvt/display.c
251
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
sys/dev/pci/drm/i915/gvt/display.c
252
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
sys/dev/pci/drm/i915/gvt/display.c
280
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
sys/dev/pci/drm/i915/gvt/display.c
284
BIT(30);
sys/dev/pci/drm/i915/gvt/display.c
310
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
sys/dev/pci/drm/i915/gvt/display.c
314
BIT(30);
sys/dev/pci/drm/i915/gvt/display.c
341
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
sys/dev/pci/drm/i915/gvt/display.c
345
BIT(30);
sys/dev/pci/drm/i915/gvt/gtt.c
295
#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
sys/dev/pci/drm/i915/gvt/handlers.c
1899
if (v & BIT(0)) {
sys/dev/pci/drm/i915/gvt/handlers.c
1906
if (v & BIT(1)) {
sys/dev/pci/drm/i915/gvt/handlers.c
340
engine_mask |= BIT(RCS0);
sys/dev/pci/drm/i915/gvt/handlers.c
344
engine_mask |= BIT(VCS0);
sys/dev/pci/drm/i915/gvt/handlers.c
348
engine_mask |= BIT(BCS0);
sys/dev/pci/drm/i915/gvt/handlers.c
352
engine_mask |= BIT(VECS0);
sys/dev/pci/drm/i915/gvt/handlers.c
356
engine_mask |= BIT(VCS1);
sys/dev/pci/drm/i915/gvt/mmio.c
266
~(BIT(0) | BIT(1));
sys/dev/pci/drm/i915/gvt/mmio.c
272
~BIT(30);
sys/dev/pci/drm/i915/gvt/mmio.c
274
~BIT(30);
sys/dev/pci/drm/i915/gvt/scheduler.c
1101
!(vgpu->resetting_eng & BIT(ring_id))) {
sys/dev/pci/drm/i915/gvt/scheduler.c
1119
if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
sys/dev/pci/drm/i915/gvt/scheduler.c
1133
intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
sys/dev/pci/drm/i915/i915_active.h
184
#define I915_ACTIVE_AWAIT_EXCL BIT(0)
sys/dev/pci/drm/i915/i915_active.h
185
#define I915_ACTIVE_AWAIT_ACTIVE BIT(1)
sys/dev/pci/drm/i915/i915_active.h
186
#define I915_ACTIVE_AWAIT_BARRIER BIT(2)
sys/dev/pci/drm/i915/i915_active_types.h
37
#define I915_ACTIVE_RETIRE_SLEEPS BIT(0)
sys/dev/pci/drm/i915/i915_debugfs.c
560
#define DROP_UNBOUND BIT(0)
sys/dev/pci/drm/i915/i915_debugfs.c
561
#define DROP_BOUND BIT(1)
sys/dev/pci/drm/i915/i915_debugfs.c
562
#define DROP_RETIRE BIT(2)
sys/dev/pci/drm/i915/i915_debugfs.c
563
#define DROP_ACTIVE BIT(3)
sys/dev/pci/drm/i915/i915_debugfs.c
564
#define DROP_FREED BIT(4)
sys/dev/pci/drm/i915/i915_debugfs.c
565
#define DROP_SHRINK_ALL BIT(5)
sys/dev/pci/drm/i915/i915_debugfs.c
566
#define DROP_IDLE BIT(6)
sys/dev/pci/drm/i915/i915_debugfs.c
567
#define DROP_RESET_ACTIVE BIT(7)
sys/dev/pci/drm/i915/i915_debugfs.c
568
#define DROP_RESET_SEQNO BIT(8)
sys/dev/pci/drm/i915/i915_debugfs.c
569
#define DROP_RCU BIT(9)
sys/dev/pci/drm/i915/i915_drv.h
498
return info->platform_mask[pi] & BIT(pb);
sys/dev/pci/drm/i915/i915_drv.h
518
return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
sys/dev/pci/drm/i915/i915_drv.h
714
#define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id))
sys/dev/pci/drm/i915/i915_gem.h
137
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
sys/dev/pci/drm/i915/i915_gem.h
68
#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
sys/dev/pci/drm/i915/i915_gem.h
69
#define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
sys/dev/pci/drm/i915/i915_gem.h
70
#define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
sys/dev/pci/drm/i915/i915_gem.h
71
#define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3)
sys/dev/pci/drm/i915/i915_gem.h
72
#define I915_GEM_OBJECT_UNBIND_ASYNC BIT(4)
sys/dev/pci/drm/i915/i915_gpu_error.c
2047
if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
sys/dev/pci/drm/i915/i915_gpu_error.c
2099
hung_classes |= BIT(cs->engine->uabi_class);
sys/dev/pci/drm/i915/i915_gpu_error.c
880
if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
sys/dev/pci/drm/i915/i915_gpu_error.h
263
#define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
sys/dev/pci/drm/i915/i915_mitigations.c
109
if (local & BIT(BITS_PER_LONG - 1)) {
sys/dev/pci/drm/i915/i915_mitigations.c
118
if ((local & BIT(i)) != enable)
sys/dev/pci/drm/i915/i915_mitigations.c
27
return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
sys/dev/pci/drm/i915/i915_mitigations.c
79
new |= BIT(i);
sys/dev/pci/drm/i915/i915_mitigations.c
81
new &= ~BIT(i);
sys/dev/pci/drm/i915/i915_params.h
33
#define ENABLE_GUC_SUBMISSION BIT(0)
sys/dev/pci/drm/i915/i915_params.h
34
#define ENABLE_GUC_LOAD_HUC BIT(1)
sys/dev/pci/drm/i915/i915_pci.c
102
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/i915_pci.c
134
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/i915_pci.c
197
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/i915_pci.c
225
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
sys/dev/pci/drm/i915/i915_pci.c
233
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
sys/dev/pci/drm/i915/i915_pci.c
239
.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
sys/dev/pci/drm/i915/i915_pci.c
265
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
sys/dev/pci/drm/i915/i915_pci.c
313
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
sys/dev/pci/drm/i915/i915_pci.c
380
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
sys/dev/pci/drm/i915/i915_pci.c
388
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
sys/dev/pci/drm/i915/i915_pci.c
447
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
sys/dev/pci/drm/i915/i915_pci.c
453
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
sys/dev/pci/drm/i915/i915_pci.c
498
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
sys/dev/pci/drm/i915/i915_pci.c
513
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
sys/dev/pci/drm/i915/i915_pci.c
560
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
sys/dev/pci/drm/i915/i915_pci.c
581
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
sys/dev/pci/drm/i915/i915_pci.c
614
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
620
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
sys/dev/pci/drm/i915/i915_pci.c
627
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
sys/dev/pci/drm/i915/i915_pci.c
643
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
650
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
sys/dev/pci/drm/i915/i915_pci.c
654
.memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_LMEM_0) | BIT(INTEL_REGION_STOLEN_LMEM), \
sys/dev/pci/drm/i915/i915_pci.c
667
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
sys/dev/pci/drm/i915/i915_pci.c
668
BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
677
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
685
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
734
BIT(RCS0) | BIT(BCS0) | \
sys/dev/pci/drm/i915/i915_pci.c
735
BIT(VECS0) | BIT(VECS1) | \
sys/dev/pci/drm/i915/i915_pci.c
736
BIT(VCS0) | BIT(VCS2) | \
sys/dev/pci/drm/i915/i915_pci.c
737
BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
sys/dev/pci/drm/i915/i915_pci.c
755
.engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),
sys/dev/pci/drm/i915/i915_pci.c
78
.memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_SMEM)
sys/dev/pci/drm/i915/i915_pci.c
780
.memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_LMEM),
sys/dev/pci/drm/i915/i915_pci.c
781
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
sys/dev/pci/drm/i915/i915_pci.c
87
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/i915_perf.c
5077
perf->gen8_valid_ctx_bit = BIT(25);
sys/dev/pci/drm/i915/i915_perf.c
5082
perf->gen8_valid_ctx_bit = BIT(16);
sys/dev/pci/drm/i915/i915_perf.c
5087
perf->gen8_valid_ctx_bit = BIT(16);
sys/dev/pci/drm/i915/i915_perf.c
5090
perf->gen8_valid_ctx_bit = BIT(16);
sys/dev/pci/drm/i915/i915_pmu.c
124
return BIT(bit);
sys/dev/pci/drm/i915/i915_pmu.c
172
enable &= ~BIT(I915_SAMPLE_BUSY);
sys/dev/pci/drm/i915/i915_pmu.c
27
(BIT(I915_SAMPLE_BUSY) | \
sys/dev/pci/drm/i915/i915_pmu.c
28
BIT(I915_SAMPLE_WAIT) | \
sys/dev/pci/drm/i915/i915_pmu.c
29
BIT(I915_SAMPLE_SEMA))
sys/dev/pci/drm/i915/i915_pmu.c
313
pmu->unparked &= ~BIT(gt->info.id);
sys/dev/pci/drm/i915/i915_pmu.c
335
pmu->unparked |= BIT(gt->info.id);
sys/dev/pci/drm/i915/i915_pmu.c
527
if (!(pmu->unparked & BIT(i)))
sys/dev/pci/drm/i915/i915_pmu.c
753
pmu->enable |= BIT(bit);
sys/dev/pci/drm/i915/i915_pmu.c
781
engine->pmu.enable |= BIT(sample);
sys/dev/pci/drm/i915/i915_pmu.c
825
engine->pmu.enable &= ~BIT(sample);
sys/dev/pci/drm/i915/i915_pmu.c
835
pmu->enable &= ~BIT(bit);
sys/dev/pci/drm/i915/i915_ptr_util.h
11
(typeof(ptr))(__v & -BIT(n)); \
sys/dev/pci/drm/i915/i915_ptr_util.h
14
#define ptr_unmask_bits(ptr, n) ((unsigned long)(ptr) & (BIT(n) - 1))
sys/dev/pci/drm/i915/i915_ptr_util.h
18
*(bits) = __v & (BIT(n) - 1); \
sys/dev/pci/drm/i915/i915_ptr_util.h
19
(typeof(ptr))(__v & -BIT(n)); \
sys/dev/pci/drm/i915/i915_ptr_util.h
24
GEM_BUG_ON(__bits & -BIT(n)); \
sys/dev/pci/drm/i915/i915_pvinfo.h
57
#define VGT_CAPS_FULL_PPGTT BIT(2)
sys/dev/pci/drm/i915/i915_pvinfo.h
58
#define VGT_CAPS_HWSP_EMULATION BIT(3)
sys/dev/pci/drm/i915/i915_pvinfo.h
59
#define VGT_CAPS_HUGE_GTT BIT(4)
sys/dev/pci/drm/i915/i915_reg.h
568
#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
sys/dev/pci/drm/i915/i915_request.h
450
#define I915_WAIT_INTERRUPTIBLE BIT(0)
sys/dev/pci/drm/i915/i915_request.h
451
#define I915_WAIT_PRIORITY BIT(1) /* small priority bump for the request */
sys/dev/pci/drm/i915/i915_request.h
452
#define I915_WAIT_ALL BIT(2) /* used by i915_gem_object_wait() */
sys/dev/pci/drm/i915/i915_scheduler_types.h
68
#define I915_SCHED_HAS_EXTERNAL_CHAIN BIT(0)
sys/dev/pci/drm/i915/i915_scheduler_types.h
79
#define I915_DEPENDENCY_ALLOC BIT(0)
sys/dev/pci/drm/i915/i915_scheduler_types.h
80
#define I915_DEPENDENCY_EXTERNAL BIT(1)
sys/dev/pci/drm/i915/i915_scheduler_types.h
81
#define I915_DEPENDENCY_WEAK BIT(2)
sys/dev/pci/drm/i915/i915_sw_fence.c
29
#define I915_SW_FENCE_FLAG_FENCE BIT(WQ_FLAG_BITS - 1)
sys/dev/pci/drm/i915/i915_sw_fence.c
30
#define I915_SW_FENCE_FLAG_ALLOC BIT(WQ_FLAG_BITS - 2)
sys/dev/pci/drm/i915/i915_syncmap.c
189
if (!(p->bitmap & BIT(idx)))
sys/dev/pci/drm/i915/i915_syncmap.c
215
p->bitmap |= BIT(idx);
sys/dev/pci/drm/i915/i915_syncmap.c
223
p->bitmap |= BIT(idx);
sys/dev/pci/drm/i915/i915_syncmap.c
297
GEM_BUG_ON(!(p->parent->bitmap & BIT(idx)));
sys/dev/pci/drm/i915/i915_sysfs.c
128
ctx->remap_slice |= BIT(slice);
sys/dev/pci/drm/i915/i915_utils.h
94
mask &= ~BIT(__idx); \
sys/dev/pci/drm/i915/i915_vma.h
49
#define I915_VMA_RELEASE_MAP BIT(0)
sys/dev/pci/drm/i915/i915_vma.h
57
#define __EXEC_OBJECT_NO_RESERVE BIT(31)
sys/dev/pci/drm/i915/i915_vma.h
58
#define __EXEC_OBJECT_NO_REQUEST_AWAIT BIT(30)
sys/dev/pci/drm/i915/i915_vma_types.h
200
#define I915_VMA_GLOBAL_BIND ((int)BIT(I915_VMA_GLOBAL_BIND_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
201
#define I915_VMA_LOCAL_BIND ((int)BIT(I915_VMA_LOCAL_BIND_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
206
#define I915_VMA_ERROR ((int)BIT(I915_VMA_ERROR_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
213
#define I915_VMA_GGTT ((int)BIT(I915_VMA_GGTT_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
214
#define I915_VMA_CAN_FENCE ((int)BIT(I915_VMA_CAN_FENCE_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
215
#define I915_VMA_USERFAULT ((int)BIT(I915_VMA_USERFAULT_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
216
#define I915_VMA_GGTT_WRITE ((int)BIT(I915_VMA_GGTT_WRITE_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
219
#define I915_VMA_SCANOUT ((int)BIT(I915_VMA_SCANOUT_BIT))
sys/dev/pci/drm/i915/i915_vma_types.h
224
#define I915_VMA_PAGES_ACTIVE (BIT(24) | 1)
sys/dev/pci/drm/i915/intel_device_info.c
239
RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
sys/dev/pci/drm/i915/intel_device_info.c
244
mask = BIT(INTEL_SUBPLATFORM_ULT);
sys/dev/pci/drm/i915/intel_device_info.c
247
mask = BIT(INTEL_SUBPLATFORM_ULX);
sys/dev/pci/drm/i915/intel_device_info.c
250
mask |= BIT(INTEL_SUBPLATFORM_ULT);
sys/dev/pci/drm/i915/intel_device_info.c
254
mask = BIT(INTEL_SUBPLATFORM_PORTF);
sys/dev/pci/drm/i915/intel_device_info.c
257
mask = BIT(INTEL_SUBPLATFORM_UY);
sys/dev/pci/drm/i915/intel_device_info.c
260
mask = BIT(INTEL_SUBPLATFORM_N);
sys/dev/pci/drm/i915/intel_device_info.c
263
mask = BIT(INTEL_SUBPLATFORM_RPL);
sys/dev/pci/drm/i915/intel_device_info.c
266
mask |= BIT(INTEL_SUBPLATFORM_RPLU);
sys/dev/pci/drm/i915/intel_device_info.c
269
mask = BIT(INTEL_SUBPLATFORM_G10);
sys/dev/pci/drm/i915/intel_device_info.c
272
mask = BIT(INTEL_SUBPLATFORM_G11);
sys/dev/pci/drm/i915/intel_device_info.c
275
mask = BIT(INTEL_SUBPLATFORM_G12);
sys/dev/pci/drm/i915/intel_device_info.c
278
mask = BIT(INTEL_SUBPLATFORM_ARL_H);
sys/dev/pci/drm/i915/intel_device_info.c
281
mask = BIT(INTEL_SUBPLATFORM_ARL_U);
sys/dev/pci/drm/i915/intel_device_info.c
284
mask = BIT(INTEL_SUBPLATFORM_ARL_S);
sys/dev/pci/drm/i915/intel_device_info.c
290
mask |= BIT(INTEL_SUBPLATFORM_D);
sys/dev/pci/drm/i915/intel_device_info.h
103
#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
sys/dev/pci/drm/i915/intel_memory_region.h
41
#define I915_ALLOC_CONTIGUOUS BIT(0)
sys/dev/pci/drm/i915/intel_uncore.c
2140
d->mask = BIT(domain_id);
sys/dev/pci/drm/i915/intel_uncore.c
2148
uncore->fw_domains |= BIT(domain_id);
sys/dev/pci/drm/i915/intel_uncore.c
2168
uncore->fw_domains &= ~BIT(domain_id);
sys/dev/pci/drm/i915/intel_uncore.c
2634
if (fw_domains & BIT(domain_id))
sys/dev/pci/drm/i915/intel_uncore.c
2644
if (fw_domains & BIT(domain_id))
sys/dev/pci/drm/i915/intel_uncore.c
2648
if ((fw_domains & BIT(FW_DOMAIN_ID_GSC)) && !HAS_ENGINE(gt, GSC0))
sys/dev/pci/drm/i915/intel_uncore.h
152
#define UNCORE_HAS_FORCEWAKE BIT(0)
sys/dev/pci/drm/i915/intel_uncore.h
153
#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
sys/dev/pci/drm/i915/intel_uncore.h
154
#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
sys/dev/pci/drm/i915/intel_uncore.h
155
#define UNCORE_HAS_FIFO BIT(3)
sys/dev/pci/drm/i915/intel_uncore.h
156
#define UNCORE_NEEDS_FLR_ON_FINI BIT(4)
sys/dev/pci/drm/i915/intel_uncore.h
71
FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
sys/dev/pci/drm/i915/intel_uncore.h
72
FORCEWAKE_GT = BIT(FW_DOMAIN_ID_GT),
sys/dev/pci/drm/i915/intel_uncore.h
73
FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
sys/dev/pci/drm/i915/intel_uncore.h
74
FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
sys/dev/pci/drm/i915/intel_uncore.h
75
FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
sys/dev/pci/drm/i915/intel_uncore.h
76
FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
sys/dev/pci/drm/i915/intel_uncore.h
77
FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
sys/dev/pci/drm/i915/intel_uncore.h
78
FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4),
sys/dev/pci/drm/i915/intel_uncore.h
79
FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5),
sys/dev/pci/drm/i915/intel_uncore.h
80
FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6),
sys/dev/pci/drm/i915/intel_uncore.h
81
FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7),
sys/dev/pci/drm/i915/intel_uncore.h
82
FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
sys/dev/pci/drm/i915/intel_uncore.h
83
FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
sys/dev/pci/drm/i915/intel_uncore.h
84
FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2),
sys/dev/pci/drm/i915/intel_uncore.h
85
FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3),
sys/dev/pci/drm/i915/intel_uncore.h
86
FORCEWAKE_GSC = BIT(FW_DOMAIN_ID_GSC),
sys/dev/pci/drm/i915/intel_uncore.h
88
FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
sys/dev/pci/drm/i915/intel_wakeref.h
138
#define INTEL_WAKEREF_PUT_ASYNC BIT(0)
sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h
45
#define PXP43_INIT_SESSION_VALID BIT(0)
sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h
46
#define PXP43_INIT_SESSION_APPTYPE BIT(1)
sys/dev/pci/drm/i915/pxp/intel_pxp_irq.h
13
#define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1)
sys/dev/pci/drm/i915/pxp/intel_pxp_irq.h
14
#define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2)
sys/dev/pci/drm/i915/pxp/intel_pxp_irq.h
15
#define GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT BIT(3)
sys/dev/pci/drm/i915/pxp/intel_pxp_session.c
28
return sip & BIT(id);
sys/dev/pci/drm/i915/pxp/intel_pxp_session.c
35
u32 mask = BIT(id);
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
124
#define PXP_TERMINATION_REQUEST BIT(0)
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
125
#define PXP_TERMINATION_COMPLETE BIT(1)
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
126
#define PXP_INVAL_REQUIRED BIT(2)
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
127
#define PXP_EVENT_TYPE_IRQ BIT(3)
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
70
rem = round_up(obj->base.size, BIT(31)) >> 31;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
84
unsigned long len = min_t(typeof(rem), rem, BIT(31));
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
42
if (last & BIT(depth - d - 1))
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
432
if (sync->bitmap != BIT(idx + 1) - 1) {
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
436
BIT(idx + 1) - 1, idx + 1);
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
498
if (sync->bitmap != BIT(KSYNCMAP) - 1) {
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
501
BIT(KSYNCMAP) - 1, KSYNCMAP);
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
530
if (leaf->bitmap != BIT(idx)) {
sys/dev/pci/drm/i915/selftests/igt_spinner.c
187
*batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
sys/dev/pci/drm/i915/selftests/mock_gem_device.c
127
.memory_regions = BIT(INTEL_REGION_SMEM),
sys/dev/pci/drm/i915/selftests/mock_gem_device.c
128
.platform_engine_mask = BIT(0),
sys/dev/pci/drm/i915/selftests/mock_gem_device.c
238
to_gt(i915)->info.engine_mask = BIT(0);
sys/dev/pci/drm/i915/selftests/scatterlist.c
199
BIT(12) >> PAGE_SHIFT,
sys/dev/pci/drm/i915/selftests/scatterlist.c
200
BIT(16) >> PAGE_SHIFT,
sys/dev/pci/drm/i915/selftests/scatterlist.c
201
BIT(21) >> PAGE_SHIFT,
sys/dev/pci/drm/i915/selftests/scatterlist.c
287
unsigned long size = BIT(prime);
sys/dev/pci/drm/i915/soc/intel_dram.c
108
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/soc/intel_dram.c
110
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_CCK));
sys/dev/pci/drm/i915/soc/intel_dram.c
124
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/soc/intel_dram.c
126
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
sys/dev/pci/drm/i915/vlv_iosf_sb.c
191
drm_WARN_ON(&i915->drm, !(i915->vlv_iosf_sb.locked_unit_mask & BIT(unit)));
sys/dev/pci/drm/i915/vlv_iosf_sb.c
210
drm_WARN_ON(&i915->drm, !(i915->vlv_iosf_sb.locked_unit_mask & BIT(unit)));
sys/dev/pci/drm/i915/vlv_iosf_sb.c
64
if (unit_mask & BIT(VLV_IOSF_SB_PUNIT))
sys/dev/pci/drm/i915/vlv_iosf_sb.c
82
if (unit_mask & BIT(VLV_IOSF_SB_PUNIT))
sys/dev/pci/drm/include/drm/display/drm_dp.h
1396
# define DP_BCAPS_REPEATER_PRESENT BIT(1)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1397
# define DP_BCAPS_HDCP_CAPABLE BIT(0)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1399
# define DP_BSTATUS_REAUTH_REQ BIT(3)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1400
# define DP_BSTATUS_LINK_FAILURE BIT(2)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1401
# define DP_BSTATUS_R0_PRIME_READY BIT(1)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1402
# define DP_BSTATUS_READY BIT(0)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1553
# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1554
# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
sys/dev/pci/drm/include/drm/display/drm_dp.h
1620
#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
sys/dev/pci/drm/include/drm/display/drm_dp.h
1621
#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
sys/dev/pci/drm/include/drm/display/drm_dp.h
1622
#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
sys/dev/pci/drm/include/drm/display/drm_dp.h
1623
#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
sys/dev/pci/drm/include/drm/display/drm_dp.h
1624
#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
sys/dev/pci/drm/include/drm/display/drm_dp.h
729
#define DP_SDP_CRC16_128B132B_EN BIT(0)
sys/dev/pci/drm/include/drm/display/drm_dp.h
740
# define DP_PSR_ENABLE BIT(0)
sys/dev/pci/drm/include/drm/display/drm_dp.h
741
# define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
sys/dev/pci/drm/include/drm/display/drm_dp.h
742
# define DP_PSR_CRC_VERIFICATION BIT(2)
sys/dev/pci/drm/include/drm/display/drm_dp.h
743
# define DP_PSR_FRAME_CAPTURE BIT(3)
sys/dev/pci/drm/include/drm/display/drm_dp.h
744
# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */
sys/dev/pci/drm/include/drm/display/drm_dp.h
745
# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */
sys/dev/pci/drm/include/drm/display/drm_dp.h
746
# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */
sys/dev/pci/drm/include/drm/display/drm_dp.h
747
# define DP_PSR_ENABLE_SU_REGION_ET BIT(7) /* eDP 1.5 */
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
835
return desc->quirks & BIT(quirk);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
975
#define DRM_DP_BW_OVERHEAD_MST BIT(0)
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
976
#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
977
#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
978
#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
979
#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
111
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
112
#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
116
#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
119
#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
120
#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
121
#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
123
#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
245
#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
253
#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
254
#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
26
#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
27
#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
42
#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
43
#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
124
#define DRM_PLANE_COMMIT_ACTIVE_ONLY BIT(0)
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
125
#define DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET BIT(1)
sys/dev/pci/drm/include/drm/drm_bridge.h
58
DRM_BRIDGE_ATTACH_NO_CONNECTOR = BIT(0),
sys/dev/pci/drm/include/drm/drm_bridge.h
923
DRM_BRIDGE_OP_DETECT = BIT(0),
sys/dev/pci/drm/include/drm/drm_bridge.h
929
DRM_BRIDGE_OP_EDID = BIT(1),
sys/dev/pci/drm/include/drm/drm_bridge.h
937
DRM_BRIDGE_OP_HPD = BIT(2),
sys/dev/pci/drm/include/drm/drm_bridge.h
944
DRM_BRIDGE_OP_MODES = BIT(3),
sys/dev/pci/drm/include/drm/drm_bridge.h
954
DRM_BRIDGE_OP_HDMI = BIT(4),
sys/dev/pci/drm/include/drm/drm_bridge.h
967
DRM_BRIDGE_OP_HDMI_AUDIO = BIT(5),
sys/dev/pci/drm/include/drm/drm_bridge.h
980
DRM_BRIDGE_OP_DP_AUDIO = BIT(6),
sys/dev/pci/drm/include/drm/drm_bridge.h
985
DRM_BRIDGE_OP_HDMI_CEC_NOTIFIER = BIT(7),
sys/dev/pci/drm/include/drm/drm_bridge.h
990
DRM_BRIDGE_OP_HDMI_CEC_ADAPTER = BIT(8),
sys/dev/pci/drm/include/drm/drm_buddy.h
17
#define DRM_BUDDY_RANGE_ALLOCATION BIT(0)
sys/dev/pci/drm/include/drm/drm_buddy.h
18
#define DRM_BUDDY_TOPDOWN_ALLOCATION BIT(1)
sys/dev/pci/drm/include/drm/drm_buddy.h
19
#define DRM_BUDDY_CONTIGUOUS_ALLOCATION BIT(2)
sys/dev/pci/drm/include/drm/drm_buddy.h
20
#define DRM_BUDDY_CLEAR_ALLOCATION BIT(3)
sys/dev/pci/drm/include/drm/drm_buddy.h
21
#define DRM_BUDDY_CLEARED BIT(4)
sys/dev/pci/drm/include/drm/drm_buddy.h
22
#define DRM_BUDDY_TRIM_DISABLE BIT(5)
sys/dev/pci/drm/include/drm/drm_color_mgmt.h
109
DRM_COLOR_LUT_EQUAL_CHANNELS = BIT(0),
sys/dev/pci/drm/include/drm/drm_color_mgmt.h
117
DRM_COLOR_LUT_NON_DECREASING = BIT(1),
sys/dev/pci/drm/include/drm/drm_connector.h
583
DRM_BUS_FLAG_DE_LOW = BIT(0),
sys/dev/pci/drm/include/drm/drm_connector.h
590
DRM_BUS_FLAG_DE_HIGH = BIT(1),
sys/dev/pci/drm/include/drm/drm_connector.h
597
DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = BIT(2),
sys/dev/pci/drm/include/drm/drm_connector.h
604
DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = BIT(3),
sys/dev/pci/drm/include/drm/drm_connector.h
625
DRM_BUS_FLAG_DATA_MSB_TO_LSB = BIT(4),
sys/dev/pci/drm/include/drm/drm_connector.h
632
DRM_BUS_FLAG_DATA_LSB_TO_MSB = BIT(5),
sys/dev/pci/drm/include/drm/drm_connector.h
639
DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = BIT(6),
sys/dev/pci/drm/include/drm/drm_connector.h
646
DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = BIT(7),
sys/dev/pci/drm/include/drm/drm_connector.h
667
DRM_BUS_FLAG_SHARP_SIGNALS = BIT(8),
sys/dev/pci/drm/include/drm/drm_device.h
39
#define DRM_WEDGE_RECOVERY_NONE BIT(0) /* optional telemetry collection */
sys/dev/pci/drm/include/drm/drm_device.h
40
#define DRM_WEDGE_RECOVERY_REBIND BIT(1) /* unbind + bind driver */
sys/dev/pci/drm/include/drm/drm_device.h
41
#define DRM_WEDGE_RECOVERY_BUS_RESET BIT(2) /* unbind + reset bus device + bind */
sys/dev/pci/drm/include/drm/drm_device.h
42
#define DRM_WEDGE_RECOVERY_VENDOR BIT(3) /* vendor specific recovery method */
sys/dev/pci/drm/include/drm/drm_drv.h
103
DRIVER_SYNCOBJ_TIMELINE = BIT(6),
sys/dev/pci/drm/include/drm/drm_drv.h
111
DRIVER_COMPUTE_ACCEL = BIT(7),
sys/dev/pci/drm/include/drm/drm_drv.h
117
DRIVER_GEM_GPUVA = BIT(8),
sys/dev/pci/drm/include/drm/drm_drv.h
126
DRIVER_CURSOR_HOTSPOT = BIT(9),
sys/dev/pci/drm/include/drm/drm_drv.h
136
DRIVER_USE_AGP = BIT(25),
sys/dev/pci/drm/include/drm/drm_drv.h
142
DRIVER_LEGACY = BIT(26),
sys/dev/pci/drm/include/drm/drm_drv.h
149
DRIVER_PCI_DMA = BIT(27),
sys/dev/pci/drm/include/drm/drm_drv.h
157
DRIVER_SG = BIT(28),
sys/dev/pci/drm/include/drm/drm_drv.h
165
DRIVER_HAVE_DMA = BIT(29),
sys/dev/pci/drm/include/drm/drm_drv.h
171
DRIVER_HAVE_IRQ = BIT(30),
sys/dev/pci/drm/include/drm/drm_drv.h
66
DRIVER_GEM = BIT(0),
sys/dev/pci/drm/include/drm/drm_drv.h
72
DRIVER_MODESET = BIT(1),
sys/dev/pci/drm/include/drm/drm_drv.h
79
DRIVER_RENDER = BIT(3),
sys/dev/pci/drm/include/drm/drm_drv.h
89
DRIVER_ATOMIC = BIT(4),
sys/dev/pci/drm/include/drm/drm_drv.h
96
DRIVER_SYNCOBJ = BIT(5),
sys/dev/pci/drm/include/drm/drm_exec.h
10
#define DRM_EXEC_IGNORE_DUPLICATES BIT(1)
sys/dev/pci/drm/include/drm/drm_exec.h
9
#define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0)
sys/dev/pci/drm/include/drm/drm_framebuffer.h
104
#define DRM_FRAMEBUFFER_HAS_HANDLE_REF(_i) BIT(0u + (_i))
sys/dev/pci/drm/include/drm/drm_gem.h
64
DRM_GEM_OBJECT_RESIDENT = BIT(0),
sys/dev/pci/drm/include/drm/drm_gem.h
65
DRM_GEM_OBJECT_PURGEABLE = BIT(1),
sys/dev/pci/drm/include/drm/drm_gem.h
66
DRM_GEM_OBJECT_ACTIVE = BIT(2),
sys/dev/pci/drm/include/drm/drm_gpuvm.h
197
DRM_GPUVM_RESV_PROTECTED = BIT(0),
sys/dev/pci/drm/include/drm/drm_gpuvm.h
207
DRM_GPUVM_IMMEDIATE_MODE = BIT(1),
sys/dev/pci/drm/include/drm/drm_gpuvm.h
212
DRM_GPUVM_USERBITS = BIT(2),
sys/dev/pci/drm/include/drm/drm_ioctl.h
105
DRM_MASTER = BIT(1),
sys/dev/pci/drm/include/drm/drm_ioctl.h
116
DRM_ROOT_ONLY = BIT(2),
sys/dev/pci/drm/include/drm/drm_ioctl.h
126
DRM_RENDER_ALLOW = BIT(5),
sys/dev/pci/drm/include/drm/drm_ioctl.h
93
DRM_AUTH = BIT(0),
sys/dev/pci/drm/include/drm/drm_mm.h
123
DRM_MM_INSERT_ONCE = BIT(31),
sys/dev/pci/drm/include/drm/drm_modeset_lock.h
98
#define DRM_MODESET_ACQUIRE_INTERRUPTIBLE BIT(0)
sys/dev/pci/drm/include/drm/drm_print.h
146
return unlikely(__drm_debug & BIT(category));
sys/dev/pci/drm/include/drm/gud.h
100
#define GUD_DISPLAY_MODE_FLAG_NCSYNC BIT(8)
sys/dev/pci/drm/include/drm/gud.h
101
#define GUD_DISPLAY_MODE_FLAG_HSKEW BIT(9)
sys/dev/pci/drm/include/drm/gud.h
103
#define GUD_DISPLAY_MODE_FLAG_DBLCLK BIT(12)
sys/dev/pci/drm/include/drm/gud.h
104
#define GUD_DISPLAY_MODE_FLAG_CLKDIV2 BIT(13)
sys/dev/pci/drm/include/drm/gud.h
113
#define GUD_DISPLAY_MODE_FLAG_PREFERRED BIT(10)
sys/dev/pci/drm/include/drm/gud.h
136
#define GUD_CONNECTOR_FLAGS_POLL_STATUS BIT(0)
sys/dev/pci/drm/include/drm/gud.h
137
#define GUD_CONNECTOR_FLAGS_INTERLACE BIT(1)
sys/dev/pci/drm/include/drm/gud.h
138
#define GUD_CONNECTOR_FLAGS_DOUBLESCAN BIT(2)
sys/dev/pci/drm/include/drm/gud.h
221
#define GUD_ROTATION_0 BIT(0)
sys/dev/pci/drm/include/drm/gud.h
222
#define GUD_ROTATION_90 BIT(1)
sys/dev/pci/drm/include/drm/gud.h
223
#define GUD_ROTATION_180 BIT(2)
sys/dev/pci/drm/include/drm/gud.h
224
#define GUD_ROTATION_270 BIT(3)
sys/dev/pci/drm/include/drm/gud.h
225
#define GUD_ROTATION_REFLECT_X BIT(4)
sys/dev/pci/drm/include/drm/gud.h
226
#define GUD_ROTATION_REFLECT_Y BIT(5)
sys/dev/pci/drm/include/drm/gud.h
302
#define GUD_CONNECTOR_STATUS_CHANGED BIT(7)
sys/dev/pci/drm/include/drm/gud.h
44
#define GUD_DISPLAY_FLAG_STATUS_ON_SET BIT(0)
sys/dev/pci/drm/include/drm/gud.h
45
#define GUD_DISPLAY_FLAG_FULL_UPDATE BIT(1)
sys/dev/pci/drm/include/drm/gud.h
47
#define GUD_COMPRESSION_LZ4 BIT(0)
sys/dev/pci/drm/include/drm/gud.h
92
#define GUD_DISPLAY_MODE_FLAG_PHSYNC BIT(0)
sys/dev/pci/drm/include/drm/gud.h
93
#define GUD_DISPLAY_MODE_FLAG_NHSYNC BIT(1)
sys/dev/pci/drm/include/drm/gud.h
94
#define GUD_DISPLAY_MODE_FLAG_PVSYNC BIT(2)
sys/dev/pci/drm/include/drm/gud.h
95
#define GUD_DISPLAY_MODE_FLAG_NVSYNC BIT(3)
sys/dev/pci/drm/include/drm/gud.h
96
#define GUD_DISPLAY_MODE_FLAG_INTERLACE BIT(4)
sys/dev/pci/drm/include/drm/gud.h
97
#define GUD_DISPLAY_MODE_FLAG_DBLSCAN BIT(5)
sys/dev/pci/drm/include/drm/gud.h
98
#define GUD_DISPLAY_MODE_FLAG_CSYNC BIT(6)
sys/dev/pci/drm/include/drm/gud.h
99
#define GUD_DISPLAY_MODE_FLAG_PCSYNC BIT(7)
sys/dev/pci/drm/include/drm/intel/intel_lb_mei_interface.h
19
#define INTEL_LB_FLAG_IS_PERSISTENT BIT(0)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
100
#define TTM_TT_FLAG_SWAPPED BIT(0)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
101
#define TTM_TT_FLAG_ZERO_ALLOC BIT(1)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
102
#define TTM_TT_FLAG_EXTERNAL BIT(2)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
103
#define TTM_TT_FLAG_EXTERNAL_MAPPABLE BIT(3)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
104
#define TTM_TT_FLAG_DECRYPTED BIT(4)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
105
#define TTM_TT_FLAG_BACKED_UP BIT(5)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
107
#define TTM_TT_FLAG_PRIV_POPULATED BIT(6)
sys/dev/pci/drm/include/linux/bits.h
19
((u32)(BIT(__n) + \
sys/dev/pci/drm/include/linux/bits.h
32
((u8)(BIT(__n) + \
sys/dev/pci/drm/include/linux/bits.h
91
((u16)(BIT(__n) + \
sys/dev/pci/if_ice.c
10772
if (!(vsi->tc_map & BIT(tc)))
sys/dev/pci/if_ice.c
18591
inkey.xlt2_cdid |= htole16(BIT(cdid) << ICE_CD_2_S);
sys/dev/pci/if_ice.c
18597
inkey.xlt2_cdid |= htole16(BIT(cdid) << ICE_CD_4_S);
sys/dev/pci/if_ice.c
18603
inkey.xlt2_cdid |= htole16(BIT(cdid) << ICE_CD_8_S);
sys/dev/pci/if_ice.c
2204
mask = (uint8_t)(BIT(ce_info->width) - 1);
sys/dev/pci/if_ice.c
22385
return !!(bitmap & BIT(tc));
sys/dev/pci/if_ice.c
2245
mask = BIT(ce_info->width) - 1;
sys/dev/pci/if_ice.c
2295
mask = BIT(ce_info->width) - 1;
sys/dev/pci/if_ice.c
23601
maxtcwilling = BIT(ICE_IEEE_ETS_WILLING_S);
sys/dev/pci/if_ice.c
23669
buf[0] = BIT(ICE_IEEE_PFC_WILLING_S);
sys/dev/pci/if_ice.c
23672
buf[0] |= BIT(ICE_IEEE_PFC_MBC_S);
sys/dev/pci/if_ice.c
27478
if (app->prio_map & BIT(up))
sys/dev/pci/if_ice.c
29259
const uint16_t l3_error = (BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |
sys/dev/pci/if_ice.c
29260
BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S));
sys/dev/pci/if_ice.c
29261
const uint16_t l4_error = (BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |
sys/dev/pci/if_ice.c
29262
BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S));
sys/dev/pci/if_ice.c
29264
BIT(ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S));
sys/dev/pci/if_ice.c
29269
if (!(status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_L3L4P_S)))
sys/dev/pci/if_ice.c
29307
if (is_ipv6 && (status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S)))
sys/dev/pci/if_ice.c
29373
if ((status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_DD_S)) == 0)
sys/dev/pci/if_ice.c
29399
eop = !!(status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_EOF_S));
sys/dev/pci/if_ice.c
29400
if (eop && (status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_RXE_S))) {
sys/dev/pci/if_ice.c
29412
if (status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
sys/dev/pci/if_ice.c
29419
BIT(ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S)) {
sys/dev/pci/if_ice.c
4398
flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
sys/dev/pci/if_icereg.h
10000
#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
sys/dev/pci/if_icereg.h
10001
#define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
sys/dev/pci/if_icereg.h
10005
#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
sys/dev/pci/if_icereg.h
10006
#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
sys/dev/pci/if_icereg.h
10007
#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
sys/dev/pci/if_icereg.h
10011
#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
sys/dev/pci/if_icereg.h
10012
#define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA BIT(3)
sys/dev/pci/if_icereg.h
10013
#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
sys/dev/pci/if_icereg.h
10017
#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
sys/dev/pci/if_icereg.h
10020
#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
sys/dev/pci/if_icereg.h
10021
#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
sys/dev/pci/if_icereg.h
10024
#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
sys/dev/pci/if_icereg.h
10035
#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
sys/dev/pci/if_icereg.h
10042
#define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5)
sys/dev/pci/if_icereg.h
10078
#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
sys/dev/pci/if_icereg.h
10084
#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
sys/dev/pci/if_icereg.h
10089
#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
sys/dev/pci/if_icereg.h
10116
#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
sys/dev/pci/if_icereg.h
10118
#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
sys/dev/pci/if_icereg.h
10126
#define ICE_AQ_VSI_FD_ENABLE BIT(0)
sys/dev/pci/if_icereg.h
10127
#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
sys/dev/pci/if_icereg.h
10128
#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
sys/dev/pci/if_icereg.h
10141
#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
sys/dev/pci/if_icereg.h
10146
#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
sys/dev/pci/if_icereg.h
102
#define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
10239
#define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
sys/dev/pci/if_icereg.h
10240
#define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
sys/dev/pci/if_icereg.h
10241
#define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
sys/dev/pci/if_icereg.h
10242
#define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
sys/dev/pci/if_icereg.h
1026
#define QTX_COMM_HEAD_RS_PENDING_M BIT(16)
sys/dev/pci/if_icereg.h
10307
#define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
sys/dev/pci/if_icereg.h
10308
#define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
sys/dev/pci/if_icereg.h
10318
#define ICE_SINGLE_ACT_VSI_LIST BIT(14)
sys/dev/pci/if_icereg.h
10319
#define ICE_SINGLE_ACT_VALID_BIT BIT(17)
sys/dev/pci/if_icereg.h
10320
#define ICE_SINGLE_ACT_DROP BIT(18)
sys/dev/pci/if_icereg.h
10328
#define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
sys/dev/pci/if_icereg.h
10332
#define ICE_SINGLE_ACT_EGRESS BIT(15)
sys/dev/pci/if_icereg.h
10333
#define ICE_SINGLE_ACT_INGRESS BIT(16)
sys/dev/pci/if_icereg.h
10334
#define ICE_SINGLE_ACT_PRUNET BIT(17)
sys/dev/pci/if_icereg.h
10342
#define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17)
sys/dev/pci/if_icereg.h
10344
#define ICE_SINGLE_ACT_PTR_BIT BIT(18)
sys/dev/pci/if_icereg.h
10397
#define ICE_LG_ACT_VSI_LIST BIT(13)
sys/dev/pci/if_icereg.h
10399
#define ICE_LG_ACT_VALID_BIT BIT(16)
sys/dev/pci/if_icereg.h
104
#define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
10407
#define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
sys/dev/pci/if_icereg.h
10411
#define ICE_LG_ACT_EGRESS BIT(14)
sys/dev/pci/if_icereg.h
10412
#define ICE_LG_ACT_INGRESS BIT(15)
sys/dev/pci/if_icereg.h
10413
#define ICE_LG_ACT_PRUNET BIT(16)
sys/dev/pci/if_icereg.h
1042
#define GL_FW_TOOL_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1044
#define GL_FW_TOOL_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1046
#define GL_FW_TOOL_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
10461
#define ICE_AQC_PFC_IGNORE_SET BIT(7)
sys/dev/pci/if_icereg.h
1048
#define GL_FW_TOOL_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
10483
#define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
sys/dev/pci/if_icereg.h
10484
#define ICE_AQC_PERSIST_DCB_CFG BIT(1)
sys/dev/pci/if_icereg.h
10486
#define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
sys/dev/pci/if_icereg.h
10487
#define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
sys/dev/pci/if_icereg.h
10504
#define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0)
sys/dev/pci/if_icereg.h
10505
#define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1)
sys/dev/pci/if_icereg.h
10506
#define ICE_AQC_TX_TOPO_FLAGS_SET_PSM BIT(2)
sys/dev/pci/if_icereg.h
10507
#define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4)
sys/dev/pci/if_icereg.h
10508
#define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5)
sys/dev/pci/if_icereg.h
10563
#define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
sys/dev/pci/if_icereg.h
10564
#define ICE_AQC_ELEM_VALID_CIR BIT(1)
sys/dev/pci/if_icereg.h
10565
#define ICE_AQC_ELEM_VALID_EIR BIT(2)
sys/dev/pci/if_icereg.h
10566
#define ICE_AQC_ELEM_VALID_SHARED BIT(3)
sys/dev/pci/if_icereg.h
106
#define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1067
#define GL_FW_TOOL_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1069
#define GL_FW_TOOL_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1071
#define GL_FW_TOOL_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1073
#define GL_FW_TOOL_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
10760
#define ICE_AQC_GET_PHY_RQM BIT(0)
sys/dev/pci/if_icereg.h
10771
#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
sys/dev/pci/if_icereg.h
10772
#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
sys/dev/pci/if_icereg.h
10773
#define ICE_AQC_REPORT_DFLT_CFG BIT(3)
sys/dev/pci/if_icereg.h
1079
#define GL_MBX_PASID_PASID_MODE_M BIT(0)
sys/dev/pci/if_icereg.h
108
#define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1081
#define GL_MBX_PASID_PASID_MODE_VALID_M BIT(1)
sys/dev/pci/if_icereg.h
10859
#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
sys/dev/pci/if_icereg.h
10860
#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
sys/dev/pci/if_icereg.h
10861
#define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
sys/dev/pci/if_icereg.h
10862
#define ICE_AQC_PHY_EN_LINK BIT(3)
sys/dev/pci/if_icereg.h
10863
#define ICE_AQC_PHY_AN_MODE BIT(4)
sys/dev/pci/if_icereg.h
10864
#define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
sys/dev/pci/if_icereg.h
10865
#define ICE_AQC_PHY_EN_LESM BIT(6)
sys/dev/pci/if_icereg.h
10866
#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
sys/dev/pci/if_icereg.h
10869
#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
sys/dev/pci/if_icereg.h
10870
#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
sys/dev/pci/if_icereg.h
10871
#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
sys/dev/pci/if_icereg.h
10872
#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
sys/dev/pci/if_icereg.h
10874
#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
sys/dev/pci/if_icereg.h
10875
#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
sys/dev/pci/if_icereg.h
10876
#define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
sys/dev/pci/if_icereg.h
10877
#define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
sys/dev/pci/if_icereg.h
10878
#define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
sys/dev/pci/if_icereg.h
10879
#define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
sys/dev/pci/if_icereg.h
10880
#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
sys/dev/pci/if_icereg.h
10881
#define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
sys/dev/pci/if_icereg.h
10882
#define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
sys/dev/pci/if_icereg.h
10883
#define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
sys/dev/pci/if_icereg.h
10884
#define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
sys/dev/pci/if_icereg.h
10889
#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
sys/dev/pci/if_icereg.h
10890
#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
sys/dev/pci/if_icereg.h
10891
#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
sys/dev/pci/if_icereg.h
10892
#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
sys/dev/pci/if_icereg.h
10893
#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
sys/dev/pci/if_icereg.h
10894
#define ICE_AQC_PHY_FEC_DIS BIT(5)
sys/dev/pci/if_icereg.h
10895
#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
sys/dev/pci/if_icereg.h
10896
#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
sys/dev/pci/if_icereg.h
10899
#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
sys/dev/pci/if_icereg.h
10911
#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
sys/dev/pci/if_icereg.h
10912
#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
sys/dev/pci/if_icereg.h
10913
#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
sys/dev/pci/if_icereg.h
10914
#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
sys/dev/pci/if_icereg.h
10915
#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
sys/dev/pci/if_icereg.h
10916
#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
sys/dev/pci/if_icereg.h
10947
#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
sys/dev/pci/if_icereg.h
10948
#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
sys/dev/pci/if_icereg.h
10949
#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
sys/dev/pci/if_icereg.h
10950
#define ICE_AQ_PHY_ENA_LINK BIT(3)
sys/dev/pci/if_icereg.h
10951
#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
sys/dev/pci/if_icereg.h
10952
#define ICE_AQ_PHY_ENA_LESM BIT(6)
sys/dev/pci/if_icereg.h
10953
#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
sys/dev/pci/if_icereg.h
10967
#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
sys/dev/pci/if_icereg.h
1097
#define PF_FW_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
10974
#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
sys/dev/pci/if_icereg.h
10976
#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
sys/dev/pci/if_icereg.h
10987
#define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
sys/dev/pci/if_icereg.h
10988
#define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
sys/dev/pci/if_icereg.h
1099
#define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1101
#define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
11017
#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
sys/dev/pci/if_icereg.h
11018
#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
sys/dev/pci/if_icereg.h
11019
#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
sys/dev/pci/if_icereg.h
11020
#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
sys/dev/pci/if_icereg.h
11021
#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
sys/dev/pci/if_icereg.h
11022
#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
sys/dev/pci/if_icereg.h
11023
#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
sys/dev/pci/if_icereg.h
11025
#define ICE_AQ_LINK_CFG_ERR BIT(0)
sys/dev/pci/if_icereg.h
11026
#define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)
sys/dev/pci/if_icereg.h
11027
#define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)
sys/dev/pci/if_icereg.h
11028
#define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)
sys/dev/pci/if_icereg.h
11029
#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
sys/dev/pci/if_icereg.h
1103
#define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
11030
#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
sys/dev/pci/if_icereg.h
11031
#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
sys/dev/pci/if_icereg.h
11033
#define ICE_AQ_LINK_UP BIT(0) /* Link Status */
sys/dev/pci/if_icereg.h
11034
#define ICE_AQ_LINK_FAULT BIT(1)
sys/dev/pci/if_icereg.h
11035
#define ICE_AQ_LINK_FAULT_TX BIT(2)
sys/dev/pci/if_icereg.h
11036
#define ICE_AQ_LINK_FAULT_RX BIT(3)
sys/dev/pci/if_icereg.h
11037
#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
sys/dev/pci/if_icereg.h
11038
#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
sys/dev/pci/if_icereg.h
11039
#define ICE_AQ_MEDIA_AVAILABLE BIT(6)
sys/dev/pci/if_icereg.h
11040
#define ICE_AQ_SIGNAL_DETECT BIT(7)
sys/dev/pci/if_icereg.h
11042
#define ICE_AQ_AN_COMPLETED BIT(0)
sys/dev/pci/if_icereg.h
11043
#define ICE_AQ_LP_AN_ABILITY BIT(1)
sys/dev/pci/if_icereg.h
11044
#define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
sys/dev/pci/if_icereg.h
11045
#define ICE_AQ_FEC_EN BIT(3)
sys/dev/pci/if_icereg.h
11046
#define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
sys/dev/pci/if_icereg.h
11047
#define ICE_AQ_LINK_PAUSE_TX BIT(5)
sys/dev/pci/if_icereg.h
11048
#define ICE_AQ_LINK_PAUSE_RX BIT(6)
sys/dev/pci/if_icereg.h
11049
#define ICE_AQ_QUALIFIED_MODULE BIT(7)
sys/dev/pci/if_icereg.h
11051
#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
sys/dev/pci/if_icereg.h
11052
#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
sys/dev/pci/if_icereg.h
11060
#define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
sys/dev/pci/if_icereg.h
11061
#define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
sys/dev/pci/if_icereg.h
11062
#define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
sys/dev/pci/if_icereg.h
11067
#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
sys/dev/pci/if_icereg.h
11068
#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
sys/dev/pci/if_icereg.h
11069
#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
sys/dev/pci/if_icereg.h
11074
#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
sys/dev/pci/if_icereg.h
11088
#define ICE_AQ_LINK_SPEED_10MB BIT(0)
sys/dev/pci/if_icereg.h
11089
#define ICE_AQ_LINK_SPEED_100MB BIT(1)
sys/dev/pci/if_icereg.h
11090
#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
sys/dev/pci/if_icereg.h
11091
#define ICE_AQ_LINK_SPEED_2500MB BIT(3)
sys/dev/pci/if_icereg.h
11092
#define ICE_AQ_LINK_SPEED_5GB BIT(4)
sys/dev/pci/if_icereg.h
11093
#define ICE_AQ_LINK_SPEED_10GB BIT(5)
sys/dev/pci/if_icereg.h
11094
#define ICE_AQ_LINK_SPEED_20GB BIT(6)
sys/dev/pci/if_icereg.h
11095
#define ICE_AQ_LINK_SPEED_25GB BIT(7)
sys/dev/pci/if_icereg.h
11096
#define ICE_AQ_LINK_SPEED_40GB BIT(8)
sys/dev/pci/if_icereg.h
11097
#define ICE_AQ_LINK_SPEED_50GB BIT(9)
sys/dev/pci/if_icereg.h
11098
#define ICE_AQ_LINK_SPEED_100GB BIT(10)
sys/dev/pci/if_icereg.h
11099
#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
sys/dev/pci/if_icereg.h
11110
#define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
sys/dev/pci/if_icereg.h
11111
#define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
sys/dev/pci/if_icereg.h
11112
#define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
sys/dev/pci/if_icereg.h
11113
#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
sys/dev/pci/if_icereg.h
11114
#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
sys/dev/pci/if_icereg.h
11115
#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
sys/dev/pci/if_icereg.h
11116
#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
sys/dev/pci/if_icereg.h
11117
#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
sys/dev/pci/if_icereg.h
11118
#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
sys/dev/pci/if_icereg.h
11119
#define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
sys/dev/pci/if_icereg.h
11120
#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
sys/dev/pci/if_icereg.h
11121
#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)
sys/dev/pci/if_icereg.h
11129
#define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0)
sys/dev/pci/if_icereg.h
11132
#define ICE_AQ_PHY_LB_EN BIT(0)
sys/dev/pci/if_icereg.h
11133
#define ICE_AQ_PHY_LB_TYPE_M BIT(1)
sys/dev/pci/if_icereg.h
11136
#define ICE_AQ_PHY_LB_LEVEL_M BIT(2)
sys/dev/pci/if_icereg.h
11145
#define ICE_AQ_MAC_LB_EN BIT(0)
sys/dev/pci/if_icereg.h
11146
#define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
sys/dev/pci/if_icereg.h
11195
#define ICE_AQ_DNL_FLAGS_ERROR BIT(2)
sys/dev/pci/if_icereg.h
11196
#define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3)
sys/dev/pci/if_icereg.h
11197
#define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4)
sys/dev/pci/if_icereg.h
11198
#define ICE_AQ_DNL_FLAGS_ZERO BIT(5)
sys/dev/pci/if_icereg.h
11199
#define ICE_AQ_DNL_FLAGS_CARRY BIT(6)
sys/dev/pci/if_icereg.h
11200
#define ICE_AQ_DNL_FLAGS_JUMP BIT(7)
sys/dev/pci/if_icereg.h
1122
#define PF_FW_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1124
#define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1126
#define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1128
#define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
11339
#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
sys/dev/pci/if_icereg.h
11370
#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
sys/dev/pci/if_icereg.h
11371
#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
sys/dev/pci/if_icereg.h
11399
#define ICE_AQC_I2C_ADDR_TYPE_M BIT(4)
sys/dev/pci/if_icereg.h
11404
#define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
sys/dev/pci/if_icereg.h
11423
#define ICE_AQC_MDIO_CLAUSE_22 BIT(5)
sys/dev/pci/if_icereg.h
11424
#define ICE_AQC_MDIO_CLAUSE_45 BIT(6)
sys/dev/pci/if_icereg.h
11440
#define ICE_AQC_GPIO_ON BIT(0)
sys/dev/pci/if_icereg.h
1147
#define PF_MBX_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
11474
#define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
sys/dev/pci/if_icereg.h
11476
#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
sys/dev/pci/if_icereg.h
11485
#define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0)
sys/dev/pci/if_icereg.h
1149
#define PF_MBX_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
11494
#define ICE_AQC_PORT_OPT_FORCED BIT(6)
sys/dev/pci/if_icereg.h
11495
#define ICE_AQC_PORT_OPT_VALID BIT(7)
sys/dev/pci/if_icereg.h
11499
#define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7)
sys/dev/pci/if_icereg.h
1151
#define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1153
#define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
11532
#define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0)
sys/dev/pci/if_icereg.h
11551
#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
sys/dev/pci/if_icereg.h
11555
#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
sys/dev/pci/if_icereg.h
11563
#define ICE_AQC_SFF_IS_WRITE BIT(15)
sys/dev/pci/if_icereg.h
11585
#define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
sys/dev/pci/if_icereg.h
11586
#define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
sys/dev/pci/if_icereg.h
11615
#define ICE_AQC_NVM_LAST_CMD BIT(0)
sys/dev/pci/if_icereg.h
11616
#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
sys/dev/pci/if_icereg.h
11620
#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
sys/dev/pci/if_icereg.h
11623
#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
sys/dev/pci/if_icereg.h
11624
#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
sys/dev/pci/if_icereg.h
11625
#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
sys/dev/pci/if_icereg.h
11626
#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
sys/dev/pci/if_icereg.h
11627
#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
sys/dev/pci/if_icereg.h
11629
#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
sys/dev/pci/if_icereg.h
11634
#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
sys/dev/pci/if_icereg.h
11640
#define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */
sys/dev/pci/if_icereg.h
11657
#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
sys/dev/pci/if_icereg.h
11677
#define ICE_AQC_NVM_CMPO_ENABLE BIT(8)
sys/dev/pci/if_icereg.h
11688
#define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0)
sys/dev/pci/if_icereg.h
11689
#define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1)
sys/dev/pci/if_icereg.h
11699
#define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4)
sys/dev/pci/if_icereg.h
1170
#define PF_MBX_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
11706
#define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
sys/dev/pci/if_icereg.h
11707
#define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
sys/dev/pci/if_icereg.h
11708
#define ICE_AQC_ANVM_NEW_CFG BIT(2)
sys/dev/pci/if_icereg.h
1172
#define PF_MBX_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
11726
#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
sys/dev/pci/if_icereg.h
11727
#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
sys/dev/pci/if_icereg.h
1174
#define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1176
#define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
11766
#define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0)
sys/dev/pci/if_icereg.h
11767
#define ICE_AQC_RESP_RESET_NEEDED BIT(1)
sys/dev/pci/if_icereg.h
11860
#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
sys/dev/pci/if_icereg.h
11863
#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
sys/dev/pci/if_icereg.h
11870
#define ICE_AQ_LLDP_AGENT_START BIT(0)
sys/dev/pci/if_icereg.h
11871
#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
sys/dev/pci/if_icereg.h
11910
#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
sys/dev/pci/if_icereg.h
11912
#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
sys/dev/pci/if_icereg.h
11924
#define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
sys/dev/pci/if_icereg.h
11937
#define ICE_AQC_START_STOP_AGENT_M BIT(0)
sys/dev/pci/if_icereg.h
1195
#define PF_SB_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
11957
#define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
sys/dev/pci/if_icereg.h
1197
#define PF_SB_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1199
#define PF_SB_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
12004
#define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
sys/dev/pci/if_icereg.h
1201
#define PF_SB_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
12068
#define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
sys/dev/pci/if_icereg.h
12071
#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
sys/dev/pci/if_icereg.h
12072
#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
sys/dev/pci/if_icereg.h
12120
#define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
sys/dev/pci/if_icereg.h
12121
#define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
sys/dev/pci/if_icereg.h
1218
#define PF_SB_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1220
#define PF_SB_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1222
#define PF_SB_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1224
#define PF_SB_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
12258
#define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
sys/dev/pci/if_icereg.h
12337
#define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
sys/dev/pci/if_icereg.h
12338
#define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
sys/dev/pci/if_icereg.h
12339
#define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
sys/dev/pci/if_icereg.h
12428
#define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)
sys/dev/pci/if_icereg.h
12429
#define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)
sys/dev/pci/if_icereg.h
12430
#define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2)
sys/dev/pci/if_icereg.h
12431
#define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)
sys/dev/pci/if_icereg.h
12432
#define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
sys/dev/pci/if_icereg.h
12433
#define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)
sys/dev/pci/if_icereg.h
12434
#define ICE_AQC_FW_LOG_PERSISTENT BIT(0)
sys/dev/pci/if_icereg.h
12436
#define ICE_AQC_FW_LOG_MORE_DATA BIT(1)
sys/dev/pci/if_icereg.h
1246
#define PF0_FW_HLP_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1248
#define PF0_FW_HLP_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1250
#define PF0_FW_HLP_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1252
#define PF0_FW_HLP_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
12626
#define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
sys/dev/pci/if_icereg.h
12627
#define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
sys/dev/pci/if_icereg.h
12628
#define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
sys/dev/pci/if_icereg.h
12629
#define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
sys/dev/pci/if_icereg.h
12630
#define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
sys/dev/pci/if_icereg.h
12631
#define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
sys/dev/pci/if_icereg.h
12632
#define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
sys/dev/pci/if_icereg.h
12633
#define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
sys/dev/pci/if_icereg.h
12634
#define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
sys/dev/pci/if_icereg.h
12635
#define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
sys/dev/pci/if_icereg.h
12636
#define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
sys/dev/pci/if_icereg.h
127
#define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1271
#define PF0_FW_HLP_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1273
#define PF0_FW_HLP_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1275
#define PF0_FW_HLP_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1277
#define PF0_FW_HLP_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
129
#define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
12901
#define ICE_FWLOG_OPTION_ARQ_ENA BIT(0)
sys/dev/pci/if_icereg.h
12902
#define ICE_FWLOG_OPTION_UART_ENA BIT(1)
sys/dev/pci/if_icereg.h
12906
#define ICE_FWLOG_OPTION_REGISTER_ON_INIT BIT(2)
sys/dev/pci/if_icereg.h
12910
#define ICE_FWLOG_OPTION_IS_REGISTERED BIT(3)
sys/dev/pci/if_icereg.h
12957
#define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1)
sys/dev/pci/if_icereg.h
1296
#define PF0_FW_PSM_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1298
#define PF0_FW_PSM_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1300
#define PF0_FW_PSM_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1302
#define PF0_FW_PSM_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
131
#define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
13188
#define ICE_RXD_QW1_STATUS_M ((BIT(ICE_RX_DESC_STATUS_LAST) - 1) << \
sys/dev/pci/if_icereg.h
1321
#define PF0_FW_PSM_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1323
#define PF0_FW_PSM_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1325
#define PF0_FW_PSM_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1327
#define PF0_FW_PSM_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
133
#define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1346
#define PF0_MBX_CPM_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1348
#define PF0_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1350
#define PF0_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1352
#define PF0_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1369
#define PF0_MBX_CPM_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1371
#define PF0_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1373
#define PF0_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1375
#define PF0_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1394
#define PF0_MBX_HLP_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1396
#define PF0_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1398
#define PF0_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1400
#define PF0_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1417
#define PF0_MBX_HLP_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1419
#define PF0_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1421
#define PF0_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1423
#define PF0_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1442
#define PF0_MBX_PSM_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1444
#define PF0_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1446
#define PF0_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1448
#define PF0_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1465
#define PF0_MBX_PSM_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1467
#define PF0_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1469
#define PF0_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1471
#define PF0_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1490
#define PF0_SB_CPM_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1492
#define PF0_SB_CPM_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1494
#define PF0_SB_CPM_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1496
#define PF0_SB_CPM_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1513
#define PF0_SB_CPM_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1515
#define PF0_SB_CPM_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1517
#define PF0_SB_CPM_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1519
#define PF0_SB_CPM_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
152
#define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
154
#define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1541
#define PF0_SB_HLP_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1543
#define PF0_SB_HLP_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1545
#define PF0_SB_HLP_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1547
#define PF0_SB_HLP_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
156
#define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1564
#define PF0_SB_HLP_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1566
#define PF0_SB_HLP_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1568
#define PF0_SB_HLP_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1570
#define PF0_SB_HLP_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
158
#define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1582
#define SB_REM_DEV_DEST_DEST_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
1602
#define VF_MBX_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1604
#define VF_MBX_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1606
#define VF_MBX_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1608
#define VF_MBX_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1630
#define VF_MBX_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1632
#define VF_MBX_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1634
#define VF_MBX_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1636
#define VF_MBX_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1660
#define VF_MBX_CPM_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1662
#define VF_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1664
#define VF_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1666
#define VF_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1688
#define VF_MBX_CPM_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1690
#define VF_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1692
#define VF_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1694
#define VF_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1718
#define VF_MBX_HLP_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1720
#define VF_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1722
#define VF_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1724
#define VF_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1746
#define VF_MBX_HLP_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1748
#define VF_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1750
#define VF_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1752
#define VF_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
177
#define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1776
#define VF_MBX_PSM_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1778
#define VF_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1780
#define VF_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1782
#define VF_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
179
#define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1804
#define VF_MBX_PSM_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1806
#define VF_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1808
#define VF_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
181
#define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1810
#define VF_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
183
#define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1834
#define VF_SB_CPM_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1836
#define VF_SB_CPM_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1838
#define VF_SB_CPM_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1840
#define VF_SB_CPM_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1862
#define VF_SB_CPM_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
1864
#define VF_SB_CPM_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
1866
#define VF_SB_CPM_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
1868
#define VF_SB_CPM_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
1879
#define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
sys/dev/pci/if_icereg.h
1883
#define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_M BIT(0)
sys/dev/pci/if_icereg.h
1887
#define VP_MBX_PF_VF_CTRL_QUEUE_EN_M BIT(0)
sys/dev/pci/if_icereg.h
1891
#define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
sys/dev/pci/if_icereg.h
1895
#define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
sys/dev/pci/if_icereg.h
1898
#define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_M BIT(0)
sys/dev/pci/if_icereg.h
1915
#define GLDCB_PRS_RETSTCC_ETSTC_M BIT(31)
sys/dev/pci/if_icereg.h
1926
#define GLDCB_PRS_RSPMC_RPM_DIS_M BIT(31)
sys/dev/pci/if_icereg.h
1932
#define GLDCB_RETSTCC_ETSTC_M BIT(31)
sys/dev/pci/if_icereg.h
1945
#define GLDCB_SWT_RETSTCC_ETSTC_M BIT(31)
sys/dev/pci/if_icereg.h
1951
#define GLDCB_TCB_MNG_SP_MNG_SP_M BIT(0)
sys/dev/pci/if_icereg.h
1957
#define GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
sys/dev/pci/if_icereg.h
1966
#define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_M BIT(0)
sys/dev/pci/if_icereg.h
1969
#define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_M BIT(0)
sys/dev/pci/if_icereg.h
1971
#define GLDCB_TCUPM_WB_DIS_TC_DISABLE_M BIT(1)
sys/dev/pci/if_icereg.h
2010
#define GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
sys/dev/pci/if_icereg.h
202
#define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
2029
#define GLTCB_WB_RL_EN_M BIT(16)
sys/dev/pci/if_icereg.h
2034
#define GLTPB_WB_RL_EN_M BIT(16)
sys/dev/pci/if_icereg.h
204
#define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
2053
#define PRTDCB_GENC_FCOEUP_VALID_M BIT(9)
sys/dev/pci/if_icereg.h
206
#define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
2061
#define PRTDCB_PRS_RETSC_ETS_MODE_M BIT(0)
sys/dev/pci/if_icereg.h
2063
#define PRTDCB_PRS_RETSC_NON_ETS_MODE_M BIT(1)
sys/dev/pci/if_icereg.h
2070
#define PRTDCB_PRS_RPRRC_BWSHARE_DIS_M BIT(31)
sys/dev/pci/if_icereg.h
2073
#define PRTDCB_RETSC_ETS_MODE_M BIT(0)
sys/dev/pci/if_icereg.h
2075
#define PRTDCB_RETSC_NON_ETS_MODE_M BIT(1)
sys/dev/pci/if_icereg.h
208
#define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
2082
#define PRTDCB_RPRRC_BWSHARE_DIS_M BIT(31)
sys/dev/pci/if_icereg.h
2108
#define PRTDCB_SWT_RETSC_ETS_MODE_M BIT(0)
sys/dev/pci/if_icereg.h
2110
#define PRTDCB_SWT_RETSC_NON_ETS_MODE_M BIT(1)
sys/dev/pci/if_icereg.h
2171
#define PRTDCB_TDPUC_MAL_LENGTH_M BIT(16)
sys/dev/pci/if_icereg.h
2173
#define PRTDCB_TDPUC_MAL_CMD_M BIT(17)
sys/dev/pci/if_icereg.h
2175
#define PRTDCB_TDPUC_TTL_DROP_M BIT(18)
sys/dev/pci/if_icereg.h
2177
#define PRTDCB_TDPUC_UR_DROP_M BIT(19)
sys/dev/pci/if_icereg.h
2179
#define PRTDCB_TDPUC_DUMMY_M BIT(20)
sys/dev/pci/if_icereg.h
2181
#define PRTDCB_TDPUC_BIG_PKT_SIZE_M BIT(21)
sys/dev/pci/if_icereg.h
2183
#define PRTDCB_TDPUC_L2_ACCEPT_FAIL_M BIT(22)
sys/dev/pci/if_icereg.h
2185
#define PRTDCB_TDPUC_DSCP_CHECK_FAIL_M BIT(23)
sys/dev/pci/if_icereg.h
2187
#define PRTDCB_TDPUC_RCU_ANTISPOOF_M BIT(24)
sys/dev/pci/if_icereg.h
2189
#define PRTDCB_TDPUC_NIC_DSI_M BIT(25)
sys/dev/pci/if_icereg.h
2191
#define PRTDCB_TDPUC_NIC_IPSEC_M BIT(26)
sys/dev/pci/if_icereg.h
2193
#define PRTDCB_TDPUC_CLEAR_DROP_M BIT(31)
sys/dev/pci/if_icereg.h
2196
#define PRTDCB_TFCS_TXOFF_M BIT(0)
sys/dev/pci/if_icereg.h
2198
#define PRTDCB_TFCS_TXOFF0_M BIT(8)
sys/dev/pci/if_icereg.h
2200
#define PRTDCB_TFCS_TXOFF1_M BIT(9)
sys/dev/pci/if_icereg.h
2202
#define PRTDCB_TFCS_TXOFF2_M BIT(10)
sys/dev/pci/if_icereg.h
2204
#define PRTDCB_TFCS_TXOFF3_M BIT(11)
sys/dev/pci/if_icereg.h
2206
#define PRTDCB_TFCS_TXOFF4_M BIT(12)
sys/dev/pci/if_icereg.h
2208
#define PRTDCB_TFCS_TXOFF5_M BIT(13)
sys/dev/pci/if_icereg.h
2210
#define PRTDCB_TFCS_TXOFF6_M BIT(14)
sys/dev/pci/if_icereg.h
2212
#define PRTDCB_TFCS_TXOFF7_M BIT(15)
sys/dev/pci/if_icereg.h
225
#define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
2250
#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
227
#define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
229
#define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
231
#define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
2360
#define TPB_GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
sys/dev/pci/if_icereg.h
2363
#define TPB_GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
sys/dev/pci/if_icereg.h
2431
#define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2467
#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
sys/dev/pci/if_icereg.h
2473
#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
sys/dev/pci/if_icereg.h
2479
#define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
250
#define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
252
#define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
2537
#define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
254
#define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
2551
#define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
sys/dev/pci/if_icereg.h
2553
#define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
256
#define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
2565
#define GL_ACLEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
sys/dev/pci/if_icereg.h
2571
#define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2585
#define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2595
#define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2605
#define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2629
#define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2661
#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
sys/dev/pci/if_icereg.h
2667
#define GL_PREEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
sys/dev/pci/if_icereg.h
2673
#define GL_PREEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
273
#define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
2731
#define GL_PREEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2745
#define GL_PREEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
sys/dev/pci/if_icereg.h
2747
#define GL_PREEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
275
#define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
2759
#define GL_PREEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
sys/dev/pci/if_icereg.h
2765
#define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
277
#define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
2779
#define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2789
#define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
279
#define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
2799
#define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2823
#define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2863
#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
sys/dev/pci/if_icereg.h
2869
#define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
sys/dev/pci/if_icereg.h
2875
#define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2913
#define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2927
#define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
sys/dev/pci/if_icereg.h
2929
#define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2941
#define GL_PSTEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
sys/dev/pci/if_icereg.h
2947
#define GL_PSTEXT_PRFLM_CTRL_RD_REQ_M BIT(30)
sys/dev/pci/if_icereg.h
2949
#define GL_PSTEXT_PRFLM_CTRL_WR_REQ_M BIT(31)
sys/dev/pci/if_icereg.h
2973
#define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
298
#define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
2987
#define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
2997
#define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
300
#define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
3007
#define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
sys/dev/pci/if_icereg.h
302
#define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
304
#define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
3123
#define QRXFLXP_CNTXT_TS_M BIT(11)
sys/dev/pci/if_icereg.h
3128
#define GL_FWSTS_FWROWD_M BIT(8)
sys/dev/pci/if_icereg.h
3130
#define GL_FWSTS_FWRI_M BIT(9)
sys/dev/pci/if_icereg.h
3135
#define GL_TCVMLR_DRAIN_CNTR_CTL_OP_M BIT(0)
sys/dev/pci/if_icereg.h
3142
#define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_M BIT(0)
sys/dev/pci/if_icereg.h
3162
#define GL_TCVMLR_ERR_STAT_ERROR_M BIT(0)
sys/dev/pci/if_icereg.h
3164
#define GL_TCVMLR_ERR_STAT_FW_REQ_M BIT(1)
sys/dev/pci/if_icereg.h
3175
#define GL_TCVMLR_QCFG_OP_M BIT(14)
sys/dev/pci/if_icereg.h
3194
#define GL_TCVMLR_QCTL_OP_M BIT(14)
sys/dev/pci/if_icereg.h
3201
#define GL_TCVMLR_REQ_STAT_OP_M BIT(17)
sys/dev/pci/if_icereg.h
321
#define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
323
#define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
3246
#define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
sys/dev/pci/if_icereg.h
325
#define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
3261
#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
sys/dev/pci/if_icereg.h
327
#define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
3278
#define GLGEN_ANA_FLAG_MAP_FLAG_EN_M BIT(0)
sys/dev/pci/if_icereg.h
3290
#define GLGEN_ANA_LAST_PROT_ID_EN_M BIT(0)
sys/dev/pci/if_icereg.h
3331
#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
sys/dev/pci/if_icereg.h
3349
#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
sys/dev/pci/if_icereg.h
3364
#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
sys/dev/pci/if_icereg.h
3377
#define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_M BIT(0)
sys/dev/pci/if_icereg.h
3384
#define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_M BIT(0)
sys/dev/pci/if_icereg.h
3431
#define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
sys/dev/pci/if_icereg.h
3434
#define GLGEN_ASSERT_HLP_CORE_ON_RST_M BIT(0)
sys/dev/pci/if_icereg.h
3436
#define GLGEN_ASSERT_HLP_FULL_ON_RST_M BIT(1)
sys/dev/pci/if_icereg.h
346
#define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
3476
#define GLGEN_GPIO_CTL_IN_VALUE_M BIT(0)
sys/dev/pci/if_icereg.h
3478
#define GLGEN_GPIO_CTL_IN_TRANSIT_M BIT(1)
sys/dev/pci/if_icereg.h
348
#define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
3480
#define GLGEN_GPIO_CTL_OUT_VALUE_M BIT(2)
sys/dev/pci/if_icereg.h
3482
#define GLGEN_GPIO_CTL_NO_P_UP_M BIT(3)
sys/dev/pci/if_icereg.h
3484
#define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4)
sys/dev/pci/if_icereg.h
3486
#define GLGEN_GPIO_CTL_TRI_CTL_M BIT(5)
sys/dev/pci/if_icereg.h
3495
#define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_M BIT(31)
sys/dev/pci/if_icereg.h
350
#define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
3510
#define GLGEN_RSTAT_RTRIG_FLR_M BIT(16)
sys/dev/pci/if_icereg.h
3512
#define GLGEN_RSTAT_RTRIG_ECC_M BIT(17)
sys/dev/pci/if_icereg.h
3514
#define GLGEN_RSTAT_RTRIG_FW_AUX_M BIT(18)
sys/dev/pci/if_icereg.h
3519
#define GLGEN_RSTCTL_ECC_RST_ENA_M BIT(8)
sys/dev/pci/if_icereg.h
352
#define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
3521
#define GLGEN_RSTCTL_ECC_RT_EN_M BIT(30)
sys/dev/pci/if_icereg.h
3523
#define GLGEN_RSTCTL_FLR_RT_EN_M BIT(31)
sys/dev/pci/if_icereg.h
3526
#define GLGEN_RTRIG_CORER_M BIT(0)
sys/dev/pci/if_icereg.h
3528
#define GLGEN_RTRIG_GLOBR_M BIT(1)
sys/dev/pci/if_icereg.h
3530
#define GLGEN_RTRIG_EMPFWR_M BIT(2)
sys/dev/pci/if_icereg.h
3540
#define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_M BIT(0)
sys/dev/pci/if_icereg.h
3551
#define PFGEN_CTRL_PFSWR_M BIT(0)
sys/dev/pci/if_icereg.h
3554
#define PFGEN_DRUN_DRVUNLD_M BIT(0)
sys/dev/pci/if_icereg.h
3557
#define PFGEN_PFRSTAT_PFRD_M BIT(0)
sys/dev/pci/if_icereg.h
3563
#define PFGEN_STATE_PFPEEN_M BIT(0)
sys/dev/pci/if_icereg.h
3565
#define PFGEN_STATE_RSVD_M BIT(1)
sys/dev/pci/if_icereg.h
3567
#define PFGEN_STATE_PFLINKEN_M BIT(2)
sys/dev/pci/if_icereg.h
3569
#define PFGEN_STATE_PFSCEN_M BIT(3)
sys/dev/pci/if_icereg.h
3575
#define PRTGEN_CNF_PORT_DIS_M BIT(0)
sys/dev/pci/if_icereg.h
3577
#define PRTGEN_CNF_ALLOW_PORT_DIS_M BIT(1)
sys/dev/pci/if_icereg.h
3579
#define PRTGEN_CNF_EMP_PORT_DIS_M BIT(2)
sys/dev/pci/if_icereg.h
3582
#define PRTGEN_CNF2_ACTIVATE_PORT_LINK_M BIT(0)
sys/dev/pci/if_icereg.h
3585
#define PRTGEN_CNF3_PORT_STAGERING_EN_M BIT(0)
sys/dev/pci/if_icereg.h
3588
#define PRTGEN_STATUS_PORT_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
3590
#define PRTGEN_STATUS_PORT_ACTIVE_M BIT(1)
sys/dev/pci/if_icereg.h
3598
#define VPGEN_VFRSTAT_VFRD_M BIT(0)
sys/dev/pci/if_icereg.h
3602
#define VPGEN_VFRTRIG_VFSWR_M BIT(0)
sys/dev/pci/if_icereg.h
3606
#define VSIGEN_RSTAT_VMRD_M BIT(0)
sys/dev/pci/if_icereg.h
3610
#define VSIGEN_RTRIG_VMSWR_M BIT(0)
sys/dev/pci/if_icereg.h
3671
#define GLHMC_FWPDINV_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
3678
#define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
3689
#define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0)
sys/dev/pci/if_icereg.h
369
#define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
3691
#define GLHMC_FWSDDATALOW_PMSDTYPE_M BIT(1)
sys/dev/pci/if_icereg.h
3698
#define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
sys/dev/pci/if_icereg.h
3700
#define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
sys/dev/pci/if_icereg.h
371
#define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
373
#define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
375
#define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
394
#define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
396
#define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
398
#define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
400
#define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
4015
#define GLHMC_VFPDINV_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
4023
#define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
4165
#define GLHMC_VFSDDATALOW_PMSDVALID_M BIT(0)
sys/dev/pci/if_icereg.h
4167
#define GLHMC_VFSDDATALOW_PMSDTYPE_M BIT(1)
sys/dev/pci/if_icereg.h
417
#define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
4175
#define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
sys/dev/pci/if_icereg.h
4177
#define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
sys/dev/pci/if_icereg.h
419
#define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
421
#define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
423
#define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
4253
#define PFHMC_ERRORINFO_PMF_ISVF_M BIT(7)
sys/dev/pci/if_icereg.h
4259
#define PFHMC_ERRORINFO_ERROR_DETECTED_M BIT(31)
sys/dev/pci/if_icereg.h
4264
#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M BIT(7)
sys/dev/pci/if_icereg.h
4270
#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M BIT(31)
sys/dev/pci/if_icereg.h
4275
#define PFHMC_PDINV_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
4282
#define PFHMC_PDINV_FPMAT_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
4289
#define PFHMC_SDCMD_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
4291
#define PFHMC_SDCMD_PMSDWR_M BIT(31)
sys/dev/pci/if_icereg.h
4296
#define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_M BIT(15)
sys/dev/pci/if_icereg.h
4298
#define PFHMC_SDCMD_FPMAT_PMSDWR_M BIT(31)
sys/dev/pci/if_icereg.h
430
#define PF0INT_DYN_CTL_INTENA_M BIT(0)
sys/dev/pci/if_icereg.h
4307
#define PFHMC_SDDATALOW_PMSDVALID_M BIT(0)
sys/dev/pci/if_icereg.h
4309
#define PFHMC_SDDATALOW_PMSDTYPE_M BIT(1)
sys/dev/pci/if_icereg.h
4316
#define PFHMC_SDDATALOW_FPMAT_PMSDVALID_M BIT(0)
sys/dev/pci/if_icereg.h
4318
#define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
sys/dev/pci/if_icereg.h
432
#define PF0INT_DYN_CTL_CLEARPBA_M BIT(1)
sys/dev/pci/if_icereg.h
4330
#define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_M BIT(0)
sys/dev/pci/if_icereg.h
4332
#define GL_MDCK_TDAT_TCLAN_UR_M BIT(1)
sys/dev/pci/if_icereg.h
4334
#define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_M BIT(2)
sys/dev/pci/if_icereg.h
4336
#define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_M BIT(3)
sys/dev/pci/if_icereg.h
4338
#define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_M BIT(4)
sys/dev/pci/if_icereg.h
434
#define PF0INT_DYN_CTL_SWINT_TRIG_M BIT(2)
sys/dev/pci/if_icereg.h
4340
#define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_M BIT(5)
sys/dev/pci/if_icereg.h
4342
#define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_M BIT(6)
sys/dev/pci/if_icereg.h
4344
#define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_M BIT(7)
sys/dev/pci/if_icereg.h
4346
#define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_M BIT(8)
sys/dev/pci/if_icereg.h
4348
#define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_M BIT(9)
sys/dev/pci/if_icereg.h
4350
#define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_M BIT(10)
sys/dev/pci/if_icereg.h
4352
#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)
sys/dev/pci/if_icereg.h
4354
#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)
sys/dev/pci/if_icereg.h
4356
#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)
sys/dev/pci/if_icereg.h
4358
#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)
sys/dev/pci/if_icereg.h
4360
#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_M BIT(15)
sys/dev/pci/if_icereg.h
4362
#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_M BIT(16)
sys/dev/pci/if_icereg.h
4364
#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_M BIT(17)
sys/dev/pci/if_icereg.h
4366
#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_M BIT(18)
sys/dev/pci/if_icereg.h
4368
#define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_M BIT(19)
sys/dev/pci/if_icereg.h
4370
#define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_M BIT(20)
sys/dev/pci/if_icereg.h
440
#define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
sys/dev/pci/if_icereg.h
444
#define PF0INT_DYN_CTL_WB_ON_ITR_M BIT(30)
sys/dev/pci/if_icereg.h
4454
#define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_M BIT(0)
sys/dev/pci/if_icereg.h
4456
#define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_M BIT(1)
sys/dev/pci/if_icereg.h
4458
#define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_M BIT(2)
sys/dev/pci/if_icereg.h
446
#define PF0INT_DYN_CTL_INTENA_MSK_M BIT(31)
sys/dev/pci/if_icereg.h
4460
#define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_M BIT(3)
sys/dev/pci/if_icereg.h
4462
#define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_M BIT(4)
sys/dev/pci/if_icereg.h
4464
#define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_M BIT(5)
sys/dev/pci/if_icereg.h
4466
#define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_M BIT(6)
sys/dev/pci/if_icereg.h
4468
#define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_M BIT(7)
sys/dev/pci/if_icereg.h
4478
#define GL_UFUSE_SOC_PE_DISABLE_M BIT(4)
sys/dev/pci/if_icereg.h
4480
#define GL_UFUSE_SOC_SWITCH_MODE_M BIT(5)
sys/dev/pci/if_icereg.h
4482
#define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_M BIT(6)
sys/dev/pci/if_icereg.h
4484
#define GL_UFUSE_SOC_SERIAL_50G_M BIT(7)
sys/dev/pci/if_icereg.h
4486
#define GL_UFUSE_SOC_NIC_ID_M BIT(8)
sys/dev/pci/if_icereg.h
4488
#define GL_UFUSE_SOC_BLOCK_BME_TO_FW_M BIT(9)
sys/dev/pci/if_icereg.h
4490
#define GL_UFUSE_SOC_SOC_TYPE_M BIT(10)
sys/dev/pci/if_icereg.h
4492
#define GL_UFUSE_SOC_BTS_MODE_M BIT(11)
sys/dev/pci/if_icereg.h
4497
#define EMPINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
4499
#define EMPINT_GPIO_ENA_GPIO1_ENA_M BIT(1)
sys/dev/pci/if_icereg.h
4501
#define EMPINT_GPIO_ENA_GPIO2_ENA_M BIT(2)
sys/dev/pci/if_icereg.h
4503
#define EMPINT_GPIO_ENA_GPIO3_ENA_M BIT(3)
sys/dev/pci/if_icereg.h
4505
#define EMPINT_GPIO_ENA_GPIO4_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
4507
#define EMPINT_GPIO_ENA_GPIO5_ENA_M BIT(5)
sys/dev/pci/if_icereg.h
4509
#define EMPINT_GPIO_ENA_GPIO6_ENA_M BIT(6)
sys/dev/pci/if_icereg.h
4520
#define GLINT_CEQCTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4522
#define GLINT_CEQCTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4525
#define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
sys/dev/pci/if_icereg.h
4539
#define GLINT_DYN_CTL_INTENA_M BIT(0)
sys/dev/pci/if_icereg.h
4541
#define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
sys/dev/pci/if_icereg.h
4543
#define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
sys/dev/pci/if_icereg.h
4549
#define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
sys/dev/pci/if_icereg.h
4553
#define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
sys/dev/pci/if_icereg.h
4555
#define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
sys/dev/pci/if_icereg.h
4562
#define GLINT_FW_TOOL_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4564
#define GLINT_FW_TOOL_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4574
#define GLINT_RATE_INTRL_ENA_M BIT(6)
sys/dev/pci/if_icereg.h
4589
#define GLINT_VECT2FUNC_IS_PF_M BIT(16)
sys/dev/pci/if_icereg.h
4596
#define PF0INT_FW_HLP_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4598
#define PF0INT_FW_HLP_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4605
#define PF0INT_FW_PSM_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4607
#define PF0INT_FW_PSM_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
461
#define PF0INT_OICR_CPM_PAGE_INTEVENT_M BIT(0)
sys/dev/pci/if_icereg.h
4614
#define PF0INT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4616
#define PF0INT_MBX_CPM_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4623
#define PF0INT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4625
#define PF0INT_MBX_HLP_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
463
#define PF0INT_OICR_CPM_PAGE_QUEUE_M BIT(1)
sys/dev/pci/if_icereg.h
4632
#define PF0INT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4634
#define PF0INT_MBX_PSM_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4637
#define PF0INT_OICR_CPM_INTEVENT_M BIT(0)
sys/dev/pci/if_icereg.h
4639
#define PF0INT_OICR_CPM_QUEUE_M BIT(1)
sys/dev/pci/if_icereg.h
4643
#define PF0INT_OICR_CPM_HH_COMP_M BIT(10)
sys/dev/pci/if_icereg.h
4645
#define PF0INT_OICR_CPM_TSYN_TX_M BIT(11)
sys/dev/pci/if_icereg.h
4647
#define PF0INT_OICR_CPM_TSYN_EVNT_M BIT(12)
sys/dev/pci/if_icereg.h
4649
#define PF0INT_OICR_CPM_TSYN_TGT_M BIT(13)
sys/dev/pci/if_icereg.h
4651
#define PF0INT_OICR_CPM_HLP_RDY_M BIT(14)
sys/dev/pci/if_icereg.h
4653
#define PF0INT_OICR_CPM_CPM_RDY_M BIT(15)
sys/dev/pci/if_icereg.h
4655
#define PF0INT_OICR_CPM_ECC_ERR_M BIT(16)
sys/dev/pci/if_icereg.h
4659
#define PF0INT_OICR_CPM_MAL_DETECT_M BIT(19)
sys/dev/pci/if_icereg.h
4661
#define PF0INT_OICR_CPM_GRST_M BIT(20)
sys/dev/pci/if_icereg.h
4663
#define PF0INT_OICR_CPM_PCI_EXCEPTION_M BIT(21)
sys/dev/pci/if_icereg.h
4665
#define PF0INT_OICR_CPM_GPIO_M BIT(22)
sys/dev/pci/if_icereg.h
4667
#define PF0INT_OICR_CPM_RSV3_M BIT(23)
sys/dev/pci/if_icereg.h
4669
#define PF0INT_OICR_CPM_STORM_DETECT_M BIT(24)
sys/dev/pci/if_icereg.h
467
#define PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10)
sys/dev/pci/if_icereg.h
4671
#define PF0INT_OICR_CPM_LINK_STAT_CHANGE_M BIT(25)
sys/dev/pci/if_icereg.h
4673
#define PF0INT_OICR_CPM_HMC_ERR_M BIT(26)
sys/dev/pci/if_icereg.h
4675
#define PF0INT_OICR_CPM_PE_PUSH_M BIT(27)
sys/dev/pci/if_icereg.h
4677
#define PF0INT_OICR_CPM_PE_CRITERR_M BIT(28)
sys/dev/pci/if_icereg.h
4679
#define PF0INT_OICR_CPM_VFLR_M BIT(29)
sys/dev/pci/if_icereg.h
4681
#define PF0INT_OICR_CPM_XLR_HW_DONE_M BIT(30)
sys/dev/pci/if_icereg.h
4683
#define PF0INT_OICR_CPM_SWINT_M BIT(31)
sys/dev/pci/if_icereg.h
469
#define PF0INT_OICR_CPM_PAGE_TSYN_TX_M BIT(11)
sys/dev/pci/if_icereg.h
4690
#define PF0INT_OICR_CTL_CPM_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4692
#define PF0INT_OICR_CTL_CPM_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4699
#define PF0INT_OICR_CTL_HLP_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4701
#define PF0INT_OICR_CTL_HLP_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4708
#define PF0INT_OICR_CTL_PSM_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
471
#define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_M BIT(12)
sys/dev/pci/if_icereg.h
4710
#define PF0INT_OICR_CTL_PSM_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4713
#define PF0INT_OICR_ENA_CPM_RSV0_M BIT(0)
sys/dev/pci/if_icereg.h
4718
#define PF0INT_OICR_ENA_HLP_RSV0_M BIT(0)
sys/dev/pci/if_icereg.h
4723
#define PF0INT_OICR_ENA_PSM_RSV0_M BIT(0)
sys/dev/pci/if_icereg.h
4728
#define PF0INT_OICR_HLP_INTEVENT_M BIT(0)
sys/dev/pci/if_icereg.h
473
#define PF0INT_OICR_CPM_PAGE_TSYN_TGT_M BIT(13)
sys/dev/pci/if_icereg.h
4730
#define PF0INT_OICR_HLP_QUEUE_M BIT(1)
sys/dev/pci/if_icereg.h
4734
#define PF0INT_OICR_HLP_HH_COMP_M BIT(10)
sys/dev/pci/if_icereg.h
4736
#define PF0INT_OICR_HLP_TSYN_TX_M BIT(11)
sys/dev/pci/if_icereg.h
4738
#define PF0INT_OICR_HLP_TSYN_EVNT_M BIT(12)
sys/dev/pci/if_icereg.h
4740
#define PF0INT_OICR_HLP_TSYN_TGT_M BIT(13)
sys/dev/pci/if_icereg.h
4742
#define PF0INT_OICR_HLP_HLP_RDY_M BIT(14)
sys/dev/pci/if_icereg.h
4744
#define PF0INT_OICR_HLP_CPM_RDY_M BIT(15)
sys/dev/pci/if_icereg.h
4746
#define PF0INT_OICR_HLP_ECC_ERR_M BIT(16)
sys/dev/pci/if_icereg.h
475
#define PF0INT_OICR_CPM_PAGE_HLP_RDY_M BIT(14)
sys/dev/pci/if_icereg.h
4750
#define PF0INT_OICR_HLP_MAL_DETECT_M BIT(19)
sys/dev/pci/if_icereg.h
4752
#define PF0INT_OICR_HLP_GRST_M BIT(20)
sys/dev/pci/if_icereg.h
4754
#define PF0INT_OICR_HLP_PCI_EXCEPTION_M BIT(21)
sys/dev/pci/if_icereg.h
4756
#define PF0INT_OICR_HLP_GPIO_M BIT(22)
sys/dev/pci/if_icereg.h
4758
#define PF0INT_OICR_HLP_RSV3_M BIT(23)
sys/dev/pci/if_icereg.h
4760
#define PF0INT_OICR_HLP_STORM_DETECT_M BIT(24)
sys/dev/pci/if_icereg.h
4762
#define PF0INT_OICR_HLP_LINK_STAT_CHANGE_M BIT(25)
sys/dev/pci/if_icereg.h
4764
#define PF0INT_OICR_HLP_HMC_ERR_M BIT(26)
sys/dev/pci/if_icereg.h
4766
#define PF0INT_OICR_HLP_PE_PUSH_M BIT(27)
sys/dev/pci/if_icereg.h
4768
#define PF0INT_OICR_HLP_PE_CRITERR_M BIT(28)
sys/dev/pci/if_icereg.h
477
#define PF0INT_OICR_CPM_PAGE_CPM_RDY_M BIT(15)
sys/dev/pci/if_icereg.h
4770
#define PF0INT_OICR_HLP_VFLR_M BIT(29)
sys/dev/pci/if_icereg.h
4772
#define PF0INT_OICR_HLP_XLR_HW_DONE_M BIT(30)
sys/dev/pci/if_icereg.h
4774
#define PF0INT_OICR_HLP_SWINT_M BIT(31)
sys/dev/pci/if_icereg.h
4777
#define PF0INT_OICR_PSM_INTEVENT_M BIT(0)
sys/dev/pci/if_icereg.h
4779
#define PF0INT_OICR_PSM_QUEUE_M BIT(1)
sys/dev/pci/if_icereg.h
4783
#define PF0INT_OICR_PSM_HH_COMP_M BIT(10)
sys/dev/pci/if_icereg.h
4785
#define PF0INT_OICR_PSM_TSYN_TX_M BIT(11)
sys/dev/pci/if_icereg.h
4787
#define PF0INT_OICR_PSM_TSYN_EVNT_M BIT(12)
sys/dev/pci/if_icereg.h
4789
#define PF0INT_OICR_PSM_TSYN_TGT_M BIT(13)
sys/dev/pci/if_icereg.h
479
#define PF0INT_OICR_CPM_PAGE_ECC_ERR_M BIT(16)
sys/dev/pci/if_icereg.h
4791
#define PF0INT_OICR_PSM_HLP_RDY_M BIT(14)
sys/dev/pci/if_icereg.h
4793
#define PF0INT_OICR_PSM_CPM_RDY_M BIT(15)
sys/dev/pci/if_icereg.h
4795
#define PF0INT_OICR_PSM_ECC_ERR_M BIT(16)
sys/dev/pci/if_icereg.h
4799
#define PF0INT_OICR_PSM_MAL_DETECT_M BIT(19)
sys/dev/pci/if_icereg.h
4801
#define PF0INT_OICR_PSM_GRST_M BIT(20)
sys/dev/pci/if_icereg.h
4803
#define PF0INT_OICR_PSM_PCI_EXCEPTION_M BIT(21)
sys/dev/pci/if_icereg.h
4805
#define PF0INT_OICR_PSM_GPIO_M BIT(22)
sys/dev/pci/if_icereg.h
4807
#define PF0INT_OICR_PSM_RSV3_M BIT(23)
sys/dev/pci/if_icereg.h
4809
#define PF0INT_OICR_PSM_STORM_DETECT_M BIT(24)
sys/dev/pci/if_icereg.h
4811
#define PF0INT_OICR_PSM_LINK_STAT_CHANGE_M BIT(25)
sys/dev/pci/if_icereg.h
4813
#define PF0INT_OICR_PSM_HMC_ERR_M BIT(26)
sys/dev/pci/if_icereg.h
4815
#define PF0INT_OICR_PSM_PE_PUSH_M BIT(27)
sys/dev/pci/if_icereg.h
4817
#define PF0INT_OICR_PSM_PE_CRITERR_M BIT(28)
sys/dev/pci/if_icereg.h
4819
#define PF0INT_OICR_PSM_VFLR_M BIT(29)
sys/dev/pci/if_icereg.h
4821
#define PF0INT_OICR_PSM_XLR_HW_DONE_M BIT(30)
sys/dev/pci/if_icereg.h
4823
#define PF0INT_OICR_PSM_SWINT_M BIT(31)
sys/dev/pci/if_icereg.h
483
#define PF0INT_OICR_CPM_PAGE_MAL_DETECT_M BIT(19)
sys/dev/pci/if_icereg.h
4830
#define PF0INT_SB_CPM_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4832
#define PF0INT_SB_CPM_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4839
#define PF0INT_SB_HLP_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4841
#define PF0INT_SB_HLP_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4848
#define PFINT_AEQCTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
485
#define PF0INT_OICR_CPM_PAGE_GRST_M BIT(20)
sys/dev/pci/if_icereg.h
4850
#define PFINT_AEQCTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4857
#define PFINT_ALLOC_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
4864
#define PFINT_ALLOC_PCI_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
487
#define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_M BIT(21)
sys/dev/pci/if_icereg.h
4871
#define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4873
#define PFINT_FW_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4876
#define PFINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
4878
#define PFINT_GPIO_ENA_GPIO1_ENA_M BIT(1)
sys/dev/pci/if_icereg.h
4880
#define PFINT_GPIO_ENA_GPIO2_ENA_M BIT(2)
sys/dev/pci/if_icereg.h
4882
#define PFINT_GPIO_ENA_GPIO3_ENA_M BIT(3)
sys/dev/pci/if_icereg.h
4884
#define PFINT_GPIO_ENA_GPIO4_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
4886
#define PFINT_GPIO_ENA_GPIO5_ENA_M BIT(5)
sys/dev/pci/if_icereg.h
4888
#define PFINT_GPIO_ENA_GPIO6_ENA_M BIT(6)
sys/dev/pci/if_icereg.h
489
#define PF0INT_OICR_CPM_PAGE_GPIO_M BIT(22)
sys/dev/pci/if_icereg.h
4895
#define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4897
#define PFINT_MBX_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4900
#define PFINT_OICR_INTEVENT_M BIT(0)
sys/dev/pci/if_icereg.h
4902
#define PFINT_OICR_QUEUE_M BIT(1)
sys/dev/pci/if_icereg.h
4906
#define PFINT_OICR_HH_COMP_M BIT(10)
sys/dev/pci/if_icereg.h
4908
#define PFINT_OICR_TSYN_TX_M BIT(11)
sys/dev/pci/if_icereg.h
491
#define PF0INT_OICR_CPM_PAGE_RSV3_M BIT(23)
sys/dev/pci/if_icereg.h
4910
#define PFINT_OICR_TSYN_EVNT_M BIT(12)
sys/dev/pci/if_icereg.h
4912
#define PFINT_OICR_TSYN_TGT_M BIT(13)
sys/dev/pci/if_icereg.h
4914
#define PFINT_OICR_HLP_RDY_M BIT(14)
sys/dev/pci/if_icereg.h
4916
#define PFINT_OICR_CPM_RDY_M BIT(15)
sys/dev/pci/if_icereg.h
4918
#define PFINT_OICR_ECC_ERR_M BIT(16)
sys/dev/pci/if_icereg.h
4922
#define PFINT_OICR_MAL_DETECT_M BIT(19)
sys/dev/pci/if_icereg.h
4924
#define PFINT_OICR_GRST_M BIT(20)
sys/dev/pci/if_icereg.h
4926
#define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
sys/dev/pci/if_icereg.h
4928
#define PFINT_OICR_GPIO_M BIT(22)
sys/dev/pci/if_icereg.h
493
#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M BIT(24)
sys/dev/pci/if_icereg.h
4930
#define PFINT_OICR_RSV3_M BIT(23)
sys/dev/pci/if_icereg.h
4932
#define PFINT_OICR_STORM_DETECT_M BIT(24)
sys/dev/pci/if_icereg.h
4934
#define PFINT_OICR_LINK_STAT_CHANGE_M BIT(25)
sys/dev/pci/if_icereg.h
4936
#define PFINT_OICR_HMC_ERR_M BIT(26)
sys/dev/pci/if_icereg.h
4938
#define PFINT_OICR_PE_PUSH_M BIT(27)
sys/dev/pci/if_icereg.h
4940
#define PFINT_OICR_PE_CRITERR_M BIT(28)
sys/dev/pci/if_icereg.h
4942
#define PFINT_OICR_VFLR_M BIT(29)
sys/dev/pci/if_icereg.h
4944
#define PFINT_OICR_XLR_HW_DONE_M BIT(30)
sys/dev/pci/if_icereg.h
4946
#define PFINT_OICR_SWINT_M BIT(31)
sys/dev/pci/if_icereg.h
495
#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)
sys/dev/pci/if_icereg.h
4953
#define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4955
#define PFINT_OICR_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
4958
#define PFINT_OICR_ENA_RSV0_M BIT(0)
sys/dev/pci/if_icereg.h
4967
#define PFINT_SB_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4969
#define PFINT_SB_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
497
#define PF0INT_OICR_CPM_PAGE_HMC_ERR_M BIT(26)
sys/dev/pci/if_icereg.h
4980
#define QINT_RQCTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4982
#define QINT_RQCTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
499
#define PF0INT_OICR_CPM_PAGE_PE_PUSH_M BIT(27)
sys/dev/pci/if_icereg.h
4990
#define QINT_TQCTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
4992
#define QINT_TQCTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
5000
#define VPINT_AEQCTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
5002
#define VPINT_AEQCTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
501
#define PF0INT_OICR_CPM_PAGE_PE_CRITERR_M BIT(28)
sys/dev/pci/if_icereg.h
5010
#define VPINT_ALLOC_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
5018
#define VPINT_ALLOC_PCI_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
5026
#define VPINT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
5028
#define VPINT_MBX_CPM_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
503
#define PF0INT_OICR_CPM_PAGE_VFLR_M BIT(29)
sys/dev/pci/if_icereg.h
5036
#define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
5038
#define VPINT_MBX_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
5046
#define VPINT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
5048
#define VPINT_MBX_HLP_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
505
#define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_M BIT(30)
sys/dev/pci/if_icereg.h
5056
#define VPINT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
5058
#define VPINT_MBX_PSM_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
5066
#define VPINT_SB_CPM_CTL_CAUSE_ENA_M BIT(30)
sys/dev/pci/if_icereg.h
5068
#define VPINT_SB_CPM_CTL_INTEVENT_M BIT(31)
sys/dev/pci/if_icereg.h
507
#define PF0INT_OICR_CPM_PAGE_SWINT_M BIT(31)
sys/dev/pci/if_icereg.h
5076
#define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_M BIT(0)
sys/dev/pci/if_icereg.h
5078
#define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_M BIT(1)
sys/dev/pci/if_icereg.h
5080
#define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_M BIT(2)
sys/dev/pci/if_icereg.h
5082
#define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_M BIT(3)
sys/dev/pci/if_icereg.h
5084
#define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_M BIT(4)
sys/dev/pci/if_icereg.h
5091
#define GLLAN_RCTL_0_PXE_MODE_M BIT(0)
sys/dev/pci/if_icereg.h
5096
#define GLLAN_RCTL_1_RXDRDCTL_M BIT(17)
sys/dev/pci/if_icereg.h
5098
#define GLLAN_RCTL_1_RXDESCRDROEN_M BIT(18)
sys/dev/pci/if_icereg.h
510
#define PF0INT_OICR_ENA_CPM_PAGE_RSV0_M BIT(0)
sys/dev/pci/if_icereg.h
5100
#define GLLAN_RCTL_1_RXDATAWRROEN_M BIT(19)
sys/dev/pci/if_icereg.h
5116
#define PFLAN_CP_QALLOC_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
5123
#define PFLAN_DB_QALLOC_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
5130
#define PFLAN_RX_QALLOC_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
5137
#define PFLAN_TX_QALLOC_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
515
#define PF0INT_OICR_ENA_HLP_PAGE_RSV0_M BIT(0)
sys/dev/pci/if_icereg.h
5150
#define QRX_CTRL_QENA_REQ_M BIT(0)
sys/dev/pci/if_icereg.h
5152
#define QRX_CTRL_FAST_QDIS_M BIT(1)
sys/dev/pci/if_icereg.h
5154
#define QRX_CTRL_QENA_STAT_M BIT(2)
sys/dev/pci/if_icereg.h
5156
#define QRX_CTRL_CDE_M BIT(3)
sys/dev/pci/if_icereg.h
5158
#define QRX_CTRL_CDS_M BIT(4)
sys/dev/pci/if_icereg.h
5162
#define QRX_ITR_NO_EXPR_M BIT(0)
sys/dev/pci/if_icereg.h
5194
#define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_M BIT(0)
sys/dev/pci/if_icereg.h
520
#define PF0INT_OICR_ENA_PSM_PAGE_RSV0_M BIT(0)
sys/dev/pci/if_icereg.h
5202
#define VPLAN_RX_QBASE_VFQTABLE_ENA_M BIT(31)
sys/dev/pci/if_icereg.h
5210
#define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
5218
#define VPLAN_TX_QBASE_VFQTABLE_ENA_M BIT(31)
sys/dev/pci/if_icereg.h
5226
#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
5232
#define VSILAN_QBASE_VSIQTABLE_ENA_M BIT(11)
sys/dev/pci/if_icereg.h
5241
#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0)
sys/dev/pci/if_icereg.h
5244
#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)
sys/dev/pci/if_icereg.h
5247
#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)
sys/dev/pci/if_icereg.h
525
#define PF0INT_OICR_HLP_PAGE_INTEVENT_M BIT(0)
sys/dev/pci/if_icereg.h
5250
#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
sys/dev/pci/if_icereg.h
527
#define PF0INT_OICR_HLP_PAGE_QUEUE_M BIT(1)
sys/dev/pci/if_icereg.h
531
#define PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10)
sys/dev/pci/if_icereg.h
5320
#define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_M BIT(0)
sys/dev/pci/if_icereg.h
5322
#define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_M BIT(1)
sys/dev/pci/if_icereg.h
5324
#define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_M BIT(3)
sys/dev/pci/if_icereg.h
5326
#define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_M BIT(4)
sys/dev/pci/if_icereg.h
5328
#define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_M BIT(5)
sys/dev/pci/if_icereg.h
533
#define PF0INT_OICR_HLP_PAGE_TSYN_TX_M BIT(11)
sys/dev/pci/if_icereg.h
5330
#define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_M BIT(6)
sys/dev/pci/if_icereg.h
5332
#define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_M BIT(7)
sys/dev/pci/if_icereg.h
5334
#define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_M BIT(8)
sys/dev/pci/if_icereg.h
5336
#define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_M BIT(9)
sys/dev/pci/if_icereg.h
5338
#define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_M BIT(10)
sys/dev/pci/if_icereg.h
5340
#define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_M BIT(11)
sys/dev/pci/if_icereg.h
5342
#define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_M BIT(12)
sys/dev/pci/if_icereg.h
5344
#define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_M BIT(13)
sys/dev/pci/if_icereg.h
5346
#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_M BIT(14)
sys/dev/pci/if_icereg.h
5348
#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_M BIT(15)
sys/dev/pci/if_icereg.h
535
#define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_M BIT(12)
sys/dev/pci/if_icereg.h
5350
#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_M BIT(16)
sys/dev/pci/if_icereg.h
5352
#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M BIT(17)
sys/dev/pci/if_icereg.h
5354
#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M BIT(18)
sys/dev/pci/if_icereg.h
5356
#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)
sys/dev/pci/if_icereg.h
5358
#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)
sys/dev/pci/if_icereg.h
5360
#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M BIT(21)
sys/dev/pci/if_icereg.h
5362
#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_M BIT(22)
sys/dev/pci/if_icereg.h
5364
#define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_M BIT(23)
sys/dev/pci/if_icereg.h
5366
#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M BIT(24)
sys/dev/pci/if_icereg.h
5368
#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25)
sys/dev/pci/if_icereg.h
537
#define PF0INT_OICR_HLP_PAGE_TSYN_TGT_M BIT(13)
sys/dev/pci/if_icereg.h
5373
#define GL_MDCK_RX_DESC_ADDR_M BIT(0)
sys/dev/pci/if_icereg.h
5376
#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
sys/dev/pci/if_icereg.h
5378
#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
sys/dev/pci/if_icereg.h
5380
#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
sys/dev/pci/if_icereg.h
5382
#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
sys/dev/pci/if_icereg.h
5384
#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
sys/dev/pci/if_icereg.h
5386
#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
sys/dev/pci/if_icereg.h
5388
#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
sys/dev/pci/if_icereg.h
539
#define PF0INT_OICR_HLP_PAGE_HLP_RDY_M BIT(14)
sys/dev/pci/if_icereg.h
5390
#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
sys/dev/pci/if_icereg.h
5392
#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
sys/dev/pci/if_icereg.h
5394
#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
sys/dev/pci/if_icereg.h
5396
#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)
sys/dev/pci/if_icereg.h
54
#define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
sys/dev/pci/if_icereg.h
5407
#define GL_MDET_RX_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
541
#define PF0INT_OICR_HLP_PAGE_CPM_RDY_M BIT(15)
sys/dev/pci/if_icereg.h
5418
#define GL_MDET_TX_PQM_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
5429
#define GL_MDET_TX_TCLAN_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
543
#define PF0INT_OICR_HLP_PAGE_ECC_ERR_M BIT(16)
sys/dev/pci/if_icereg.h
5440
#define GL_MDET_TX_TDPU_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
5443
#define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0)
sys/dev/pci/if_icereg.h
5446
#define PF_MDET_RX_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
5449
#define PF_MDET_TX_PQM_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
5452
#define PF_MDET_TX_TCLAN_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
5455
#define PF_MDET_TX_TDPU_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
5459
#define VP_MDET_RX_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
5463
#define VP_MDET_TX_PQM_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
5467
#define VP_MDET_TX_TCLAN_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
547
#define PF0INT_OICR_HLP_PAGE_MAL_DETECT_M BIT(19)
sys/dev/pci/if_icereg.h
5471
#define VP_MDET_TX_TDPU_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
5481
#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0)
sys/dev/pci/if_icereg.h
5483
#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1)
sys/dev/pci/if_icereg.h
5485
#define GL_MNG_FWSM_FW_LOADING_M BIT(30)
sys/dev/pci/if_icereg.h
549
#define PF0INT_OICR_HLP_PAGE_GRST_M BIT(20)
sys/dev/pci/if_icereg.h
5491
#define GL_MNG_FWSM_EEP_RELOAD_IND_M BIT(10)
sys/dev/pci/if_icereg.h
5495
#define GL_MNG_FWSM_RSV2_M BIT(15)
sys/dev/pci/if_icereg.h
5497
#define GL_MNG_FWSM_PCIR_AL_FAILURE_M BIT(16)
sys/dev/pci/if_icereg.h
5499
#define GL_MNG_FWSM_POR_AL_FAILURE_M BIT(17)
sys/dev/pci/if_icereg.h
5501
#define GL_MNG_FWSM_RSV3_M BIT(18)
sys/dev/pci/if_icereg.h
5505
#define GL_MNG_FWSM_RSV4_M BIT(25)
sys/dev/pci/if_icereg.h
551
#define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_M BIT(21)
sys/dev/pci/if_icereg.h
5512
#define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_M BIT(0)
sys/dev/pci/if_icereg.h
5525
#define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_M BIT(30)
sys/dev/pci/if_icereg.h
5527
#define GL_MNG_SHA_EXTEND_STATUS_DONE_M BIT(31)
sys/dev/pci/if_icereg.h
553
#define PF0INT_OICR_HLP_PAGE_GPIO_M BIT(22)
sys/dev/pci/if_icereg.h
5533
#define GL_SWT_PRT2MDEF_MDEFENA_M BIT(31)
sys/dev/pci/if_icereg.h
5536
#define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_M BIT(0)
sys/dev/pci/if_icereg.h
5538
#define PRT_MNG_MANC_NCSI_DISCARD_M BIT(1)
sys/dev/pci/if_icereg.h
5540
#define PRT_MNG_MANC_RCV_TCO_EN_M BIT(17)
sys/dev/pci/if_icereg.h
5542
#define PRT_MNG_MANC_RCV_ALL_M BIT(19)
sys/dev/pci/if_icereg.h
5544
#define PRT_MNG_MANC_FIXED_NET_TYPE_M BIT(25)
sys/dev/pci/if_icereg.h
5546
#define PRT_MNG_MANC_NET_TYPE_M BIT(26)
sys/dev/pci/if_icereg.h
5548
#define PRT_MNG_MANC_EN_BMC2OS_M BIT(28)
sys/dev/pci/if_icereg.h
555
#define PF0INT_OICR_HLP_PAGE_RSV3_M BIT(23)
sys/dev/pci/if_icereg.h
5550
#define PRT_MNG_MANC_EN_BMC2NET_M BIT(29)
sys/dev/pci/if_icereg.h
5560
#define PRT_MNG_MDEF_BROADCAST_AND_M BIT(4)
sys/dev/pci/if_icereg.h
557
#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M BIT(24)
sys/dev/pci/if_icereg.h
5570
#define PRT_MNG_MDEF_BROADCAST_OR_M BIT(25)
sys/dev/pci/if_icereg.h
5572
#define PRT_MNG_MDEF_MULTICAST_AND_M BIT(26)
sys/dev/pci/if_icereg.h
5574
#define PRT_MNG_MDEF_ARP_REQUEST_OR_M BIT(27)
sys/dev/pci/if_icereg.h
5576
#define PRT_MNG_MDEF_ARP_RESPONSE_OR_M BIT(28)
sys/dev/pci/if_icereg.h
5578
#define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_M BIT(29)
sys/dev/pci/if_icereg.h
5580
#define PRT_MNG_MDEF_PORT_0X298_OR_M BIT(30)
sys/dev/pci/if_icereg.h
5582
#define PRT_MNG_MDEF_PORT_0X26F_OR_M BIT(31)
sys/dev/pci/if_icereg.h
559
#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)
sys/dev/pci/if_icereg.h
5592
#define PRT_MNG_MDEF_EXT_FLEX_TCO_M BIT(24)
sys/dev/pci/if_icereg.h
5594
#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_M BIT(25)
sys/dev/pci/if_icereg.h
5596
#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_M BIT(26)
sys/dev/pci/if_icereg.h
5598
#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_M BIT(27)
sys/dev/pci/if_icereg.h
56
#define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1)
sys/dev/pci/if_icereg.h
5600
#define PRT_MNG_MDEF_EXT_ICMP_OR_M BIT(28)
sys/dev/pci/if_icereg.h
5602
#define PRT_MNG_MDEF_EXT_MLD_M BIT(29)
sys/dev/pci/if_icereg.h
5604
#define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_M BIT(30)
sys/dev/pci/if_icereg.h
5606
#define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_M BIT(31)
sys/dev/pci/if_icereg.h
561
#define PF0INT_OICR_HLP_PAGE_HMC_ERR_M BIT(26)
sys/dev/pci/if_icereg.h
5618
#define PRT_MNG_METF_POLARITY_M BIT(30)
sys/dev/pci/if_icereg.h
5624
#define PRT_MNG_MFUTP_UDP_M BIT(16)
sys/dev/pci/if_icereg.h
5626
#define PRT_MNG_MFUTP_TCP_M BIT(17)
sys/dev/pci/if_icereg.h
5628
#define PRT_MNG_MFUTP_SOURCE_DESTINATION_M BIT(18)
sys/dev/pci/if_icereg.h
563
#define PF0INT_OICR_HLP_PAGE_PE_PUSH_M BIT(27)
sys/dev/pci/if_icereg.h
565
#define PF0INT_OICR_HLP_PAGE_PE_CRITERR_M BIT(28)
sys/dev/pci/if_icereg.h
5650
#define PRT_MNG_MSFM_PORT_26F_UDP_M BIT(0)
sys/dev/pci/if_icereg.h
5652
#define PRT_MNG_MSFM_PORT_26F_TCP_M BIT(1)
sys/dev/pci/if_icereg.h
5654
#define PRT_MNG_MSFM_PORT_298_UDP_M BIT(2)
sys/dev/pci/if_icereg.h
5656
#define PRT_MNG_MSFM_PORT_298_TCP_M BIT(3)
sys/dev/pci/if_icereg.h
5658
#define PRT_MNG_MSFM_IPV6_0_MASK_M BIT(4)
sys/dev/pci/if_icereg.h
5660
#define PRT_MNG_MSFM_IPV6_1_MASK_M BIT(5)
sys/dev/pci/if_icereg.h
5662
#define PRT_MNG_MSFM_IPV6_2_MASK_M BIT(6)
sys/dev/pci/if_icereg.h
5664
#define PRT_MNG_MSFM_IPV6_3_MASK_M BIT(7)
sys/dev/pci/if_icereg.h
567
#define PF0INT_OICR_HLP_PAGE_VFLR_M BIT(29)
sys/dev/pci/if_icereg.h
569
#define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_M BIT(30)
sys/dev/pci/if_icereg.h
5704
#define MSIX_TVCTRL_PAGE_MASK_M BIT(0)
sys/dev/pci/if_icereg.h
5708
#define MSIX_TVCTRL1_MASK_M BIT(0)
sys/dev/pci/if_icereg.h
571
#define PF0INT_OICR_HLP_PAGE_SWINT_M BIT(31)
sys/dev/pci/if_icereg.h
5711
#define GLNVM_AL_DONE_HLP_HLP_CORER_M BIT(0)
sys/dev/pci/if_icereg.h
5713
#define GLNVM_AL_DONE_HLP_HLP_FULLR_M BIT(1)
sys/dev/pci/if_icereg.h
5721
#define GLNVM_FLA_LOCKED_M BIT(6)
sys/dev/pci/if_icereg.h
5724
#define GLNVM_GENS_NVM_PRES_M BIT(0)
sys/dev/pci/if_icereg.h
5728
#define GLNVM_GENS_BANK1VAL_M BIT(8)
sys/dev/pci/if_icereg.h
5730
#define GLNVM_GENS_ALT_PRST_M BIT(23)
sys/dev/pci/if_icereg.h
5732
#define GLNVM_GENS_FL_AUTO_RD_M BIT(25)
sys/dev/pci/if_icereg.h
5739
#define GLNVM_ULD_PCIER_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
574
#define PF0INT_OICR_PSM_PAGE_INTEVENT_M BIT(0)
sys/dev/pci/if_icereg.h
5741
#define GLNVM_ULD_PCIER_DONE_1_M BIT(1)
sys/dev/pci/if_icereg.h
5743
#define GLNVM_ULD_CORER_DONE_M BIT(3)
sys/dev/pci/if_icereg.h
5745
#define GLNVM_ULD_GLOBR_DONE_M BIT(4)
sys/dev/pci/if_icereg.h
5747
#define GLNVM_ULD_POR_DONE_M BIT(5)
sys/dev/pci/if_icereg.h
5749
#define GLNVM_ULD_POR_DONE_1_M BIT(8)
sys/dev/pci/if_icereg.h
5751
#define GLNVM_ULD_PCIER_DONE_2_M BIT(9)
sys/dev/pci/if_icereg.h
5753
#define GLNVM_ULD_PE_DONE_M BIT(10)
sys/dev/pci/if_icereg.h
5755
#define GLNVM_ULD_HLP_CORE_DONE_M BIT(11)
sys/dev/pci/if_icereg.h
5757
#define GLNVM_ULD_HLP_FULL_DONE_M BIT(12)
sys/dev/pci/if_icereg.h
576
#define PF0INT_OICR_PSM_PAGE_QUEUE_M BIT(1)
sys/dev/pci/if_icereg.h
5760
#define GLNVM_ULT_CONF_PCIR_AE_M BIT(0)
sys/dev/pci/if_icereg.h
5762
#define GLNVM_ULT_CONF_PCIRTL_AE_M BIT(1)
sys/dev/pci/if_icereg.h
5764
#define GLNVM_ULT_RESERVED_1_M BIT(2)
sys/dev/pci/if_icereg.h
5766
#define GLNVM_ULT_CONF_CORE_AE_M BIT(3)
sys/dev/pci/if_icereg.h
5768
#define GLNVM_ULT_CONF_GLOBAL_AE_M BIT(4)
sys/dev/pci/if_icereg.h
5770
#define GLNVM_ULT_CONF_POR_AE_M BIT(5)
sys/dev/pci/if_icereg.h
5772
#define GLNVM_ULT_RESERVED_2_M BIT(6)
sys/dev/pci/if_icereg.h
5774
#define GLNVM_ULT_RESERVED_3_M BIT(7)
sys/dev/pci/if_icereg.h
5776
#define GLNVM_ULT_RESERVED_5_M BIT(8)
sys/dev/pci/if_icereg.h
5778
#define GLNVM_ULT_CONF_PCIALT_AE_M BIT(9)
sys/dev/pci/if_icereg.h
5780
#define GLNVM_ULT_CONF_PE_AE_M BIT(10)
sys/dev/pci/if_icereg.h
5789
#define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(0)
sys/dev/pci/if_icereg.h
5792
#define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_M BIT(0)
sys/dev/pci/if_icereg.h
5794
#define GL_PRS_MARKER_ERROR_QH_CFG_ERR_M BIT(1)
sys/dev/pci/if_icereg.h
5796
#define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_M BIT(2)
sys/dev/pci/if_icereg.h
58
#define GL_RDPU_CNTRL_BLNC_EN_M BIT(2)
sys/dev/pci/if_icereg.h
580
#define PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10)
sys/dev/pci/if_icereg.h
5811
#define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15)
sys/dev/pci/if_icereg.h
5815
#define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31)
sys/dev/pci/if_icereg.h
582
#define PF0INT_OICR_PSM_PAGE_TSYN_TX_M BIT(11)
sys/dev/pci/if_icereg.h
5830
#define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15)
sys/dev/pci/if_icereg.h
5834
#define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31)
sys/dev/pci/if_icereg.h
584
#define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_M BIT(12)
sys/dev/pci/if_icereg.h
5847
#define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(31)
sys/dev/pci/if_icereg.h
5850
#define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
sys/dev/pci/if_icereg.h
5852
#define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1)
sys/dev/pci/if_icereg.h
5855
#define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
sys/dev/pci/if_icereg.h
5857
#define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1)
sys/dev/pci/if_icereg.h
586
#define PF0INT_OICR_PSM_PAGE_TSYN_TGT_M BIT(13)
sys/dev/pci/if_icereg.h
588
#define PF0INT_OICR_PSM_PAGE_HLP_RDY_M BIT(14)
sys/dev/pci/if_icereg.h
590
#define PF0INT_OICR_PSM_PAGE_CPM_RDY_M BIT(15)
sys/dev/pci/if_icereg.h
5913
#define GLPCI_CAPCTRL_VPD_EN_M BIT(0)
sys/dev/pci/if_icereg.h
5916
#define GLPCI_CAPSUP_PCIE_VER_M BIT(0)
sys/dev/pci/if_icereg.h
5918
#define GLPCI_CAPSUP_RESERVED_2_M BIT(1)
sys/dev/pci/if_icereg.h
592
#define PF0INT_OICR_PSM_PAGE_ECC_ERR_M BIT(16)
sys/dev/pci/if_icereg.h
5920
#define GLPCI_CAPSUP_LTR_EN_M BIT(2)
sys/dev/pci/if_icereg.h
5922
#define GLPCI_CAPSUP_TPH_EN_M BIT(3)
sys/dev/pci/if_icereg.h
5924
#define GLPCI_CAPSUP_ARI_EN_M BIT(4)
sys/dev/pci/if_icereg.h
5926
#define GLPCI_CAPSUP_IOV_EN_M BIT(5)
sys/dev/pci/if_icereg.h
5928
#define GLPCI_CAPSUP_ACS_EN_M BIT(6)
sys/dev/pci/if_icereg.h
5930
#define GLPCI_CAPSUP_SEC_EN_M BIT(7)
sys/dev/pci/if_icereg.h
5932
#define GLPCI_CAPSUP_PASID_EN_M BIT(8)
sys/dev/pci/if_icereg.h
5934
#define GLPCI_CAPSUP_DLFE_EN_M BIT(9)
sys/dev/pci/if_icereg.h
5936
#define GLPCI_CAPSUP_GEN4_EXT_EN_M BIT(10)
sys/dev/pci/if_icereg.h
5938
#define GLPCI_CAPSUP_GEN4_MARG_EN_M BIT(11)
sys/dev/pci/if_icereg.h
5940
#define GLPCI_CAPSUP_ECRC_GEN_EN_M BIT(16)
sys/dev/pci/if_icereg.h
5942
#define GLPCI_CAPSUP_ECRC_CHK_EN_M BIT(17)
sys/dev/pci/if_icereg.h
5944
#define GLPCI_CAPSUP_IDO_EN_M BIT(18)
sys/dev/pci/if_icereg.h
5946
#define GLPCI_CAPSUP_MSI_MASK_M BIT(19)
sys/dev/pci/if_icereg.h
5948
#define GLPCI_CAPSUP_CSR_CONF_EN_M BIT(20)
sys/dev/pci/if_icereg.h
5950
#define GLPCI_CAPSUP_WAKUP_EN_M BIT(21)
sys/dev/pci/if_icereg.h
5952
#define GLPCI_CAPSUP_LOAD_SUBSYS_ID_M BIT(30)
sys/dev/pci/if_icereg.h
5954
#define GLPCI_CAPSUP_LOAD_DEV_ID_M BIT(31)
sys/dev/pci/if_icereg.h
5957
#define GLPCI_CNF_FLEX10_M BIT(1)
sys/dev/pci/if_icereg.h
5959
#define GLPCI_CNF_WAKE_PIN_EN_M BIT(2)
sys/dev/pci/if_icereg.h
596
#define PF0INT_OICR_PSM_PAGE_MAL_DETECT_M BIT(19)
sys/dev/pci/if_icereg.h
5961
#define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_M BIT(3)
sys/dev/pci/if_icereg.h
5964
#define GLPCI_CNF2_RO_DIS_M BIT(0)
sys/dev/pci/if_icereg.h
5966
#define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
sys/dev/pci/if_icereg.h
5972
#define GLPCI_GSCL_1_NP_C_RT_MODE_M BIT(8)
sys/dev/pci/if_icereg.h
5976
#define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_M BIT(14)
sys/dev/pci/if_icereg.h
598
#define PF0INT_OICR_PSM_PAGE_GRST_M BIT(20)
sys/dev/pci/if_icereg.h
5980
#define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_M BIT(29)
sys/dev/pci/if_icereg.h
5982
#define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_M BIT(30)
sys/dev/pci/if_icereg.h
5984
#define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_M BIT(31)
sys/dev/pci/if_icereg.h
5987
#define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_M BIT(0)
sys/dev/pci/if_icereg.h
5989
#define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_M BIT(1)
sys/dev/pci/if_icereg.h
5991
#define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_M BIT(2)
sys/dev/pci/if_icereg.h
5993
#define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_M BIT(3)
sys/dev/pci/if_icereg.h
5995
#define GLPCI_GSCL_1_P_LBC_ENABLE_0_M BIT(4)
sys/dev/pci/if_icereg.h
5997
#define GLPCI_GSCL_1_P_LBC_ENABLE_1_M BIT(5)
sys/dev/pci/if_icereg.h
5999
#define GLPCI_GSCL_1_P_LBC_ENABLE_2_M BIT(6)
sys/dev/pci/if_icereg.h
60
#define GL_RDPU_CNTRL_RECIPE_BYPASS_M BIT(3)
sys/dev/pci/if_icereg.h
600
#define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_M BIT(21)
sys/dev/pci/if_icereg.h
6001
#define GLPCI_GSCL_1_P_LBC_ENABLE_3_M BIT(7)
sys/dev/pci/if_icereg.h
6003
#define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_M BIT(14)
sys/dev/pci/if_icereg.h
6005
#define GLPCI_GSCL_1_P_GIO_64_BIT_EN_M BIT(28)
sys/dev/pci/if_icereg.h
6007
#define GLPCI_GSCL_1_P_GIO_COUNT_RESET_M BIT(29)
sys/dev/pci/if_icereg.h
6009
#define GLPCI_GSCL_1_P_GIO_COUNT_STOP_M BIT(30)
sys/dev/pci/if_icereg.h
6011
#define GLPCI_GSCL_1_P_GIO_COUNT_START_M BIT(31)
sys/dev/pci/if_icereg.h
602
#define PF0INT_OICR_PSM_PAGE_GPIO_M BIT(22)
sys/dev/pci/if_icereg.h
6036
#define GLPCI_LBARCTRL_PREFBAR_M BIT(0)
sys/dev/pci/if_icereg.h
6038
#define GLPCI_LBARCTRL_BAR32_M BIT(1)
sys/dev/pci/if_icereg.h
604
#define PF0INT_OICR_PSM_PAGE_RSV3_M BIT(23)
sys/dev/pci/if_icereg.h
6040
#define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_M BIT(2)
sys/dev/pci/if_icereg.h
6042
#define GLPCI_LBARCTRL_FLASH_EXPOSE_M BIT(3)
sys/dev/pci/if_icereg.h
6046
#define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_M BIT(9)
sys/dev/pci/if_icereg.h
6058
#define GLPCI_NPQ_CFG_EXTEND_TO_M BIT(0)
sys/dev/pci/if_icereg.h
606
#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M BIT(24)
sys/dev/pci/if_icereg.h
6060
#define GLPCI_NPQ_CFG_SMALL_TO_M BIT(1)
sys/dev/pci/if_icereg.h
608
#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)
sys/dev/pci/if_icereg.h
6085
#define GLPCI_PMSUP_RESERVED_3_M BIT(14)
sys/dev/pci/if_icereg.h
6090
#define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_M BIT(0)
sys/dev/pci/if_icereg.h
610
#define PF0INT_OICR_PSM_PAGE_HMC_ERR_M BIT(26)
sys/dev/pci/if_icereg.h
612
#define PF0INT_OICR_PSM_PAGE_PE_PUSH_M BIT(27)
sys/dev/pci/if_icereg.h
6120
#define GLPCI_VFSUP_VF_PREFETCH_M BIT(0)
sys/dev/pci/if_icereg.h
6122
#define GLPCI_VFSUP_VR_BAR_TYPE_M BIT(1)
sys/dev/pci/if_icereg.h
614
#define PF0INT_OICR_PSM_PAGE_PE_CRITERR_M BIT(28)
sys/dev/pci/if_icereg.h
6143
#define PFPCI_CLASS_STORAGE_CLASS_M BIT(0)
sys/dev/pci/if_icereg.h
6145
#define PFPCI_CLASS_PF_IS_LAN_M BIT(2)
sys/dev/pci/if_icereg.h
6148
#define PFPCI_CNF_MSI_EN_M BIT(2)
sys/dev/pci/if_icereg.h
6150
#define PFPCI_CNF_EXROM_DIS_M BIT(3)
sys/dev/pci/if_icereg.h
6152
#define PFPCI_CNF_IO_BAR_M BIT(4)
sys/dev/pci/if_icereg.h
616
#define PF0INT_OICR_PSM_PAGE_VFLR_M BIT(29)
sys/dev/pci/if_icereg.h
6164
#define PFPCI_FACTPS_FUNC_AUX_EN_M BIT(3)
sys/dev/pci/if_icereg.h
6167
#define PFPCI_FUNC_FUNC_DIS_M BIT(0)
sys/dev/pci/if_icereg.h
6169
#define PFPCI_FUNC_ALLOW_FUNC_DIS_M BIT(1)
sys/dev/pci/if_icereg.h
6171
#define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_M BIT(2)
sys/dev/pci/if_icereg.h
6174
#define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
6177
#define PFPCI_PM_PME_EN_M BIT(0)
sys/dev/pci/if_icereg.h
618
#define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_M BIT(30)
sys/dev/pci/if_icereg.h
6180
#define PFPCI_STATUS1_FUNC_VALID_M BIT(0)
sys/dev/pci/if_icereg.h
6189
#define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
6192
#define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
6198
#define PFPCI_VMPEND_PENDING_M BIT(0)
sys/dev/pci/if_icereg.h
620
#define PF0INT_OICR_PSM_PAGE_SWINT_M BIT(31)
sys/dev/pci/if_icereg.h
6203
#define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_M BIT(31)
sys/dev/pci/if_icereg.h
6229
#define GLPE_PEPM_CTRL_PEPM_ENABLE_M BIT(0)
sys/dev/pci/if_icereg.h
6231
#define GLPE_PEPM_CTRL_PEPM_HALT_M BIT(8)
sys/dev/pci/if_icereg.h
6244
#define GLPE_PEPM_DEALLOC_DEALLOC_RDY_M BIT(31)
sys/dev/pci/if_icereg.h
6332
#define PFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
6338
#define PFPE_CCQPSTATUS_CCQP_ERR_M BIT(31)
sys/dev/pci/if_icereg.h
6357
#define PFPE_CQPTAIL_CQP_OP_ERR_M BIT(31)
sys/dev/pci/if_icereg.h
6362
#define PFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16)
sys/dev/pci/if_icereg.h
6364
#define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17)
sys/dev/pci/if_icereg.h
6400
#define VFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
6406
#define VFPE_CCQPSTATUS_CCQP_ERR_M BIT(31)
sys/dev/pci/if_icereg.h
6430
#define VFPE_CQPTAIL_CQP_OP_ERR_M BIT(31)
sys/dev/pci/if_icereg.h
6436
#define VFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16)
sys/dev/pci/if_icereg.h
6438
#define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17)
sys/dev/pci/if_icereg.h
652
#define VSI_MBX_ARQLEN_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
654
#define VSI_MBX_ARQLEN_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
656
#define VSI_MBX_ARQLEN_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
658
#define VSI_MBX_ARQLEN_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
680
#define VSI_MBX_ATQLEN_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
6817
#define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_M BIT(0)
sys/dev/pci/if_icereg.h
6819
#define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_M BIT(1)
sys/dev/pci/if_icereg.h
682
#define VSI_MBX_ATQLEN_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
6821
#define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_M BIT(2)
sys/dev/pci/if_icereg.h
684
#define VSI_MBX_ATQLEN_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
686
#define VSI_MBX_ATQLEN_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
697
#define GL_ACL_ACCESS_CMD_OPERATION_M BIT(20)
sys/dev/pci/if_icereg.h
701
#define GL_ACL_ACCESS_CMD_EXECUTE_M BIT(31)
sys/dev/pci/if_icereg.h
704
#define GL_ACL_ACCESS_STATUS_BUSY_M BIT(0)
sys/dev/pci/if_icereg.h
706
#define GL_ACL_ACCESS_STATUS_DONE_M BIT(1)
sys/dev/pci/if_icereg.h
708
#define GL_ACL_ACCESS_STATUS_ERROR_M BIT(2)
sys/dev/pci/if_icereg.h
710
#define GL_ACL_ACCESS_STATUS_OPERATION_M BIT(3)
sys/dev/pci/if_icereg.h
7104
#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_M BIT(0)
sys/dev/pci/if_icereg.h
7106
#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_M BIT(1)
sys/dev/pci/if_icereg.h
7108
#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_M BIT(3)
sys/dev/pci/if_icereg.h
7111
#define GLGEN_PME_TO_PME_TO_FOR_PE_M BIT(0)
sys/dev/pci/if_icereg.h
7114
#define PRTPM_EEE_STAT_EEE_NEG_M BIT(29)
sys/dev/pci/if_icereg.h
7116
#define PRTPM_EEE_STAT_RX_LPI_STATUS_M BIT(30)
sys/dev/pci/if_icereg.h
7118
#define PRTPM_EEE_STAT_TX_LPI_STATUS_M BIT(31)
sys/dev/pci/if_icereg.h
7128
#define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_M BIT(31)
sys/dev/pci/if_icereg.h
7133
#define PRTPM_EEER_TX_LPI_EN_M BIT(16)
sys/dev/pci/if_icereg.h
7157
#define GLRPB_DSI_EN_DSI_EN_M BIT(0)
sys/dev/pci/if_icereg.h
7159
#define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_M BIT(1)
sys/dev/pci/if_icereg.h
7205
#define GLQF_FD_CTL_HASH_REPORT_M BIT(4)
sys/dev/pci/if_icereg.h
7207
#define GLQF_FD_CTL_FLT_ADDR_REPORT_M BIT(5)
sys/dev/pci/if_icereg.h
7217
#define GLQF_FDCNT_0_CNT_NOT_VLD_M BIT(31)
sys/dev/pci/if_icereg.h
7227
#define GLQF_FDINSET_FV_WORD_VAL0_M BIT(7)
sys/dev/pci/if_icereg.h
7231
#define GLQF_FDINSET_FV_WORD_VAL1_M BIT(15)
sys/dev/pci/if_icereg.h
7235
#define GLQF_FDINSET_FV_WORD_VAL2_M BIT(23)
sys/dev/pci/if_icereg.h
7239
#define GLQF_FDINSET_FV_WORD_VAL3_M BIT(31)
sys/dev/pci/if_icereg.h
7255
#define GLQF_FDSWAP_FV_WORD_VAL0_M BIT(7)
sys/dev/pci/if_icereg.h
7259
#define GLQF_FDSWAP_FV_WORD_VAL1_M BIT(15)
sys/dev/pci/if_icereg.h
7263
#define GLQF_FDSWAP_FV_WORD_VAL2_M BIT(23)
sys/dev/pci/if_icereg.h
7267
#define GLQF_FDSWAP_FV_WORD_VAL3_M BIT(31)
sys/dev/pci/if_icereg.h
7273
#define GLQF_HINSET_FV_WORD_VAL0_M BIT(7)
sys/dev/pci/if_icereg.h
7277
#define GLQF_HINSET_FV_WORD_VAL1_M BIT(15)
sys/dev/pci/if_icereg.h
7281
#define GLQF_HINSET_FV_WORD_VAL2_M BIT(23)
sys/dev/pci/if_icereg.h
7285
#define GLQF_HINSET_FV_WORD_VAL3_M BIT(31)
sys/dev/pci/if_icereg.h
729
#define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_M BIT(0)
sys/dev/pci/if_icereg.h
7309
#define GLQF_HLUT_SIZE_HSIZE_M BIT(0)
sys/dev/pci/if_icereg.h
731
#define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_M BIT(1)
sys/dev/pci/if_icereg.h
7325
#define GLQF_HSYMM_SYMM0_ENA_M BIT(7)
sys/dev/pci/if_icereg.h
7329
#define GLQF_HSYMM_SYMM1_ENA_M BIT(15)
sys/dev/pci/if_icereg.h
7333
#define GLQF_HSYMM_SYMM2_ENA_M BIT(23)
sys/dev/pci/if_icereg.h
7337
#define GLQF_HSYMM_SYMM3_ENA_M BIT(31)
sys/dev/pci/if_icereg.h
7354
#define GLQF_PE_CTL2_APBVT_ENA_M BIT(2)
sys/dev/pci/if_icereg.h
7368
#define GLQF_PEINSET_FV_WORD_VAL0_M BIT(7)
sys/dev/pci/if_icereg.h
7372
#define GLQF_PEINSET_FV_WORD_VAL1_M BIT(15)
sys/dev/pci/if_icereg.h
7376
#define GLQF_PEINSET_FV_WORD_VAL2_M BIT(23)
sys/dev/pci/if_icereg.h
7380
#define GLQF_PEINSET_FV_WORD_VAL3_M BIT(31)
sys/dev/pci/if_icereg.h
7400
#define GLQF_PETABLE_CLR_PE_BUSY_M BIT(16)
sys/dev/pci/if_icereg.h
7402
#define GLQF_PETABLE_CLR_PE_CLEAR_M BIT(17)
sys/dev/pci/if_icereg.h
7406
#define GLQF_PROF2TC_OVERRIDE_ENA_0_M BIT(0)
sys/dev/pci/if_icereg.h
7410
#define GLQF_PROF2TC_OVERRIDE_ENA_1_M BIT(4)
sys/dev/pci/if_icereg.h
7414
#define GLQF_PROF2TC_OVERRIDE_ENA_2_M BIT(8)
sys/dev/pci/if_icereg.h
7418
#define GLQF_PROF2TC_OVERRIDE_ENA_3_M BIT(12)
sys/dev/pci/if_icereg.h
7422
#define GLQF_PROF2TC_OVERRIDE_ENA_4_M BIT(16)
sys/dev/pci/if_icereg.h
7426
#define GLQF_PROF2TC_OVERRIDE_ENA_5_M BIT(20)
sys/dev/pci/if_icereg.h
7430
#define GLQF_PROF2TC_OVERRIDE_ENA_6_M BIT(24)
sys/dev/pci/if_icereg.h
7434
#define GLQF_PROF2TC_OVERRIDE_ENA_7_M BIT(28)
sys/dev/pci/if_icereg.h
7444
#define PFQF_FD_ENA_FD_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
7482
#define PFQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
7488
#define PFQF_PE_ST_CTL_PF_CNT_EN_M BIT(0)
sys/dev/pci/if_icereg.h
7490
#define PFQF_PE_ST_CTL_VFS_CNT_EN_M BIT(1)
sys/dev/pci/if_icereg.h
7492
#define PFQF_PE_ST_CTL_VF_CNT_EN_M BIT(2)
sys/dev/pci/if_icereg.h
7517
#define VPQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
7536
#define GLDCB_RMPMC_RPM_DIS_M BIT(31)
sys/dev/pci/if_icereg.h
7542
#define GLDCB_RPCC_EN_M BIT(0)
sys/dev/pci/if_icereg.h
7557
#define GLDCB_RSPMC_RPM_DIS_M BIT(31)
sys/dev/pci/if_icereg.h
7569
#define GLDCB_RTCTQ_IS_PF_Q_M BIT(16)
sys/dev/pci/if_icereg.h
769
#define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_M BIT(8)
sys/dev/pci/if_icereg.h
777
#define GL_ACL_SCENARIO_CFG_H_START_COMPARE_M BIT(24)
sys/dev/pci/if_icereg.h
779
#define GL_ACL_SCENARIO_CFG_H_START_SET_M BIT(28)
sys/dev/pci/if_icereg.h
825
#define GL_SWT_L2TAGCTRL_HAS_UP_M BIT(7)
sys/dev/pci/if_icereg.h
8264
#define EMP_SWT_PRUNIND_BIT_VALUE_M BIT(31)
sys/dev/pci/if_icereg.h
827
#define GL_SWT_L2TAGCTRL_ISVLAN_M BIT(9)
sys/dev/pci/if_icereg.h
8273
#define EMP_SWT_REPIND_BIT_VALUE_M BIT(31)
sys/dev/pci/if_icereg.h
8283
#define GL_PLG_AVG_CALC_CFG_MODE_M BIT(31)
sys/dev/pci/if_icereg.h
829
#define GL_SWT_L2TAGCTRL_INNERUP_M BIT(10)
sys/dev/pci/if_icereg.h
8290
#define GL_PLG_AVG_CALC_ST_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
8297
#define GL_PRE_CFG_CMD_CMD_M BIT(29)
sys/dev/pci/if_icereg.h
8299
#define GL_PRE_CFG_CMD_DONE_M BIT(31)
sys/dev/pci/if_icereg.h
8306
#define GL_SWT_FUNCFILT_FUNCFILT_M BIT(0)
sys/dev/pci/if_icereg.h
831
#define GL_SWT_L2TAGCTRL_OUTERUP_M BIT(11)
sys/dev/pci/if_icereg.h
833
#define GL_SWT_L2TAGCTRL_LONG_M BIT(12)
sys/dev/pci/if_icereg.h
8348
#define GL_SWT_MIRTARVSI_RULEENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
835
#define GL_SWT_L2TAGCTRL_ISMPLS_M BIT(13)
sys/dev/pci/if_icereg.h
8353
#define GL_SWT_SWIDFVIDX_PORT_TYPE_M BIT(31)
sys/dev/pci/if_icereg.h
8363
#define GLSWID_STAT_BLOCK_VEBID_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
837
#define GL_SWT_L2TAGCTRL_ISNSH_M BIT(14)
sys/dev/pci/if_icereg.h
8372
#define GLSWT_ARB_MODE_FLU_PRI_SHM_M BIT(0)
sys/dev/pci/if_icereg.h
8374
#define GLSWT_ARB_MODE_TX_RX_FWD_PRI_M BIT(1)
sys/dev/pci/if_icereg.h
8379
#define PRT_SBPVSI_SBP_M BIT(31)
sys/dev/pci/if_icereg.h
8382
#define PRT_SCSTS_BSCA_M BIT(0)
sys/dev/pci/if_icereg.h
8384
#define PRT_SCSTS_BSCAP_M BIT(1)
sys/dev/pci/if_icereg.h
8386
#define PRT_SCSTS_MSCA_M BIT(2)
sys/dev/pci/if_icereg.h
8388
#define PRT_SCSTS_MSCAP_M BIT(3)
sys/dev/pci/if_icereg.h
8399
#define PRT_SWT_MIREG_MIRENA_M BIT(7)
sys/dev/pci/if_icereg.h
8404
#define PRT_SWT_MIRIG_MIRENA_M BIT(7)
sys/dev/pci/if_icereg.h
8416
#define PRT_SWT_SCCRL_MDIPW_M BIT(0)
sys/dev/pci/if_icereg.h
8418
#define PRT_SWT_SCCRL_MDICW_M BIT(1)
sys/dev/pci/if_icereg.h
8420
#define PRT_SWT_SCCRL_BDIPW_M BIT(2)
sys/dev/pci/if_icereg.h
8422
#define PRT_SWT_SCCRL_BDICW_M BIT(3)
sys/dev/pci/if_icereg.h
8445
#define GLHH_ART_CTL_ACTIVE_M BIT(0)
sys/dev/pci/if_icereg.h
8447
#define GLHH_ART_CTL_TIME_OUT1_M BIT(1)
sys/dev/pci/if_icereg.h
8449
#define GLHH_ART_CTL_TIME_OUT2_M BIT(2)
sys/dev/pci/if_icereg.h
8451
#define GLHH_ART_CTL_RESET_HH_M BIT(31)
sys/dev/pci/if_icereg.h
8456
#define GLHH_ART_DATA_SYNC_TYPE_M BIT(3)
sys/dev/pci/if_icereg.h
8474
#define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
8480
#define GLTSYN_AUX_IN_1_INT_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
8486
#define GLTSYN_AUX_IN_2_INT_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
8490
#define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
8494
#define GLTSYN_AUX_OUT_0_OUTLVL_M BIT(3)
sys/dev/pci/if_icereg.h
8496
#define GLTSYN_AUX_OUT_0_INT_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
8502
#define GLTSYN_AUX_OUT_1_OUT_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
8506
#define GLTSYN_AUX_OUT_1_OUTLVL_M BIT(3)
sys/dev/pci/if_icereg.h
8508
#define GLTSYN_AUX_OUT_1_INT_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
8514
#define GLTSYN_AUX_OUT_2_OUT_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
8518
#define GLTSYN_AUX_OUT_2_OUTLVL_M BIT(3)
sys/dev/pci/if_icereg.h
8520
#define GLTSYN_AUX_OUT_2_INT_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
8526
#define GLTSYN_AUX_OUT_3_OUT_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
8530
#define GLTSYN_AUX_OUT_3_OUTLVL_M BIT(3)
sys/dev/pci/if_icereg.h
8532
#define GLTSYN_AUX_OUT_3_INT_ENA_M BIT(4)
sys/dev/pci/if_icereg.h
8555
#define GLTSYN_CMD_SEL_MASTER_M BIT(8)
sys/dev/pci/if_icereg.h
8562
#define GLTSYN_ENA_TSYN_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
86
#define MSIX_TVCTRL_MASK_M BIT(0)
sys/dev/pci/if_icereg.h
8626
#define GLTSYN_STAT_EVENT0_M BIT(0)
sys/dev/pci/if_icereg.h
8628
#define GLTSYN_STAT_EVENT1_M BIT(1)
sys/dev/pci/if_icereg.h
8630
#define GLTSYN_STAT_EVENT2_M BIT(2)
sys/dev/pci/if_icereg.h
8632
#define GLTSYN_STAT_TGT0_M BIT(4)
sys/dev/pci/if_icereg.h
8634
#define GLTSYN_STAT_TGT1_M BIT(5)
sys/dev/pci/if_icereg.h
8636
#define GLTSYN_STAT_TGT2_M BIT(6)
sys/dev/pci/if_icereg.h
8638
#define GLTSYN_STAT_TGT3_M BIT(7)
sys/dev/pci/if_icereg.h
8688
#define PFHH_SEM_BUSY_M BIT(0)
sys/dev/pci/if_icereg.h
8693
#define PFTSYN_SEM_BUSY_M BIT(0)
sys/dev/pci/if_icereg.h
8709
#define GLPE_TSCD_FLR_VLD_M BIT(31)
sys/dev/pci/if_icereg.h
8719
#define PF_VIRT_VSTATUS_IOV_ACTIVE_M BIT(16)
sys/dev/pci/if_icereg.h
8726
#define PF_VT_PFALLOC_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
8733
#define PF_VT_PFALLOC_HIF_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
8740
#define PF_VT_PFALLOC_PCIE_VALID_M BIT(31)
sys/dev/pci/if_icereg.h
8746
#define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_M BIT(3)
sys/dev/pci/if_icereg.h
8750
#define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_M BIT(7)
sys/dev/pci/if_icereg.h
8754
#define VSI_L2TAGSTXVALID_TIR0_INSERT_M BIT(19)
sys/dev/pci/if_icereg.h
8758
#define VSI_L2TAGSTXVALID_TIR1_INSERT_M BIT(23)
sys/dev/pci/if_icereg.h
8762
#define VSI_L2TAGSTXVALID_TIR2_INSERT_M BIT(27)
sys/dev/pci/if_icereg.h
8768
#define VSI_PASID_EN_M BIT(31)
sys/dev/pci/if_icereg.h
8790
#define VSI_RXSWCTRL_MACVSIPRUNEENABLE_M BIT(8)
sys/dev/pci/if_icereg.h
8794
#define VSI_RXSWCTRL_SRCPRUNEENABLE_M BIT(13)
sys/dev/pci/if_icereg.h
8798
#define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_M BIT(0)
sys/dev/pci/if_icereg.h
8800
#define VSI_SRCSWCTRL_ALLOWLOOPBACK_M BIT(1)
sys/dev/pci/if_icereg.h
8802
#define VSI_SRCSWCTRL_LANENABLE_M BIT(2)
sys/dev/pci/if_icereg.h
8804
#define VSI_SRCSWCTRL_MACAS_M BIT(3)
sys/dev/pci/if_icereg.h
8816
#define VSI_SWT_MIREG_MIRENA_M BIT(7)
sys/dev/pci/if_icereg.h
8822
#define VSI_SWT_MIRIG_MIRENA_M BIT(7)
sys/dev/pci/if_icereg.h
884
#define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M BIT(19)
sys/dev/pci/if_icereg.h
8902
#define VSI_VSI2F_VSI_ENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
891
#define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0)
sys/dev/pci/if_icereg.h
8912
#define VSIQF_FD_CTL1_FLT_ENA_M BIT(0)
sys/dev/pci/if_icereg.h
8914
#define VSIQF_FD_CTL1_CFG_ENA_M BIT(1)
sys/dev/pci/if_icereg.h
8916
#define VSIQF_FD_CTL1_EVICT_ENA_M BIT(2)
sys/dev/pci/if_icereg.h
8928
#define VSIQF_FD_DFLT_DEFLT_DROP_M BIT(31)
sys/dev/pci/if_icereg.h
8946
#define VSIQF_HASH_CTL_TC_OVER_ENA_M BIT(15)
sys/dev/pci/if_icereg.h
8970
#define VSIQF_PE_CTL1_PE_FLTENA_M BIT(0)
sys/dev/pci/if_icereg.h
8986
#define PFPM_APM_APME_M BIT(0)
sys/dev/pci/if_icereg.h
8989
#define PFPM_WUC_EN_APM_D0_M BIT(5)
sys/dev/pci/if_icereg.h
8992
#define PFPM_WUFC_LNKC_M BIT(0)
sys/dev/pci/if_icereg.h
8994
#define PFPM_WUFC_MAG_M BIT(1)
sys/dev/pci/if_icereg.h
8996
#define PFPM_WUFC_MNG_M BIT(3)
sys/dev/pci/if_icereg.h
8998
#define PFPM_WUFC_FLX0_ACT_M BIT(4)
sys/dev/pci/if_icereg.h
9000
#define PFPM_WUFC_FLX1_ACT_M BIT(5)
sys/dev/pci/if_icereg.h
9002
#define PFPM_WUFC_FLX2_ACT_M BIT(6)
sys/dev/pci/if_icereg.h
9004
#define PFPM_WUFC_FLX3_ACT_M BIT(7)
sys/dev/pci/if_icereg.h
9006
#define PFPM_WUFC_FLX4_ACT_M BIT(8)
sys/dev/pci/if_icereg.h
9008
#define PFPM_WUFC_FLX5_ACT_M BIT(9)
sys/dev/pci/if_icereg.h
9010
#define PFPM_WUFC_FLX6_ACT_M BIT(10)
sys/dev/pci/if_icereg.h
9012
#define PFPM_WUFC_FLX7_ACT_M BIT(11)
sys/dev/pci/if_icereg.h
9014
#define PFPM_WUFC_FLX0_M BIT(16)
sys/dev/pci/if_icereg.h
9016
#define PFPM_WUFC_FLX1_M BIT(17)
sys/dev/pci/if_icereg.h
9018
#define PFPM_WUFC_FLX2_M BIT(18)
sys/dev/pci/if_icereg.h
9020
#define PFPM_WUFC_FLX3_M BIT(19)
sys/dev/pci/if_icereg.h
9022
#define PFPM_WUFC_FLX4_M BIT(20)
sys/dev/pci/if_icereg.h
9024
#define PFPM_WUFC_FLX5_M BIT(21)
sys/dev/pci/if_icereg.h
9026
#define PFPM_WUFC_FLX6_M BIT(22)
sys/dev/pci/if_icereg.h
9028
#define PFPM_WUFC_FLX7_M BIT(23)
sys/dev/pci/if_icereg.h
9030
#define PFPM_WUFC_FW_RST_WK_M BIT(31)
sys/dev/pci/if_icereg.h
9033
#define PFPM_WUS_LNKC_M BIT(0)
sys/dev/pci/if_icereg.h
9035
#define PFPM_WUS_MAG_M BIT(1)
sys/dev/pci/if_icereg.h
9037
#define PFPM_WUS_PME_STATUS_M BIT(2)
sys/dev/pci/if_icereg.h
9039
#define PFPM_WUS_MNG_M BIT(3)
sys/dev/pci/if_icereg.h
904
#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M BIT(6)
sys/dev/pci/if_icereg.h
9041
#define PFPM_WUS_FLX0_M BIT(16)
sys/dev/pci/if_icereg.h
9043
#define PFPM_WUS_FLX1_M BIT(17)
sys/dev/pci/if_icereg.h
9045
#define PFPM_WUS_FLX2_M BIT(18)
sys/dev/pci/if_icereg.h
9047
#define PFPM_WUS_FLX3_M BIT(19)
sys/dev/pci/if_icereg.h
9049
#define PFPM_WUS_FLX4_M BIT(20)
sys/dev/pci/if_icereg.h
9051
#define PFPM_WUS_FLX5_M BIT(21)
sys/dev/pci/if_icereg.h
9053
#define PFPM_WUS_FLX6_M BIT(22)
sys/dev/pci/if_icereg.h
9055
#define PFPM_WUS_FLX7_M BIT(23)
sys/dev/pci/if_icereg.h
9057
#define PFPM_WUS_FW_RST_WK_M BIT(31)
sys/dev/pci/if_icereg.h
9065
#define PRTPM_SAH_MC_MAG_EN_M BIT(30)
sys/dev/pci/if_icereg.h
9067
#define PRTPM_SAH_AV_M BIT(31)
sys/dev/pci/if_icereg.h
9080
#define GLPE_CQM_FUNC_INVALIDATE_ENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9102
#define VF_MBX_ARQLEN1_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9104
#define VF_MBX_ARQLEN1_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9106
#define VF_MBX_ARQLEN1_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9108
#define VF_MBX_ARQLEN1_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9125
#define VF_MBX_ATQLEN1_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9127
#define VF_MBX_ATQLEN1_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9129
#define VF_MBX_ATQLEN1_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9131
#define VF_MBX_ATQLEN1_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9137
#define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
9143
#define VFINT_DYN_CTL0_INTENA_M BIT(0)
sys/dev/pci/if_icereg.h
9145
#define VFINT_DYN_CTL0_CLEARPBA_M BIT(1)
sys/dev/pci/if_icereg.h
9147
#define VFINT_DYN_CTL0_SWINT_TRIG_M BIT(2)
sys/dev/pci/if_icereg.h
9153
#define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_M BIT(24)
sys/dev/pci/if_icereg.h
9157
#define VFINT_DYN_CTL0_WB_ON_ITR_M BIT(30)
sys/dev/pci/if_icereg.h
9159
#define VFINT_DYN_CTL0_INTENA_MSK_M BIT(31)
sys/dev/pci/if_icereg.h
9163
#define VFINT_DYN_CTLN_INTENA_M BIT(0)
sys/dev/pci/if_icereg.h
9165
#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
sys/dev/pci/if_icereg.h
9167
#define VFINT_DYN_CTLN_SWINT_TRIG_M BIT(2)
sys/dev/pci/if_icereg.h
9173
#define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(24)
sys/dev/pci/if_icereg.h
9177
#define VFINT_DYN_CTLN_WB_ON_ITR_M BIT(30)
sys/dev/pci/if_icereg.h
9179
#define VFINT_DYN_CTLN_INTENA_MSK_M BIT(31)
sys/dev/pci/if_icereg.h
9211
#define VF_MBX_CPM_ARQLEN1_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9213
#define VF_MBX_CPM_ARQLEN1_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9215
#define VF_MBX_CPM_ARQLEN1_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9217
#define VF_MBX_CPM_ARQLEN1_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9234
#define VF_MBX_CPM_ATQLEN1_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9236
#define VF_MBX_CPM_ATQLEN1_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9238
#define VF_MBX_CPM_ATQLEN1_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9240
#define VF_MBX_CPM_ATQLEN1_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9259
#define VF_MBX_HLP_ARQLEN1_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9261
#define VF_MBX_HLP_ARQLEN1_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9263
#define VF_MBX_HLP_ARQLEN1_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9265
#define VF_MBX_HLP_ARQLEN1_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9282
#define VF_MBX_HLP_ATQLEN1_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9284
#define VF_MBX_HLP_ATQLEN1_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9286
#define VF_MBX_HLP_ATQLEN1_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9288
#define VF_MBX_HLP_ATQLEN1_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9307
#define VF_MBX_PSM_ARQLEN1_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9309
#define VF_MBX_PSM_ARQLEN1_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9311
#define VF_MBX_PSM_ARQLEN1_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9313
#define VF_MBX_PSM_ARQLEN1_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9330
#define VF_MBX_PSM_ATQLEN1_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9332
#define VF_MBX_PSM_ATQLEN1_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9334
#define VF_MBX_PSM_ATQLEN1_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9336
#define VF_MBX_PSM_ATQLEN1_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9355
#define VF_SB_CPM_ARQLEN1_ARQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9357
#define VF_SB_CPM_ARQLEN1_ARQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9359
#define VF_SB_CPM_ARQLEN1_ARQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9361
#define VF_SB_CPM_ARQLEN1_ARQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9378
#define VF_SB_CPM_ATQLEN1_ATQVFE_M BIT(28)
sys/dev/pci/if_icereg.h
9380
#define VF_SB_CPM_ATQLEN1_ATQOVFL_M BIT(29)
sys/dev/pci/if_icereg.h
9382
#define VF_SB_CPM_ATQLEN1_ATQCRIT_M BIT(30)
sys/dev/pci/if_icereg.h
9384
#define VF_SB_CPM_ATQLEN1_ATQENABLE_M BIT(31)
sys/dev/pci/if_icereg.h
9391
#define VFINT_DYN_CTL_INTENA_M BIT(0)
sys/dev/pci/if_icereg.h
9393
#define VFINT_DYN_CTL_CLEARPBA_M BIT(1)
sys/dev/pci/if_icereg.h
9395
#define VFINT_DYN_CTL_SWINT_TRIG_M BIT(2)
sys/dev/pci/if_icereg.h
9401
#define VFINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
sys/dev/pci/if_icereg.h
9405
#define VFINT_DYN_CTL_WB_ON_ITR_M BIT(30)
sys/dev/pci/if_icereg.h
9407
#define VFINT_DYN_CTL_INTENA_MSK_M BIT(31)
sys/dev/pci/if_icereg.h
9447
#define VFPE_CCQPSTATUS1_CCQP_DONE_M BIT(0)
sys/dev/pci/if_icereg.h
9453
#define VFPE_CCQPSTATUS1_CCQP_ERR_M BIT(31)
sys/dev/pci/if_icereg.h
9472
#define VFPE_CQPTAIL1_CQP_OP_ERR_M BIT(31)
sys/dev/pci/if_icereg.h
9477
#define VFPE_IPCONFIG01_USEENTIREIDRANGE_M BIT(16)
sys/dev/pci/if_icereg.h
9479
#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M BIT(17)
sys/dev/pci/if_icereg.h
9554
#define ICE_AQC_DRIVER_UNLOADING BIT(0)
sys/dev/pci/if_icereg.h
9675
#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
sys/dev/pci/if_icereg.h
9676
#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
sys/dev/pci/if_icereg.h
9677
#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
sys/dev/pci/if_icereg.h
9678
#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
sys/dev/pci/if_icereg.h
9679
#define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
sys/dev/pci/if_icereg.h
9680
#define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
sys/dev/pci/if_icereg.h
9703
#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
sys/dev/pci/if_icereg.h
9704
#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
sys/dev/pci/if_icereg.h
9708
#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
sys/dev/pci/if_icereg.h
9725
#define ICE_AQC_FORCE_NO_DROP BIT(0)
sys/dev/pci/if_icereg.h
974
#define GLTCLAN_CQ_CNTX3_GENERATION_M BIT(0)
sys/dev/pci/if_icereg.h
9769
#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
sys/dev/pci/if_icereg.h
9775
#define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0)
sys/dev/pci/if_icereg.h
9776
#define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1)
sys/dev/pci/if_icereg.h
9777
#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
sys/dev/pci/if_icereg.h
9781
#define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15)
sys/dev/pci/if_icereg.h
9788
#define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14)
sys/dev/pci/if_icereg.h
9789
#define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15)
sys/dev/pci/if_icereg.h
9828
#define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
sys/dev/pci/if_icereg.h
9829
#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
sys/dev/pci/if_icereg.h
9830
#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
sys/dev/pci/if_icereg.h
9831
#define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14)
sys/dev/pci/if_icereg.h
9832
#define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15)
sys/dev/pci/if_icereg.h
988
#define GLTCLAN_CQ_CNTX5_TPH_EN_M BIT(0)
sys/dev/pci/if_icereg.h
992
#define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_M BIT(9)
sys/dev/pci/if_icereg.h
9932
#define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
sys/dev/pci/if_icereg.h
9946
#define ICE_AQ_VSI_IS_VALID BIT(15)
sys/dev/pci/if_icereg.h
9991
#define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
sys/dev/pci/if_icereg.h
9992
#define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
sys/dev/pci/if_icereg.h
9993
#define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
sys/dev/pci/if_icereg.h
9994
#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
sys/dev/pci/if_icereg.h
9995
#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
sys/dev/pci/if_icereg.h
9996
#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
sys/dev/pci/if_icereg.h
9997
#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
sys/dev/pci/if_icereg.h
9998
#define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
sys/dev/pci/if_icereg.h
9999
#define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
sys/dev/pci/if_icevar.h
1014
#define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
sys/dev/pci/if_icevar.h
1015
#define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
sys/dev/pci/if_icevar.h
1016
#define ICE_MGMT_MODE_PROTO_OEM BIT(2)
sys/dev/pci/if_icevar.h
1017
#define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
sys/dev/pci/if_icevar.h
1073
#define ICE_WOL_SUPPORT_M BIT(0)
sys/dev/pci/if_icevar.h
1074
#define ICE_ACPI_PROG_MTHD_M BIT(1)
sys/dev/pci/if_icevar.h
1075
#define ICE_PROXY_SUPPORT_M BIT(2)
sys/dev/pci/if_icevar.h
1083
#define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
sys/dev/pci/if_icevar.h
1084
#define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
sys/dev/pci/if_icevar.h
1085
#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
sys/dev/pci/if_icevar.h
1086
#define ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5)
sys/dev/pci/if_icevar.h
1101
#define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)
sys/dev/pci/if_icevar.h
1103
#define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
sys/dev/pci/if_icevar.h
1105
#define ICE_EXT_TOPO_DEV_IMG_VER_SCHEMA BIT(2)
sys/dev/pci/if_icevar.h
1112
#define ICE_NAC_TOPO_PRIMARY_M BIT(0)
sys/dev/pci/if_icevar.h
1113
#define ICE_NAC_TOPO_DUAL_M BIT(1)
sys/dev/pci/if_icevar.h
1131
#define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
sys/dev/pci/if_icevar.h
1132
#define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
sys/dev/pci/if_icevar.h
1133
#define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
sys/dev/pci/if_icevar.h
1134
#define ICE_LINK_OVERRIDE_EN BIT(3)
sys/dev/pci/if_icevar.h
1135
#define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
sys/dev/pci/if_icevar.h
1136
#define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
sys/dev/pci/if_icevar.h
1141
#define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
sys/dev/pci/if_icevar.h
1142
#define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
sys/dev/pci/if_icevar.h
1435
#define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
sys/dev/pci/if_icevar.h
1436
#define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
sys/dev/pci/if_icevar.h
1437
#define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
sys/dev/pci/if_icevar.h
1439
#define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
sys/dev/pci/if_icevar.h
144
return !!(*bitmap & BIT(nr));
sys/dev/pci/if_icevar.h
1525
#define ICE_SENSOR_SUPPORT_E810_INT_TEMP BIT(0)
sys/dev/pci/if_icevar.h
1543
#define ICE_KBYTE_GRANULARITY BIT(11)
sys/dev/pci/if_icevar.h
1546
((BIT(11) - 1) * 1024) /* In Bytes */
sys/dev/pci/if_icevar.h
1548
((BIT(11) - 1) * 64) /* In Bytes */
sys/dev/pci/if_icevar.h
162
*bitmap &= ~BIT(nr);
sys/dev/pci/if_icevar.h
167
*bitmap |= BIT(nr);
sys/dev/pci/if_icevar.h
1751
#define ICE_IEEE_ETS_CBS_M BIT(ICE_IEEE_ETS_CBS_S)
sys/dev/pci/if_icevar.h
1753
#define ICE_IEEE_ETS_WILLING_M BIT(ICE_IEEE_ETS_WILLING_S)
sys/dev/pci/if_icevar.h
1774
#define ICE_IEEE_PFC_MBC_M BIT(ICE_IEEE_PFC_MBC_S)
sys/dev/pci/if_icevar.h
1776
#define ICE_IEEE_PFC_WILLING_M BIT(ICE_IEEE_PFC_WILLING_S)
sys/dev/pci/if_icevar.h
2471
#define ICE_FLTR_RX BIT(0)
sys/dev/pci/if_icevar.h
2472
#define ICE_FLTR_TX BIT(1)
sys/dev/pci/if_icevar.h
2473
#define ICE_FLTR_RX_LB BIT(2)
sys/dev/pci/if_icevar.h
588
if (entry & BIT(j))
sys/dev/pci/if_icevar.h
603
if (entry & BIT(j))
sys/dev/pci/if_icevar.h
734
#define ICE_DFLT_TRAFFIC_CLASS BIT(0)
sys/dev/pci/if_icevar.h
826
#define ICE_APPLY_LS BIT(0)
sys/dev/pci/if_icevar.h
827
#define ICE_APPLY_FEC BIT(1)
sys/dev/pci/if_icevar.h
828
#define ICE_APPLY_FC BIT(2)
sys/dev/pci/if_iwxreg.h
4640
#define IWX_TWT_SUPPORTED BIT (1 << 0)
sys/dev/pci/if_mwx.c
4408
if (!(status->chains & BIT(i)) ||
usr.bin/lastcomm/lastcomm.c
173
BIT(AFORK, 'F');
usr.bin/lastcomm/lastcomm.c
174
BIT(AMAP, 'M');
usr.bin/lastcomm/lastcomm.c
175
BIT(ACORE, 'D');
usr.bin/lastcomm/lastcomm.c
176
BIT(AXSIG, 'X');
usr.bin/lastcomm/lastcomm.c
177
BIT(APLEDGE, 'P');
usr.bin/lastcomm/lastcomm.c
178
BIT(ATRAP, 'T');
usr.bin/lastcomm/lastcomm.c
179
BIT(AUNVEIL, 'U');
usr.bin/lastcomm/lastcomm.c
180
BIT(APINSYS, 'S');
usr.bin/lastcomm/lastcomm.c
181
BIT(ABTCFI, 'B');
usr.bin/yacc/mkpar.c
141
if (BIT(rowp, j))
usr.sbin/snmpd/mib.y
1011
{ "BIT", BIT },
usr.sbin/snmpd/mib.y
287
%token BIT BITS BOOLEAN BY CHOICE COMPONENT COMPONENTS CONTACTINFO
