PORT_C
return pio0[PORT_C];
return port == PORT_B || port == PORT_C;
return port == PORT_B || port == PORT_C || port == PORT_D;
enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C;
[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
[PORT_C] = { -1 },
[PORT_C] = { -1 },
[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
return PORT_C;
case PORT_C:
[PORT_C] = TRANSCODER_B,
if (port >= PORT_C)
return HPD_PORT_TC1 + port - PORT_C;
return port >= PORT_C;
case PORT_C:
port >= PORT_C ? " (TC)" : "",
return TC_PORT_1 + port - PORT_C;
for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
g4x_hdmi_init(display, PCH_HDMIC, PORT_C);
g4x_dp_init(display, PCH_DP_C, PORT_C);
has_edp = intel_dp_is_port_edp(display, PORT_C);
has_port = intel_bios_is_port_present(display, PORT_C);
has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);
g4x_hdmi_init(display, VLV_HDMIC, PORT_C);
found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C);
g4x_hdmi_init(display, GEN4_HDMIC, PORT_C);
g4x_dp_init(display, DP_C, PORT_C);
case PORT_C:
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
.port_start = PORT_C,
.port_end = PORT_C,
.port_end = PORT_C,
port != PORT_B && port != PORT_C))
case PORT_C:
[DPIO_CH1] = { .port = PORT_C },
[DPIO_CH0] = { .port = PORT_C },
case PORT_C:
case PORT_C:
if (intel_dsi->ports & BIT(PORT_C))
return PORT_C;
.port = PORT_C,
.port = PORT_C,
.port = PORT_C,
.port = PORT_C,
.port = PORT_C,
case PORT_C:
case PORT_C:
case PORT_C:
case PORT_C:
WARN_ON(encoder->port == PORT_C);
WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C);
case PORT_C:
assert_pch_hdmi_disabled(display, pipe, PORT_C, PCH_HDMIC);
ibx_sanitize_pch_dp_port(display, PORT_C, PCH_DP_C);
ibx_sanitize_pch_hdmi_port(display, PORT_C, PCH_HDMIC);
assert_pch_dp_disabled(display, pipe, PORT_C, PCH_DP_C);
case PORT_C:
case PORT_C:
g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);
return port == PORT_B || port == PORT_C;
MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
if (intel_dsi->ports == BIT(PORT_C))
if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
port == PORT_C)
if (intel_dsi->ports & (1 << PORT_C))
for (port = PORT_A; port <= PORT_C; port++) {
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
(PORT_C << TRANS_DDI_PORT_SHIFT) |
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
port = PORT_C;
port = PORT_C;
port = PORT_C;
MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
case PORT_C:
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
MMIO_D(BXT_PHY_CTL(PORT_C));
MMIO_D(BXT_PORT_PLL_ENABLE(PORT_C));
MMIO_D(PORT_CLK_SEL(PORT_C));
MMIO_D(DDI_BUF_CTL(PORT_C));
MMIO_D(DP_TP_CTL(PORT_C));
MMIO_D(DP_TP_STATUS(PORT_C));