#include <sys/cdefs.h>
#include "opt_modular.h"
#include <sys/param.h>
#include <sys/cpu.h>
#include <sys/exec.h>
#include <sys/ksyms.h>
#include <sys/msgbuf.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <machine/ia64_cpu.h>
#include <machine/pal.h>
#include <machine/sal.h>
#include <machine/ssc.h>
#include <machine/md_var.h>
#include <machine/fpu.h>
#include <machine/efi.h>
#include <machine/bootinfo.h>
#include <machine/vmparam.h>
#include <machine/atomic.h>
#include <machine/pte.h>
#include <machine/pcb.h>
#include <uvm/uvm.h>
#include <dev/cons.h>
#include <dev/mm.h>
#ifdef DEBUG
#define DPRINTF(fmt, args...) printf("%s: " fmt, __func__, ##args)
#else
#define DPRINTF(fmt, args...) ((void)0)
#endif
char machine[] = MACHINE;
char machine_arch[] = MACHINE_ARCH;
#if NKSYMS || defined(DDB) || defined(MODULAR)
void *ksym_start, *ksym_end;
vaddr_t ia64_unwindtab;
vsize_t ia64_unwindtablen;
#endif
struct vm_map *phys_map = NULL;
void *msgbufaddr;
vaddr_t kernstart, kernend;
uint64_t processor_frequency;
uint64_t bus_frequency;
uint64_t itc_frequency;
uint64_t ia64_pal_base;
uint64_t ia64_pal_size;
uint64_t ia64_port_base;
int ia64_sync_icache_needed = 0;
extern uint64_t ia64_gateway_page[];
uint64_t pa_bootinfo;
struct bootinfo bootinfo;
extern vaddr_t kstack, kstack_top;
extern vaddr_t kernel_text, end;
struct fpswa_iface *fpswa_iface;
void
cpu_startup(void)
{
vaddr_t minaddr, maxaddr;
#ifdef PERFMON
perfmon_init();
#endif
printf("Detected memory = %ld (%ld MB)\n", ia64_ptob(physmem),
ptoa(physmem) / 1048576);
if (bootverbose) {
int sizetmp, vm_nphysseg;
uvm_physseg_t upm;
printf("Physical memory chunk(s):\n");
for (vm_nphysseg = 0, upm = uvm_physseg_get_first();
uvm_physseg_valid_p(upm);
vm_nphysseg++, upm = uvm_physseg_get_next(upm)) {
sizetmp = uvm_physseg_get_avail_end(upm) -
uvm_physseg_get_avail_start(upm);
printf("0x%016lx - 0x%016lx, %ld bytes (%d pages)\n",
ptoa(uvm_physseg_get_avail_start(upm)),
ptoa(uvm_physseg_get_avail_end(upm)) - 1,
ptoa(sizetmp), sizetmp);
}
printf("Total number of segments: vm_nphysseg = %d \n",
vm_nphysseg);
}
minaddr = 0;
phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
VM_PHYS_SIZE, 0, false, NULL);
banner();
if (fpswa_iface == NULL)
printf("Warning: no FPSWA package supplied\n");
else
printf("FPSWA Revision = 0x%lx, Entry = %p\n",
(long)fpswa_iface->if_rev, (void *)fpswa_iface->if_fpswa);
ia64_probe_sapics();
}
void
cpu_reboot(int howto, char *bootstr)
{
efi_reset_system();
panic("XXX: Reset didn't work ? \n");
}
bool
cpu_intr_p(void)
{
return 0;
}
void
cpu_dumpconf(void)
{
return;
}
void
map_vhpt(uintptr_t vhpt)
{
pt_entry_t pte;
uint64_t psr;
register uint64_t log2size = pmap_vhpt_log2size << 2;
pte = PTE_PRESENT | PTE_MA_WB | PTE_ACCESSED | PTE_DIRTY |
PTE_PL_KERN | PTE_AR_RW;
pte |= vhpt & PTE_PPN_MASK;
__asm __volatile("ptr.d %0,%1" :: "r"(vhpt), "r"(log2size));
__asm __volatile("mov %0=psr" : "=r"(psr));
__asm __volatile("rsm psr.ic|psr.i");
ia64_srlz_i();
ia64_set_ifa(vhpt);
ia64_set_itir(log2size);
ia64_srlz_d();
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(3), "r"(pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
ia64_srlz_i();
}
void
map_pal_code(void)
{
pt_entry_t pte;
uint64_t psr;
if (ia64_pal_base == 0)
return;
pte = PTE_PRESENT | PTE_MA_WB | PTE_ACCESSED | PTE_DIRTY |
PTE_PL_KERN | PTE_AR_RWX;
pte |= ia64_pal_base & PTE_PPN_MASK;
__asm __volatile("ptr.d %0,%1; ptr.i %0,%1" ::
"r"(IA64_PHYS_TO_RR7(ia64_pal_base)),
"r"(IA64_ID_PAGE_SHIFT<<2));
__asm __volatile("mov %0=psr" : "=r"(psr));
__asm __volatile("rsm psr.ic|psr.i");
ia64_srlz_i();
ia64_set_ifa(IA64_PHYS_TO_RR7(ia64_pal_base));
ia64_set_itir(IA64_ID_PAGE_SHIFT << 2);
ia64_srlz_d();
__asm __volatile("itr.d dtr[%0]=%1" ::
"r"(1), "r"(*(pt_entry_t *)&pte));
ia64_srlz_d();
__asm __volatile("itr.i itr[%0]=%1" ::
"r"(1), "r"(*(pt_entry_t *)&pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
ia64_srlz_i();
}
void
map_gateway_page(void)
{
pt_entry_t pte;
uint64_t psr;
pte = PTE_PRESENT | PTE_MA_WB | PTE_ACCESSED | PTE_DIRTY |
PTE_PL_KERN | PTE_AR_X_RX;
pte |= (uint64_t)ia64_gateway_page & PTE_PPN_MASK;
__asm __volatile("ptr.d %0,%1; ptr.i %0,%1" ::
"r"(VM_MAX_ADDRESS), "r"(PAGE_SHIFT << 2));
__asm __volatile("mov %0=psr" : "=r"(psr));
__asm __volatile("rsm psr.ic|psr.i");
ia64_srlz_i();
ia64_set_ifa(VM_MAX_ADDRESS);
ia64_set_itir(PAGE_SHIFT << 2);
ia64_srlz_d();
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(3), "r"(*(pt_entry_t*)&pte));
ia64_srlz_d();
__asm __volatile("itr.i itr[%0]=%1" :: "r"(3), "r"(*(pt_entry_t*)&pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
ia64_srlz_i();
ia64_set_k5(VM_MAX_ADDRESS);
}
static void
calculate_frequencies(void)
{
struct ia64_sal_result sal;
struct ia64_pal_result pal;
sal = ia64_sal_entry(SAL_FREQ_BASE, 0, 0, 0, 0, 0, 0, 0);
pal = ia64_call_pal_static(PAL_FREQ_RATIOS, 0, 0, 0);
if (sal.sal_status == 0 && pal.pal_status == 0) {
if (bootverbose) {
printf("Platform clock frequency %ld Hz\n",
sal.sal_result[0]);
printf("Processor ratio %ld/%ld, Bus ratio %ld/%ld, "
"ITC ratio %ld/%ld\n",
pal.pal_result[0] >> 32,
pal.pal_result[0] & ((1L << 32) - 1),
pal.pal_result[1] >> 32,
pal.pal_result[1] & ((1L << 32) - 1),
pal.pal_result[2] >> 32,
pal.pal_result[2] & ((1L << 32) - 1));
}
processor_frequency =
sal.sal_result[0] * (pal.pal_result[0] >> 32)
/ (pal.pal_result[0] & ((1L << 32) - 1));
bus_frequency =
sal.sal_result[0] * (pal.pal_result[1] >> 32)
/ (pal.pal_result[1] & ((1L << 32) - 1));
itc_frequency =
sal.sal_result[0] * (pal.pal_result[2] >> 32)
/ (pal.pal_result[2] & ((1L << 32) - 1));
}
}
register struct cpu_info *ci __asm__("r13");
struct ia64_init_return
ia64_init(void)
{
struct ia64_init_return ret;
paddr_t kernstartpfn, kernendpfn, pfn0, pfn1;
struct pcb *pcb0;
struct efi_md *md;
vaddr_t v;
ia64_set_fpsr(IA64_FPSR_DEFAULT);
ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (LOG2_ID_PAGE_SIZE << 2));
ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (LOG2_ID_PAGE_SIZE << 2));
ia64_srlz_d();
bootinfo = *(struct bootinfo *)(IA64_PHYS_TO_RR7(pa_bootinfo));
if (bootinfo.bi_magic != BOOTINFO_MAGIC || bootinfo.bi_version != 1) {
memset(&bootinfo, 0, sizeof(bootinfo));
bootinfo.bi_kernend = (vaddr_t) round_page((vaddr_t)&end);
}
for (md = efi_md_first(); md != NULL; md = efi_md_next(md)) {
switch (md->md_type) {
case EFI_MD_TYPE_IOPORT:
ia64_port_base = IA64_PHYS_TO_RR6(md->md_phys);
break;
case EFI_MD_TYPE_PALCODE:
ia64_pal_base = md->md_phys;
break;
}
}
boothowto = bootinfo.bi_boothowto;
boothowto |= AB_VERBOSE;
cninit();
if (ia64_pal_base != 0) {
ia64_pal_base &= ~IA64_ID_PAGE_MASK;
if (ia64_pal_base == 0)
printf("PAL code mapped by the kernel's TR\n");
} else
printf("PAL code not found\n");
map_pal_code();
efi_boot_minimal(bootinfo.bi_systab);
ia64_sal_init();
calculate_frequencies();
kernstart = trunc_page((vaddr_t) &kernel_text);
#ifdef DDB
ia64_unwindtab = (uint64_t)bootinfo.bi_unwindtab;
ia64_unwindtablen = (uint64_t)bootinfo.bi_unwindtablen;
ksym_start = (void *)bootinfo.bi_symtab;
ksym_end = (void *)bootinfo.bi_esymtab;
kernend = (vaddr_t)round_page((vaddr_t)bootinfo.bi_kernend);
#else
kernend = (vaddr_t)round_page(bootinfo.bi_kernend);
#endif
kernstartpfn = atop(IA64_RR_MASK(kernstart));
kernendpfn = atop(IA64_RR_MASK(kernend));
uvmexp.pagesize = PAGE_SIZE;
uvm_md_init();
physmem = 0;
for (md = efi_md_first(); md != NULL; md = efi_md_next(md)) {
DPRINTF("MD %p: type %d pa 0x%lx cnt 0x%lx\n", md,
md->md_type, md->md_phys, md->md_pages);
pfn0 = ia64_btop(round_page(md->md_phys));
pfn1 = ia64_btop(trunc_page(md->md_phys + md->md_pages * 4096));
if (pfn1 <= pfn0)
continue;
if (md->md_type != EFI_MD_TYPE_FREE)
continue;
if (pfn0 >= ia64_btop(0x100000000UL)) {
printf("Skipping memory chunk start 0x%lx\n",
md->md_phys);
continue;
}
if (pfn1 >= ia64_btop(0x100000000UL)) {
printf("Skipping memory chunk end 0x%lx\n",
md->md_phys + md->md_pages * 4096);
continue;
}
physmem += (pfn1 - pfn0);
if (pfn0 <= kernendpfn && kernstartpfn <= pfn1) {
DPRINTF("Descriptor %p contains kernel\n", md);
if (pfn0 < kernstartpfn) {
DPRINTF("Loading chunk before kernel: "
"0x%lx / 0x%lx\n", pfn0, kernstartpfn);
uvm_page_physload(pfn0, kernstartpfn,
pfn0, kernstartpfn, VM_FREELIST_DEFAULT);
}
if (kernendpfn < pfn1) {
DPRINTF("Loading chunk after kernel: "
"0x%lx / 0x%lx\n", kernendpfn, pfn1);
uvm_page_physload(kernendpfn, pfn1,
kernendpfn, pfn1, VM_FREELIST_DEFAULT);
}
} else {
DPRINTF("Loading descriptor %p: 0x%lx / 0x%lx\n",
md, pfn0, pfn1);
uvm_page_physload(pfn0, pfn1, pfn0, pfn1,
VM_FREELIST_DEFAULT);
}
}
if (physmem == 0)
panic("can't happen: system seems to have no memory!");
msgbufaddr = (void *) uvm_pageboot_alloc(MSGBUFSIZE);
initmsgbuf(msgbufaddr, MSGBUFSIZE);
v = (vaddr_t)&kstack;
uvm_lwp_setuarea(&lwp0, v);
lwp0.l_md.md_tf = (struct trapframe *)(v + UAREA_TF_OFFSET);
lwp0.l_md.md_tf->tf_length = sizeof(struct trapframe);
lwp0.l_md.md_tf->tf_flags = FRAME_SYSCALL;
lwp0.l_md.user_stack = NULL;
lwp0.l_md.user_stack_size = 0;
pcb0 = lwp_getpcb(&lwp0);
pcb0->pcb_special.sp = v + UAREA_SP_OFFSET;
pcb0->pcb_special.bspstore = v + UAREA_BSPSTORE_OFFSET;
ci = curcpu();
ia64_set_k4((uint64_t) ci);
ci->ci_cpuid = cpu_number();
ci->ci_curlwp = &lwp0;
ci->ci_idle_pcb = pcb0;
lwp0.l_cpu = ci;
ia64_set_tpr(0);
ia64_srlz_d();
mutex_init(&pcb0->pcb_fpcpu_slock, MUTEX_DEFAULT, 0);
if (savectx(pcb0))
panic("savectx failed");
pmap_bootstrap();
#if NKSYMS || defined(DDB) || defined(MODULAR)
ksyms_addsyms_elf((int)((uint64_t)ksym_end - (uint64_t)ksym_start),
ksym_start, ksym_end);
#endif
#ifdef DDB
if (boothowto & RB_KDB)
Debugger();
#endif
ret.bspstore = pcb0->pcb_special.bspstore;
ret.sp = pcb0->pcb_special.sp;
return (ret);
}
uint64_t
ia64_get_hcdp(void)
{
return bootinfo.bi_hcdp;
}
void
setregs(register struct lwp *l, struct exec_package *pack, vaddr_t stack)
{
struct trapframe *tf;
uint64_t *ksttop, *kst, regstkp;
vaddr_t uv = uvm_lwp_getuarea(l);
tf = l->l_md.md_tf;
memset(tf, 0, sizeof(*tf));
regstkp = uv + sizeof(struct pcb);
ksttop =
(uint64_t*)(regstkp + tf->tf_special.ndirty +
(tf->tf_special.bspstore & 0x1ffUL));
KASSERT((tf->tf_special.ndirty & ~PAGE_MASK) == 0);
memset(&tf->tf_special, 0, sizeof(tf->tf_special));
if ((tf->tf_flags & FRAME_SYSCALL) == 0) {
memset(&tf->tf_scratch, 0, sizeof(tf->tf_scratch));
memset(&tf->tf_scratch_fp, 0, sizeof(tf->tf_scratch_fp));
tf->tf_special.cfm = (1UL<<63) | (3UL<<7) | 3UL;
tf->tf_special.bspstore = IA64_BACKINGSTORE;
kst = ksttop - 1;
if (((uintptr_t)kst & 0x1ff) == 0x1f8)
*kst-- = 0;
*kst-- = stack;
if (((uintptr_t)kst & 0x1ff) == 0x1f8)
*kst-- = 0;
*kst-- = l->l_proc->p_psstrp;
if (((uintptr_t)kst & 0x1ff) == 0x1f8)
*kst-- = 0;
*kst-- = 0;
if (((uintptr_t)kst & 0x1ff) == 0x1f8)
*kst-- = 0;
*kst = 0;
tf->tf_special.ndirty = (ksttop - kst) << 3;
} else {
tf->tf_special.cfm = (3UL<<62) | (3UL<<7) | 3UL;
tf->tf_special.bspstore = IA64_BACKINGSTORE + 24;
ustore_long((u_long *)(tf->tf_special.bspstore - 32), 0);
ustore_long((u_long *)(tf->tf_special.bspstore - 24), 0);
ustore_long((u_long *)(tf->tf_special.bspstore - 16),
l->l_proc->p_psstrp);
ustore_long((u_long *)(tf->tf_special.bspstore - 8),
stack);
}
tf->tf_special.iip = pack->ep_entry;
tf->tf_special.sp = (stack & ~15) - 16;
tf->tf_special.rsc = 0xf;
tf->tf_special.fpsr = IA64_FPSR_DEFAULT;
tf->tf_special.psr = IA64_PSR_IC | IA64_PSR_I | IA64_PSR_IT |
IA64_PSR_DT | IA64_PSR_RT | IA64_PSR_DFH | IA64_PSR_BN |
IA64_PSR_CPL_USER;
return;
}
void
sendsig_siginfo(const ksiginfo_t *ksi, const sigset_t *mask)
{
return;
}
void
cpu_getmcontext(struct lwp *l, mcontext_t *mcp, unsigned int *flags)
{
return;
}
int
cpu_setmcontext(struct lwp *l, const mcontext_t *mcp, unsigned int flags)
{
return EINVAL;
}
int
cpu_mcontext_validate(struct lwp *l, const mcontext_t *mcp)
{
return EINVAL;
}
int
mm_md_physacc(paddr_t pa, vm_prot_t prot)
{
return 0;
}
void
ia64_sync_icache(vaddr_t va, vsize_t sz)
{
vaddr_t lim;
if (!ia64_sync_icache_needed)
return;
lim = va + sz;
while (va < lim) {
ia64_fc_i(va);
va += 32;
}
ia64_sync_i();
ia64_srlz_i();
}
void
makectx(struct trapframe *tf, struct pcb *pcb)
{
pcb->pcb_special = tf->tf_special;
pcb->pcb_special.__spare = ~0UL;
save_callee_saved(&pcb->pcb_preserved);
save_callee_saved_fp(&pcb->pcb_preserved_fp);
}