Symbol: MIPS_INT_MASK_4
sys/arch/algor/algor/algor_intr.c
142
MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
sys/arch/algor/algor/algor_p4032_intr.c
423
if (ipending & MIPS_INT_MASK_4) {
sys/arch/algor/algor/algor_p5064_intr.c
516
if (ipending & MIPS_INT_MASK_4) {
sys/arch/arc/arc/c_magnum.c
114
return MIPS_INT_MASK_4; /* Keep clock interrupts enabled */
sys/arch/arc/arc/c_magnum.c
179
out32(R4030_SYS_EXT_IMASK, cpu_int_mask & (~MIPS_INT_MASK_4 >> 10));
sys/arch/arc/arc/c_magnum.c
80
MIPS_INT_MASK_4,
sys/arch/cobalt/cobalt/interrupt.c
460
if (pending & MIPS_INT_MASK_4) {
sys/arch/evbmips/gdium/gdium_intr.c
153
MIPS_INT_MASK_4,
sys/arch/evbmips/gdium/gdium_intr.c
160
MIPS_INT_MASK_4 |
sys/arch/evbmips/gdium/gdium_intr.c
310
if ((ipending & (MIPS_INT_MASK_4 << level)) == 0)
sys/arch/evbmips/ingenic/intr.c
74
MIPS_INT_MASK_4 |
sys/arch/evbmips/ingenic/intr.c
82
MIPS_INT_MASK_4 |
sys/arch/evbmips/loongson/gdium_machdep.c
76
.bonito_mips_intr = MIPS_INT_MASK_4,
sys/arch/evbmips/loongson/loongson_intr.c
83
MIPS_INT_MASK_4,
sys/arch/evbmips/loongson/loongson_intr.c
90
MIPS_INT_MASK_4 |
sys/arch/evbmips/loongson/yeeloong_machdep.c
180
.bonito_mips_intr = MIPS_INT_MASK_4,
sys/arch/evbmips/loongson/yeeloong_machdep.c
201
.bonito_mips_intr = MIPS_INT_MASK_4,
sys/arch/evbmips/loongson/yeeloong_machdep.c
222
.bonito_mips_intr = MIPS_INT_MASK_4,
sys/arch/evbmips/sbmips/sb1250_icu.c
71
| MIPS_INT_MASK_1 | MIPS_INT_MASK_4
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
166
if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
61
| MIPS_INT_MASK_4,
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
65
| MIPS_INT_MASK_4
sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
195
if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
sys/arch/hpcmips/tx/tx39icu.c
334
if (!(ipending & MIPS_INT_MASK_4) &&
sys/arch/hpcmips/tx/tx39icu.c
345
if (ipending & MIPS_INT_MASK_4) {
sys/arch/hpcmips/tx/tx39icu.c
92
| MIPS_INT_MASK_4,
sys/arch/hpcmips/tx/tx39icu.c
95
| MIPS_INT_MASK_4,
sys/arch/mips/atheros/ar7100.c
90
MIPS_INT_MASK_4, /* MISC (UART0/1) */
sys/arch/mips/atheros/ar9344.c
377
MIPS_INT_MASK_4, /* MISC */
sys/arch/mipsco/mipsco/mips_3x30.c
124
HANDLE_INTR(SYS_INTR_FDC, MIPS_INT_MASK_4);
sys/arch/mipsco/mipsco/mips_3x30.c
68
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
sys/arch/newsmips/newsmips/news3400.c
122
if (ipending & MIPS_INT_MASK_4) {
sys/arch/newsmips/newsmips/news3400.c
229
if ((cause & MIPS_INT_MASK_4) != 0) {
sys/arch/newsmips/newsmips/news4000.c
110
if (ipending & MIPS_INT_MASK_4) {
sys/arch/newsmips/newsmips/news5000.c
131
if (ipending & MIPS_INT_MASK_4) {
sys/arch/pmax/pmax/dec_3100.c
217
if (ipending & MIPS_INT_MASK_4) {
sys/arch/pmax/pmax/dec_3maxplus.c
351
if (ipending & MIPS_INT_MASK_4)
sys/arch/pmax/pmax/dec_3min.c
325
if (ipending & MIPS_INT_MASK_4)
sys/arch/pmax/pmax/dec_5100.c
160
if (ipending & MIPS_INT_MASK_4) {
sys/arch/pmax/pmax/dec_maxine.c
340
if (ipending & MIPS_INT_MASK_4)
sys/arch/pmax/pmax/interrupt.c
97
MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
sys/arch/sbmips/sbmips/sb1250_icu.c
71
| MIPS_INT_MASK_1 | MIPS_INT_MASK_4
sys/arch/sgimips/sgimips/cpu.c
127
if (pending & MIPS_INT_MASK_4) {
sys/arch/sgimips/sgimips/machdep.c
136
[IPL_SCHED] = MIPS_INT_MASK_4|MIPS_INT_MASK_2|
sys/arch/sgimips/sgimips/machdep.c
145
[IPL_SCHED] = MIPS_INT_MASK_4|MIPS_INT_MASK_3|MIPS_INT_MASK_2|