Symbol: AR_SETBITS
sys/dev/ic/arn5008.c
1798
AR_SETBITS(sc, AR_PHY_CCK_DETECT,
sys/dev/ic/arn5008.c
1828
AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
sys/dev/ic/arn5008.c
1944
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
sys/dev/ic/arn5008.c
1968
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
sys/dev/ic/arn5008.c
1969
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
sys/dev/ic/arn5008.c
1970
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
sys/dev/ic/arn5008.c
1979
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
sys/dev/ic/arn5008.c
2003
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, AR_PHY_TIMING_CTRL4_DO_CAL);
sys/dev/ic/arn5008.c
2085
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
sys/dev/ic/arn5008.c
2136
AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
sys/dev/ic/arn5008.c
2191
AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
sys/dev/ic/arn5008.c
2461
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
sys/dev/ic/arn5008.c
2744
AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
sys/dev/ic/arn5008.c
410
AR_SETBITS(sc, AR7010_GPIO_OE, 1 << pin);
sys/dev/ic/arn5008.c
456
AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
sys/dev/ic/arn5008.c
461
AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
sys/dev/ic/arn5008.c
463
AR_SETBITS(sc, AR_GPIO_INTR_POL,
sys/dev/ic/arn5416.c
331
AR_SETBITS(sc, AR_PHY_AGC_CONTROL,
sys/dev/ic/arn5416.c
335
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
sys/dev/ic/arn5416.c
346
AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
sys/dev/ic/arn5416.c
698
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
sys/dev/ic/arn9003.c
1972
AR_SETBITS(sc, AR_PHY_CCK_DETECT,
sys/dev/ic/arn9003.c
2000
AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
sys/dev/ic/arn9003.c
2129
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
sys/dev/ic/arn9003.c
2153
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
sys/dev/ic/arn9003.c
2154
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
sys/dev/ic/arn9003.c
2155
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
sys/dev/ic/arn9003.c
2163
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
sys/dev/ic/arn9003.c
2192
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
sys/dev/ic/arn9003.c
2221
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
sys/dev/ic/arn9003.c
2225
AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
sys/dev/ic/arn9003.c
2227
AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
sys/dev/ic/arn9003.c
2302
AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
sys/dev/ic/arn9003.c
2444
AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL);
sys/dev/ic/arn9003.c
2470
AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY,
sys/dev/ic/arn9003.c
2496
AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3,
sys/dev/ic/arn9003.c
2498
AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
sys/dev/ic/arn9003.c
2547
AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i),
sys/dev/ic/arn9003.c
3042
AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain),
sys/dev/ic/arn9003.c
3076
AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ);
sys/dev/ic/arn9003.c
3286
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
sys/dev/ic/arn9003.c
3414
AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
sys/dev/ic/arn9003.c
586
AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
sys/dev/ic/arn9003.c
591
AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
sys/dev/ic/arn9003.c
593
AR_SETBITS(sc, AR_GPIO_INTR_POL,
sys/dev/ic/arn9280.c
495
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
sys/dev/ic/arn9285.c
426
AR_SETBITS(sc, AR_PHY(2), 1 << 27);
sys/dev/ic/arn9285.c
428
AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
sys/dev/ic/arn9285.c
429
AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
sys/dev/ic/arn9285.c
430
AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
sys/dev/ic/arn9285.c
431
AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
sys/dev/ic/arn9285.c
465
AR_SETBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS(i));
sys/dev/ic/arn9285.c
469
AR_SETBITS(sc, AR9285_AN_RF2G6,
sys/dev/ic/arn9285.c
478
AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
sys/dev/ic/arn9285.c
482
AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
sys/dev/ic/arn9285.c
488
AR_SETBITS(sc, AR9285_AN_RF2G6, 1);
sys/dev/ic/arn9285.c
524
AR_SETBITS(sc, AR_PHY(2), 1 << 27);
sys/dev/ic/arn9285.c
526
AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
sys/dev/ic/arn9285.c
527
AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
sys/dev/ic/arn9285.c
528
AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
sys/dev/ic/arn9285.c
529
AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
sys/dev/ic/arn9285.c
571
AR_SETBITS(sc, AR9285_AN_RF2G6, 1);
sys/dev/ic/arn9285.c
593
AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
sys/dev/ic/arn9285.c
596
AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
sys/dev/ic/arn9285.c
597
AR_SETBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
sys/dev/ic/arn9285.c
601
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
sys/dev/ic/arn9285.c
616
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
sys/dev/ic/arn9285.c
617
AR_SETBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
sys/dev/ic/arn9285.c
618
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
sys/dev/ic/arn9285.c
627
AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
sys/dev/ic/arn9287.c
546
AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
sys/dev/ic/arn9287.c
597
AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
sys/dev/ic/arn9287.c
599
AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
sys/dev/ic/arn9287.c
602
AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
sys/dev/ic/arn9287.c
623
AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER,
sys/dev/ic/arn9287.c
630
AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
sys/dev/ic/arn9380.c
284
AR_SETBITS(sc, AR_PHY_65NM_CH0_SYNTH4,
sys/dev/ic/arn9380.c
465
AR_SETBITS(sc, AR_RTC_REG_CONTROL1,
sys/dev/ic/arn9380.c
469
AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD);
sys/dev/ic/arn9380.c
653
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
sys/dev/ic/arn9380.c
669
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
sys/dev/ic/arn9380.c
685
AR_SETBITS(sc, AR_PHY_TIMING4,
sys/dev/ic/athn.c
1189
AR_SETBITS(sc, sc->sc_gpio_input_en_off,
sys/dev/ic/athn.c
1200
AR_SETBITS(sc, sc->sc_gpio_input_en_off,
sys/dev/ic/athn.c
1238
AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE);
sys/dev/ic/athn.c
1721
AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
sys/dev/ic/athn.c
1797
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
sys/dev/ic/athn.c
1860
AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
sys/dev/ic/athn.c
1864
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
sys/dev/ic/athn.c
1928
AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON),
sys/dev/ic/athn.c
1931
AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON),
sys/dev/ic/athn.c
1942
AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB),
sys/dev/ic/athn.c
1945
AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB),
sys/dev/ic/athn.c
1950
AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL),
sys/dev/ic/athn.c
1954
AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),
sys/dev/ic/athn.c
2027
AR_SETBITS(sc, AR_TIMER_MODE,
sys/dev/ic/athn.c
2087
AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
sys/dev/ic/athn.c
2262
AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE);
sys/dev/ic/athn.c
2286
AR_SETBITS(sc, AR_PCU_MISC_MODE2,
sys/dev/ic/athn.c
2341
AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
sys/dev/ic/athn.c
2357
AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA);
sys/dev/ic/athn.c
2363
AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
sys/dev/ic/athn.c
2976
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
sys/dev/ic/athn.c
515
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS);
sys/dev/ic/athn.c
533
AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
sys/dev/ic/athn.c
749
AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
sys/dev/ic/athn.c
759
AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
sys/dev/ic/athn.c
775
AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
sys/dev/ic/athn.c
857
AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
sys/dev/ic/athn.c
966
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);