AR_READ
reg = AR_READ(sc, AR_ISR_S0_S);
reg = AR_READ(sc, AR_ISR_S1_S);
intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
(AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
intr = AR_READ(sc, AR_ISR);
sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
uint32_t intr2 = AR_READ(sc, AR_ISR_S2);
intr = AR_READ(sc, AR_ISR_RAC);
intr5 = AR_READ(sc, AR_ISR_S5_S);
(void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
(void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
synth_delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY);
if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN)
phy = AR_READ(sc, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO;
reg = AR_READ(sc, AR_PHY_TIMING3);
reg = AR_READ(sc, AR_PHY_HALFGI);
reg = AR_READ(sc, AR_PHY_CCA(i));
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
reg = AR_READ(sc, AR_PHY_CCA(i));
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
if (!(AR_READ(sc, AR_PHY_TIMING_CTRL4_0) &
cal->pwr_meas_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
cal->pwr_meas_q += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
(int32_t)AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));
cal->pwr_meas_odd_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
cal->pwr_meas_odd_q += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
cal->pwr_meas_odd_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
cal->pwr_meas_odd_q += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
reg = AR_READ(sc, AR_PCU_MISC_MODE2);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = AR_READ(sc, AR_PHY_AGC_CTL1);
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
reg = AR_READ(sc, AR_PHY_SFCORR);
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
reg = AR_READ(sc, AR_PHY_SFCORR);
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
reg = AR_READ(sc, AR_PHY_TIMING5);
return !((AR_READ(sc, AR7010_GPIO_IN) >> pin) & 1);
return (AR_READ(sc, AR_GPIO_IN_OUT) >> (sc->sc_ngpiopins + pin)) & 1;
reg = AR_READ(sc, AR7010_GPIO_OUT);
reg = AR_READ(sc, AR_GPIO_IN_OUT);
reg = AR_READ(sc, AR_GPIO_OE_OUT);
reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
reg = AR_READ(sc, AR_GPIO_OE_OUT);
reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
tsf = AR_READ(sc, AR_TSF_U32);
tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32);
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = AR_READ(sc, AR_PHY_SETTLING);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = AR_READ(sc, AR_PHY_RF_CTL3);
reg = AR_READ(sc, AR_PHY_CCA(0));
reg = AR_READ(sc, AR_PHY_EXT_CCA(0));
reg = AR_READ(sc, AR_PHY_RF_CTL2);
reg = AR_READ(sc, AR_PHY_SETTLING);
if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
reg = AR_READ(sc, AR_PHY_TPCRG1);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff;
intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
(AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
intr = AR_READ(sc, AR_ISR);
sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
uint32_t intr2 = AR_READ(sc, AR_ISR_S2);
intr = AR_READ(sc, AR_ISR_RAC);
uint32_t intr5 = AR_READ(sc, AR_ISR_S5_S);
(void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
synth_delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY);
if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN)
phy = AR_READ(sc, AR_PHY_GEN_CTRL);
reg = AR_READ(sc, AR_PHY_TIMING3);
reg = AR_READ(sc, AR_PHY_SGI_DELTA);
reg = AR_READ(sc, AR_PHY_CCA(i));
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
reg = AR_READ(sc, AR_PHY_CCA(i));
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE)
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
reg = AR_READ(sc, AR_PHY_TIMING4);
if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i));
cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i));
(int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i));
reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD)
reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i));
reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i));
reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM);
reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM);
reg = AR_READ(sc, AR_PHY_PAPRD_HT40);
reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i));
reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i));
reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1);
reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3);
reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4);
reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i));
reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i));
sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5),
scale = MS(AR_READ(sc, AR_PHY_TPC_12),
reg = AR_READ(sc, AR_PHY_TPC_19);
reg = AR_READ(sc, AR_PHY_TPC_18);
reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4);
delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)),
reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN);
reg = AR_READ(sc, AR_PHY_TPC_1);
reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain));
reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain));
if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) &
lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i));
hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i));
reg = AR_READ(sc, AR_OTP_BASE(addr));
reg = AR_READ(sc, AR_OTP_STATUS);
*val = AR_READ(sc, AR_OTP_READ_DATA);
reg = AR_READ(sc, AR_PCU_MISC_MODE2);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = AR_READ(sc, AR_PHY_AGC);
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
reg = AR_READ(sc, AR_PHY_SFCORR);
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
reg = AR_READ(sc, AR_PHY_SFCORR);
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = AR_READ(sc, AR_PHY_TIMING5);
return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) &
reg = AR_READ(sc, AR_GPIO_IN_OUT);
reg = AR_READ(sc, AR_GPIO_OE_OUT);
reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
reg = AR_READ(sc, AR_GPIO_OE_OUT);
reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
reg = AR_READ(sc, AR_RXBP_THRESH);
tsf = AR_READ(sc, AR_TSF_U32);
tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32);
phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
reg = AR_READ(sc, AR_AN_SYNTH9);
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
reg = AR_READ(sc, AR_AN_RF2G1_CH0);
reg = AR_READ(sc, AR_AN_RF2G1_CH1);
reg = AR_READ(sc, AR_AN_RF5G1_CH0);
reg = AR_READ(sc, AR_AN_RF5G1_CH1);
reg = AR_READ(sc, AR_AN_TOP2);
reg = AR_READ(sc, AR_PHY_XPA_CFG);
reg = AR_READ(sc, AR_PHY_SETTLING);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = AR_READ(sc, AR_PHY_RF_CTL3);
reg = AR_READ(sc, AR_PHY_CCA(0));
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
reg = AR_READ(sc, AR_PHY_RF_CTL2);
reg = AR_READ(sc, AR_PHY_SETTLING);
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
reg = AR_READ(sc, AR_AN_TOP1);
reg = AR_READ(sc, AR_PHY_FRAME_CTL);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) { /* XE rev. */
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ);
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = AR_READ(sc, AR_PHY_RXGAIN);
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL);
reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */
reg = AR_READ(sc, AR9285_AN_RF2G3);
reg = AR_READ(sc, AR9285_AN_RF2G4);
reg = AR_READ(sc, AR9285_AN_RF2G3);
reg = AR_READ(sc, AR9285_AN_RF2G4);
reg = AR_READ(sc, AR_PHY_SETTLING);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = AR_READ(sc, AR_PHY_RF_CTL3);
reg = AR_READ(sc, AR_PHY_CCA(0));
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
reg = AR_READ(sc, AR_PHY_RF_CTL2);
reg = AR_READ(sc, AR_PHY_SETTLING);
svg[i] = AR_READ(sc, regs[i]);
reg = AR_READ(sc, AR9285_AN_RF2G8);
reg = AR_READ(sc, AR9285_AN_RF2G7);
reg = AR_READ(sc, AR9285_AN_RF2G6);
if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) {
if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9)
reg = AR_READ(sc, AR9285_AN_RF2G6);
svg[i] = AR_READ(sc, regs[i]);
reg = AR_READ(sc, AR9285_AN_RF2G8);
reg = AR_READ(sc, AR9285_AN_RF2G7);
reg = rf2g3_svg = AR_READ(sc, AR9285_AN_RF2G3);
reg = AR_READ(sc, AR9285_AN_RF2G6);
if (!(AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9))
if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
reg = AR_READ(sc, AR_PHY_CLC_TBL(i));
rf2g5_svg = reg = AR_READ(sc, AR9285_AN_RF2G5);
if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) /* XE rev. */
overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
reg = AR_READ(sc, AR_PHY_TPCRG1);
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
reg = AR_READ(sc, AR_PHY_SETTLING);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = AR_READ(sc, AR_PHY_RF_CTL3);
reg = AR_READ(sc, AR_PHY_CCA(0));
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
reg = AR_READ(sc, AR9287_AN_RF2G3_CH0);
reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);
reg = AR_READ(sc, AR_PHY_RF_CTL2);
reg = AR_READ(sc, AR9287_AN_TOP2);
overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
reg = AR_READ(sc, AR_PHY_TPCRG1);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset);
reg = AR_READ(sc, AR9287_AN_TXPC0);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);
reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);
reg = AR_READ(sc, AR_AHB_MODE);
reg = AR_READ(sc, AR9485_PHY_65NM_CH0_TOP2);
reg = AR_READ(sc, AR_PHY_65NM_CH0_TOP);
reg = AR_READ(sc, AR_PHY_65NM_CH0_THERM);
reg = AR_READ(sc, AR_PHY_SWITCH_COM);
reg = AR_READ(sc, AR_PHY_SWITCH_COM_2);
reg = AR_READ(sc, AR_PHY_SWITCH_CHAIN(i));
reg = AR_READ(sc, AR_PHY_MC_GAIN_CTRL);
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS1);
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS2);
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS4);
reg = AR_READ(sc, AR_PHY_EXT_ATTEN_CTL(i));
reg = AR_READ(sc, AR9485_PHY_CH0_XTAL);
if (AR_READ(sc, addr) == val)
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
reg = AR_READ(sc, AR_PHY_TIMING11);
reg = AR_READ(sc, AR_PHY_SPUR_REG);
if (AR_READ(sc, AR_PHY_GEN_CTRL) & AR_PHY_GC_DYN2040_PRI_CH)
reg = AR_READ(sc, AR_PHY_GEN_CTRL);
reg = AR_READ(sc, AR_PHY_TIMING11);
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
reg = AR_READ(sc, AR_PHY_SPUR_REG);
if (AR_READ(sc, AR_PHY_MODE) & AR_PHY_MODE_DYNAMIC)
reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK);
reg = AR_READ(sc, AR_PHY_SPUR_MASK_A);
reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK);
reg = AR_READ(sc, AR_PHY_TPC_11_B(i));
reg = AR_READ(sc, AR_PHY_TPC_6_B(i));
reg = AR_READ(sc, AR_PHY_TPC_19);
reg = AR_READ(sc, AR_PHY_TPC_18);
#define ar9485_pmu_read AR_READ
reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
reg = AR_READ(sc, AR_GPIO_PDPU);
txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */
rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */
cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */
phy1 = AR_READ(sc, AR_PHY_ERR_1);
phy2 = AR_READ(sc, AR_PHY_ERR_2);
reg = AR_READ(sc, AR_TXCFG);
reg = AR_READ(sc, AR_RXCFG);
reg = AR_READ(sc, AR_TXCFG);
if (!(AR_READ(sc, AR_CR) & AR_CR_RXE))
if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0)
return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 ||
(AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0;
tsflo = AR_READ(sc, AR_TSF_L32) / 1024;
if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo)
tsfhi = AR_READ(sc, AR_TSF_U32);
tsflo = AR_READ(sc, AR_TSF_L32);
reg = AR_READ(sc, AR_RSSI_THR);
reg = AR_READ(sc, AR_STA_ID1);
reg = AR_READ(sc, AR_STA_ID1);
reg = AR_READ(sc, AR_STA_ID1);
mask2 = AR_READ(sc, AR_IMR_S2);
(void)AR_READ(sc, AR_IER);
(void)AR_READ(sc, AR_INTR_ASYNC_ENABLE);
(void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0)
sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M |
tsfhi = AR_READ(sc, AR_TSF_U32);
tsflo = AR_READ(sc, AR_TSF_L32);
reg = AR_READ(sc, AR_AES_MUTE_MASK1);
reg = AR_READ(sc, AR_RX_FILTER);
reg = AR_READ(sc, AR_PHY_ERR);
reg = AR_READ(sc, AR_SREV);
if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
if (AR_READ(sc, AR_INTR_SYNC_CAUSE) &
if (!(AR_READ(sc, AR_RTC_RC) &
if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))
AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))
reg = AR_READ(sc, AR_RX_FILTER);