LCR_8BITS
CSR_WRITE(com_port, com_lctl, LCR_PNONE | LCR_8BITS);
OUTB(com_cfcr, LCR_8BITS);
dnkbd_init(sc, 1200, LCR_8BITS | LCR_PEVEN | LCR_PENAB);
*((volatile u_int8_t *)(addr + com_cfcr)) = LCR_8BITS;
if ((ubtmp1 != LCR_8BITS) || ((ubtmp2 & 0x38) != 0)) {
REGWRITE_1(VR4181_SIU_ADDR, com_lcr, LCR_8BITS);
outb(combase + com_cfcr, LCR_8BITS);
com0addr[com_lctl] = htole32(LCR_8BITS); /* XXX */
com0addr[com_lctl] = htobe32(LCR_8BITS); /* XXX */
CSR_WRITE(com_port, com_lctl, LCR_PNONE | LCR_8BITS);
bus_space_write_1(&genppc_isa_io_space_tag, comh, com_cfcr, LCR_8BITS);
init_uart(uart2base, 9600, LCR_8BITS | LCR_PEVEN);
init_uart(uart2base, 9600, LCR_8BITS | LCR_PNONE);
init_uart(uart2base, 19200, LCR_8BITS | LCR_PNONE);
init_uart(uart2base, 9600, LCR_8BITS | LCR_PNONE);
init_uart(uart2base, 9600, LCR_8BITS | LCR_PNONE);
init_uart(uart2base, 38400, LCR_8BITS | LCR_PEVEN);
SET(lcr, LCR_8BITS);
CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS);
if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) ||