Symbol: sci_csr
sys/arch/amiga/dev/empsc.c
140
sc->sci_csr = rp + 0x50;
sys/arch/amiga/dev/empsc.c
187
if ((*dev->sci_csr & SCI_CSR_INT) == 0)
sys/arch/amiga/dev/ivsc.c
145
sc->sci_csr = rp + 10;
sys/arch/amiga/dev/ivsc.c
198
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/ivsc.c
211
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/ivsc.c
213
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/ivsc.c
248
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/ivsc.c
250
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/ivsc.c
281
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/ivsc.c
295
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/ivsc.c
297
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/ivsc.c
315
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
sys/arch/amiga/dev/ivsc.c
329
if ((*dev->sci_csr & SCI_CSR_INT) == 0)
sys/arch/amiga/dev/mlhsc.c
138
sc->sci_csr = rp + 11;
sys/arch/amiga/dev/mlhsc.c
185
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/mlhsc.c
201
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/mlhsc.c
203
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/mlhsc.c
237
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/mlhsc.c
239
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/mlhsc.c
271
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/mlhsc.c
288
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/mlhsc.c
290
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/mlhsc.c
316
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/mlhsc.c
318
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/mlhsc.c
336
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
sys/arch/amiga/dev/otgsc.c
140
sc->sci_csr = rp + 0x50;
sys/arch/amiga/dev/otgsc.c
191
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/otgsc.c
204
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/otgsc.c
206
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/otgsc.c
237
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/otgsc.c
251
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/otgsc.c
253
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/otgsc.c
271
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
sys/arch/amiga/dev/otgsc.c
285
if ((*dev->sci_csr & SCI_CSR_INT) == 0)
sys/arch/amiga/dev/sci.c
270
device_xname(dev->sc_dev), where, *dev->sci_csr, *dev->sci_bus_csr);
sys/arch/amiga/dev/sci.c
432
if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
sys/arch/amiga/dev/sci.c
479
if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
sys/arch/amiga/dev/scireg.h
62
volatile unsigned char sci_csr; /* r: Status */
sys/arch/amiga/dev/scireg.h
63
#define sci_dma_send sci_csr /* w: Start DMA send data */
sys/arch/amiga/dev/scivar.h
55
volatile u_char *sci_csr; /* r: Status */
sys/arch/amiga/dev/wstsc.c
152
sc->sci_csr = rp + 10;
sys/arch/amiga/dev/wstsc.c
209
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/wstsc.c
223
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/wstsc.c
225
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/wstsc.c
260
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/wstsc.c
262
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/wstsc.c
293
volatile register u_char *sci_csr = dev->sci_csr;
sys/arch/amiga/dev/wstsc.c
307
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/wstsc.c
309
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/wstsc.c
327
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
sys/arch/amiga/dev/wstsc.c
343
volatile register u_char *sci_csr = dev->sci_csr + 0x10;
sys/arch/amiga/dev/wstsc.c
360
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/wstsc.c
362
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/wstsc.c
375
while (!(*sci_csr & SCI_CSR_DREQ))
sys/arch/amiga/dev/wstsc.c
393
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/wstsc.c
395
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/wstsc.c
408
while (!(*sci_csr & SCI_CSR_DREQ))
sys/arch/amiga/dev/wstsc.c
452
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/wstsc.c
454
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/wstsc.c
486
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
sys/arch/amiga/dev/wstsc.c
488
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
sys/arch/amiga/dev/wstsc.c
517
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
sys/arch/amiga/dev/wstsc.c
535
if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0)
sys/arch/mac68k/dev/sbc.c
134
if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
sys/arch/mac68k/dev/sbc.c
139
if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0)
sys/arch/mac68k/dev/sbc.c
157
if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
sys/arch/mac68k/dev/sbc.c
177
if (*ncr_sc->sci_csr & SCI_CSR_INT) {
sys/arch/mac68k/dev/sbc.c
185
if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT)
sys/arch/mac68k/dev/sbc.c
206
u_int8_t csr = *ncr_sc->sci_csr;
sys/arch/mac68k/dev/sbc.c
408
if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) {
sys/arch/mac68k/dev/sbc.c
571
if (*ncr_sc->sci_csr & SCI_CSR_ACK)
sys/arch/mac68k/dev/sbc.c
640
device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr,
sys/arch/mac68k/dev/sbc.c
829
device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr,
sys/arch/mac68k/include/scsi_5380.h
58
volatile unsigned char sci_csr; /* r: Status */
sys/arch/mac68k/include/scsi_5380.h
59
#define sci_dma_send sci_csr /* w: Start DMA send data */
sys/dev/ic/ncr5380sbc.c
1614
if (NCR5380_READ(sc, sci_csr) & SCI_CSR_PERR) {
sys/dev/ic/ncr5380sbc.c
2318
if (NCR5380_READ(sc, sci_csr) & SCI_CSR_PERR) {
sys/dev/podulebus/hcsc.c
234
if ((NCR5380_READ(sc,sci_csr) &
sys/dev/podulebus/hcsc.c
239
if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
sys/dev/podulebus/hcsc.c
256
(NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
sys/dev/podulebus/hcsc.c
355
if ((NCR5380_READ(ncr_sc, sci_csr)
sys/dev/podulebus/oak.c
232
status = NCR5380_READ(sc, sci_csr);
sys/dev/podulebus/oak.c
271
(NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
sys/dev/podulebus/oak.c
375
if ((NCR5380_READ(ncr_sc, sci_csr)