sci_bus_csr
sc->sci_bus_csr = rp + 0x40;
sc->sci_bus_csr = rp + 8;
QPRINTF(("ivsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
QPRINTF(("ivsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
sc->sci_bus_csr = rp + 9;
csr = *dev->sci_bus_csr;
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
csr = *dev->sci_bus_csr;
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
sc->sci_bus_csr = rp + 0x40;
QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
device_xname(dev->sc_dev), where, *dev->sci_csr, *dev->sci_bus_csr);
if ((*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
(*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
(*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)))
while ((*dev->sci_bus_csr & SCI_BUS_BSY) == 0) {
csr = *dev->sci_bus_csr;
csr = *dev->sci_bus_csr;
while (*dev->sci_bus_csr & SCI_BUS_REQ);
volatile register u_char *sci_bus_csr = dev->sci_bus_csr;
csr = *sci_bus_csr;
csr = *sci_bus_csr;
csr = *sci_bus_csr;
while (*sci_bus_csr & SCI_BUS_REQ);
while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) == SCI_BUS_BSY);
QPRINTF((">CSR:%02x<", *dev->sci_bus_csr));
if ((*dev->sci_bus_csr & SCI_BUS_REQ) == 0) {
phase = SCI_PHASE(*dev->sci_bus_csr);
while (*dev->sci_bus_csr & SCI_BUS_BSY);
while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) ==
QPRINTF((">CSR:%02x<", *dev->sci_bus_csr));
if ((*dev->sci_bus_csr & SCI_BUS_REQ) == 0) {
phase = SCI_PHASE(*dev->sci_bus_csr);
while (*dev->sci_bus_csr & SCI_BUS_BSY);
volatile unsigned char sci_bus_csr; /* r: Bus Status */
#define sci_sel_enb sci_bus_csr /* w: Select enable */
volatile u_char *sci_bus_csr; /* r: Bus Status */
sc->sci_bus_csr = rp + 8;
QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
len, *dev->sci_bus_csr, wait);
volatile register u_char *sci_bus_csr = dev->sci_bus_csr;
QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
while (!(*sci_bus_csr & SCI_BUS_REQ))
if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
while (!(*sci_bus_csr & SCI_BUS_REQ))
if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
&& ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) {
u_int8_t bus_csr = *ncr_sc->sci_bus_csr;
*ncr_sc->sci_bus_csr);
*ncr_sc->sci_bus_csr);
volatile unsigned char sci_bus_csr; /* r: Bus Status */
#define sci_sel_enb sci_bus_csr /* w: Select enable */
bus = NCR5380_READ(sc, sci_bus_csr);
bus = NCR5380_READ(sc, sci_bus_csr);
bus = NCR5380_READ(sc, sci_bus_csr);
phase = SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr));
if (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY)
if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY) == 0) {
phase = SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr));
phase = SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr));
if (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) {
if (SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr)) == phase) {
if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0) {
if (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ)
phase = SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr));
if (SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr)) != phase)
if (SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr)) != phase)
#define SCI_BUSY(sc) (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY)
if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 ||
if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 ||