Cardbus_conf_write
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, tag, PCI_BHLC_REG, ct->ct_bhlc);
Cardbus_conf_write(ct, csc->cc_tag, csc->cc_reg, csc->cc_base);
Cardbus_conf_write(ct, csc->cc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->cc_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG,
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG,
Cardbus_conf_write(ct, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val);
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->csc_tag, ATHN_PCI_MMBA, csc->csc_bar_val);
Cardbus_conf_write(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->csc_tag, 0x40, reg & ~0xff00);
Cardbus_conf_write(ct, csc->csc_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg,
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, csr);
Cardbus_conf_write(ct, csc->csc_tag, BWI_PCIR_BAR, csc->csc_bar_val);
Cardbus_conf_write(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(csc->csc_ct, csc->csc_tag, reg, val);
Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val);
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(csc->ct, tag,
Cardbus_conf_write(csc->ct, tag,
Cardbus_conf_write(csc->ct, tag, PCI_COMMAND_STATUS_REG, command);
Cardbus_conf_write(ct, csc->sc_tag, PCI_BAR0, csc->sc_bar1_val);
Cardbus_conf_write(ct, csc->sc_tag, PCI_BAR1, csc->sc_bar2_val);
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag, PCI_BAR0, csc->sc_bar_val);
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val);
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag,
Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val);
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, tag, PCI_BHLC_REG, bhlc);
Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG, csr);
Cardbus_conf_write(ct, csc->sc_tag, TULIP_PCI_CFDA,
Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val);
Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG,
Cardbus_conf_write(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG,
Cardbus_conf_write(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG,
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG,
Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR0, base);
Cardbus_conf_write(ct, ca->ca_tag,
Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR1, base);
Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR0, 0);
Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR1, 0);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, csr);
Cardbus_conf_write(ct, ctag, SIISATA_CARDBUS_BAR0, 0);
Cardbus_conf_write(ct, ctag, SIISATA_CARDBUS_BAR1, 0);
Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG,
Cardbus_conf_write(ct, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN);