Cardbus_conf_read
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
cis_ptr = Cardbus_conf_read(csc->cc_ct, csc->cc_tag, CARDBUS_CIS_REG);
reg = Cardbus_conf_read(ct, csc->cc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->cc_tag, PCI_BHLC_REG);
csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag,
reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->csc_tag, 0x40);
reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_BHLC_REG);
Cardbus_conf_read(ct, csc->sc_tag, 0x80));
csr = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG);
return Cardbus_conf_read(csc->csc_ct, csc->csc_tag, reg);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);
command = Cardbus_conf_read(csc->ct, tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
command = Cardbus_conf_read(ct, csc->sc_tag,
iobase = Cardbus_conf_read(ct, csc->sc_tag,
membase = Cardbus_conf_read(ct, csc->sc_tag,
irq = Cardbus_conf_read(ct, csc->sc_tag,
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);
command = Cardbus_conf_read(ct, csc->sc_tag,
iobase = Cardbus_conf_read(ct, csc->sc_tag,
membase = Cardbus_conf_read(ct, csc->sc_tag,
irq = Cardbus_conf_read(ct, csc->sc_tag,
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);
Cardbus_conf_read(ct, csc->sc_tag, 0x80)));
bhlc = Cardbus_conf_read(ct, tag, PCI_BHLC_REG);
csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag, 0x80);
reg = Cardbus_conf_read(ct, csc->sc_tag, TULIP_PCI_CFDA);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_BUS_REG);
busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG);
busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_BUS_REG);
slotinfo = Cardbus_conf_read(ct, ca->ca_tag, SDHC_PCI_CONF_SLOT_INFO);
csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
base = PCI_MAPREG_MEM_ADDR(Cardbus_conf_read(ct, ca->ca_tag, SIISATA_CARDBUS_BAR0));
base = PCI_MAPREG_MEM_ADDR(Cardbus_conf_read(ct, ca->ca_tag,
csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG);
switch(Cardbus_conf_read(ct, tag, PCI_USBREV) & PCI_USBREV_MASK) {