outw
#define out16(a,v) outw(a,v)
void outw(int, u_short);
outw(0x3C4, 0x0120); /* disable video */
outw(0x3C4, 0x0100); /* re-enable video */
outw(0x3C4, 0x0612); /* unlock ext regs */
outw(0x3C4, 0x0700); /* reset ext sequence mode */
outw(0x3C4, 0x0120); /* disable video */
outw(0x3C4, 0x0100); /* re-enable video */
outw(0x3C4, 0x0120); /* disable video */
outw(0x3C4, 0x0100); /* re-enable video */
outw(0x3C4, 0x0001); /* reset sequencer */
outw(0x3C4, 0x0204); /* write to plane 2 */
outw(0x3C4, 0x0406); /* enable plane graphics */
outw(0x3C4, 0x0003); /* reset sequencer */
outw(0x3CE, 0x0402); /* read plane 2 */
outw(0x3CE, 0x0500); /* write mode 0, read mode 0 */
outw(0x3CE, 0x0605); /* set graphics mode */
void outw(unsigned, uint16_t);
#define acpi_md_OsOut16(x, v) outw((x), (v))
outw((h) + (o), (v)); \
outw(__port, *__src); \
outw(addr, v);
outw(addr, v);
outw(addr2, inw(addr1));
outw(addr2, inw(addr1));
outw(port, *buf++);
#define out16(a,v) outw(a,v)
void outw(int, u_int16_t);
outw(VGA_SR_PORT, 0x0612); /* unlock ext regs */
outw(VGA_SR_PORT, 0x0700); /* reset ext sequence mode */
outw(VGA_GR_PORT, 0x0f05); /* unlock registers */
outw(VGA_SR_PORT, 0x0648);
outw(VGA_CR_PORT, 0x2985);
outw(VGA_CR_PORT, 0x34a6);
outw(VGA_SR_PORT, 0x1400);
outw(VGA_CR_PORT, 0x0250);
outw(VGA_CR_PORT, 0x07ba);
outw(VGA_CR_PORT, 0x0900);
outw(VGA_CR_PORT, 0x15e7);
outw(VGA_CR_PORT, 0x2a95);
outw(VGA_CR_PORT, 0x34a0);
outw(VGA_SR_PORT, 0x0120); /* disable video */
outw(VGA_SR_PORT, 0x0100); /* re-enable video */
outw(0x3C4, 0x0001); /* reset sequencer */
outw(0x3C4, 0x0204); /* write to plane 2 */
outw(0x3C4, 0x0406); /* enable plane graphics */
outw(0x3C4, 0x0003); /* reset sequencer */
outw(0x3CE, 0x0402); /* read plane 2 */
outw(0x3CE, 0x0500); /* write mode 0, read mode 0 */
outw(0x3CE, 0x0605); /* set graphics mode */
outw(VGA_CR_PORT, 0x3848);
outw(VGA_CR_PORT, 0x39a5);
outw(VGA_SR_PORT, 0x0806);
outw(VGA_SR_PORT, 0x1041);
outw(VGA_SR_PORT, 0x1128);
outw(VGA_CR_PORT, 0x4000);
outw(VGA_CR_PORT, 0x3100);
outw(VGA_CR_PORT, 0x3a05);
outw(VGA_CR_PORT, 0x6688);
outw(VGA_CR_PORT, 0x5800); /* disable linear addressing */
outw(VGA_CR_PORT, 0x4500); /* disable H/W cursor */
outw(VGA_SR_PORT, 0x5410); /* enable auto-centering */
outw(VGA_SR_PORT, 0x561f);
outw(VGA_SR_PORT, 0x1b80); /* lock DCLK selection */
outw(VGA_CR_PORT, 0x3900); /* lock S3 registers */
outw(VGA_CR_PORT, 0x3800);
void outw(int, u_int16_t);
#define ASIC_OUTW(x, b) outw(ASIC_PORT(x), (b))
#define acpi_md_OsOut16(x, v) outw((x), (v))
void outw(unsigned, uint16_t);
outw(PCI_MODE1_ADDRESS_REG + 2, 0);
outw(addr, v);
outw(addr, v);
outw(addr2, inw(addr1));
outw(addr2, inw(addr1));
outw(port, val);
outw(XEN_MAGIC_IOPORT,