out32
out32(arc_bus_io.bs_vbase + C_JAZZ_EISA_TODCLOCK_AS, as | reg);
out32(arc_bus_io.bs_vbase + C_JAZZ_EISA_TODCLOCK_AS, as | reg);
out32(R4030_SYS_IT_VALUE, interval - 1);
out32(R4030_SYS_EXT_IMASK, cpu_int_mask);
out32(R4030_SYS_EXT_IMASK, cpu_int_mask & (~MIPS_INT_MASK_4 >> 10));
out32(R4030_SYS_EXT_IMASK, 0x00);
out32(RD94_SYS_EXT_IMASK, 0);
out32(RD94_SYS_EXT_IMASK, cpu_int_mask & (~MIPS_INT_MASK_3 >> 10));
out32(RD94_SYS_IT_VALUE, interval - 1);
out32(RD94_SYS_EXT_IMASK, cpu_int_mask);
out32(RD94_SYS_EXT_IMASK, 0);
out32(RD94_SYS_PCI_INTMASK, 0xf);
out32(RD94_SYS_PCI_CONFADDR, tag | reg);
out32(RD94_SYS_PCI_CONFADDR, 0);
out32(RD94_SYS_PCI_CONFADDR, tag | reg);
out32(RD94_SYS_PCI_CONFDATA, data);
out32(RD94_SYS_PCI_CONFADDR, 0);
out32(RD94_SYS_PCI_INTMASK, mask);
out32(RD94_SYS_PCI_INTMASK, mask);
goto out32;
goto out32;
out32:
out32(HW_GPIOB_OUT, val);
out32(HW_GPIOB_OUT, val);
#define WR4(reg, val) out32(reg, val)
out32(HW_RESETS, in32(HW_RESETS) | RSTB_DSP);
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) & ~__BIT(GPIO_DI_SPIN));
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(GPIO_DI_SPIN));
out32(HW_RESETS, val & ~RSTB_IODI);
out32(HW_RESETS, val | RSTB_IODI);
out32(USB_CHICKENBITS, in32(USB_CHICKENBITS) | EHCI_INTR_ENABLE);
#define WR4(reg, val) out32(EXI_BASE + (reg), val)
out32(USB_CHICKENBITS, in32(USB_CHICKENBITS) | OHCI_INTR_ENABLE);
out32(HW_RESETS, in32(HW_RESETS) & ~RSTBINB);
out32(HW_VIDIM, __SHIFTIN(7, VIDIM_Y) |
out32(HW_VIDIM, 0);
out32(LT_GPUINDADDR, LT_GPUINDADDR_REGSPACE_GPU | reg);
out32(LT_GPUINDDATA, data);
out32(LT_GPUINDADDR, LT_GPUINDADDR_REGSPACE_GPU | reg);
out32(GLOBAL_MEM2_AVAIL_START, 0);
out32(GLOBAL_MEM2_AVAIL_END, 0);
out32(HW_AIPPROT, in32(HW_AIPPROT) | ENAHBIOPI);
out32(HW_GPIO_OWNER, in32(HW_GPIO_OWNER) | __BIT(GPIO_SHUTDOWN));
out32(HW_GPIO_OWNER, in32(HW_GPIO_OWNER) | __BIT(GPIO_DI_SPIN));
out32(HW_COMPAT, in32(HW_COMPAT) & ~DVDVIDEO);
out32(HW_IPCPPCMSG, msg);
out32(HW_IPCPPCCTRL, HW_IPCPPCCTRL_X1);
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(GPIO_SHUTDOWN));
out32(HW_RESETS, in32(HW_RESETS) & ~RSTBINB);
#define WR4(reg, val) out32(reg, val)
out32(HW_RESETS, in32(HW_RESETS) & ~RSTBINB);
out32(EXI_CSR(gecko_chan), GECKO_CSR);
out32(EXI_DATA(gecko_chan), 0);
out32(EXI_CR(gecko_chan), GECKO_CR(2, EXI_CR_RW_READWRITE));
out32(EXI_CR(gecko_chan), GECKO_CR(4, EXI_CR_RW_READWRITE));
out32(EXI_CSR(gecko_chan), 0);
out32(EXI_CSR(gecko_chan), 0);
out32(EXI_CSR(gecko_chan), EXI_CSR_EXTINT | EXI_CSR_EXTINTMASK);
out32(SI_EXILK, 0);
out32(EXI_CSR(gecko_chan), GECKO_CSR);
out32(EXI_DATA(gecko_chan), (uint32_t)command << 16);
out32(EXI_CR(gecko_chan), GECKO_CR(2, EXI_CR_RW_READWRITE));
out32(EXI_CSR(gecko_chan), 0);
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(pin));
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) & ~__BIT(pin));
out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) | __BIT(pin));
out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) & ~__BIT(pin));
out32(HW_GPIO_INTFLAG, __BIT(pin));
out32(HW_IPC_PPCMSG,
out32(HW_IPC_PPCCTRL, in32(HW_IPC_PPCCTRL) | HW_IPC_PPCCTRL_OUT);
out32(HW_IPC_PPCMSG,
out32(sc->sc_reg + PLATINUM_REG_OFFSET_ADDR(reg), val);
out32(0xf2800000, (int)cpu_spinup_trampoline);
out32(0xf2800000, 0x100);
out32(HH_INTR_SECONDARY, ~0); /* Reset interrupt. */
out32(HH_INTR_SECONDARY, ~0);
out32(HH_INTR_SECONDARY, 0);
out32(HH_INTR_SECONDARY, ~0);
out32(HH_INTR_SECONDARY, 0);
out32(unin_reg + 0xe0, tmp);
out32(addr, val);
out32(pc->pc_addr, tag | reg); /* PCICAR: big-endian */
out32(pc->pc_addr, 0); /* clear E: restore I/O window */
out32(pc->pc_addr, tag | reg); /* PCICAR: big-endian */
out32(pc->pc_addr, 0); /* clear E: restore I/O window */