sys/arch/evbmips/gdium/machdep.c

260

mips3_sd(MIPS_PHYS_TO_KSEG1(BONITO_REGBASE + 0x158), 0xe);

sys/arch/evbmips/sbmips/rtc.c

421

#define WRITE_REG(rp, val) mips3_sd((register_t)(MIPS_PHYS_TO_KSEG1(rp)), (val))

sys/arch/evbmips/sbmips/sb1250_icu.c

94

#define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))

sys/arch/mips/cavium/octeon_cpunode.c

375

mips3_sd(cpu->cpu_pp_poke, wdog);

sys/arch/mips/cavium/octeon_cpunode.c

379

mips3_sd(cpu->cpu_wdog, wdog);

sys/arch/mips/cavium/octeon_cpunode.c

380

mips3_sd(cpu->cpu_pp_poke, wdog);

sys/arch/mips/cavium/octeon_cpunode.c

411

mips3_sd(cpu->cpu_wdog, wdog);

sys/arch/mips/cavium/octeon_cpunode.c

424

mips3_sd(cpu->cpu_pp_poke, 0);

sys/arch/mips/cavium/octeon_intr.c

297

mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

298

mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

299

mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

303

mips3_sd(cpu->cpu_mbox_clr, __BITS(31,0));

sys/arch/mips/cavium/octeon_intr.c

377

mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

384

mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

391

mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

401

mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

408

mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

440

mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

449

mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

460

mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);

sys/arch/mips/cavium/octeon_intr.c

553

mips3_sd(cpu->cpu_mbox_clr, ipi_mask);

sys/arch/mips/cavium/octeon_intr.c

609

mips3_sd(cpu->cpu_mbox_set, ipi_mask);

sys/arch/mips/cavium/octeonvar.h

288

mips3_sd(MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, address), value);

sys/arch/mips/include/locore.h

477

void mips3_sd(register_t addr, uint64_t val);

sys/arch/mips/include/locore.h

480

static inline void mips3_sd(register_t addr, uint64_t val) __unused;

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

1062

mips3_sd(h, val);

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

1077

mips3_sd(h, val);

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

1091

mips3_sd(h, val);

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

1103

mips3_sd(h, val);

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

821

mips3_sd(h, cval);

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

844

mips3_sd(h, cval);

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

863

mips3_sd(h, ((CHIP_TYPE)CHIP_SWAP32(val)) << shift);

sys/arch/mips/mips/bus_space_alignstride_chipdep.c

875

mips3_sd(h, CHIP_SWAP64(val));

sys/arch/mips/mips/db_interface.c

866

mips3_sd(MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_NMI), __BIT(ci->ci_cpuid));

sys/arch/mips/sibyte/dev/sbbuswatch.c

44

#define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))

sys/arch/mips/sibyte/dev/sbjcn.c

239

#define WRITE_REG(rp, val) (mips3_sd((volatile uint64_t *)(rp), (val)))

sys/arch/mips/sibyte/dev/sbmac.c

116

#define SBMAC_WRITECSR(t, v) mips3_sd((register_t)(t), (v))

sys/arch/mips/sibyte/dev/sbscn.c

248

#define WRITE_REG(rp, val) (mips3_sd((register_t)(rp), (val)))

sys/arch/mips/sibyte/dev/sbtimer.c

62

#define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))

sys/arch/mips/sibyte/dev/sbwdog.c

82

#define WRITE_REG(rp, val) (mips3_sd((register_t)(rp), (val)))

sys/arch/mips/sibyte/pci/sbbrz_pci.c

216

return mips3_sd(addr, data);

sys/arch/sbmips/sbmips/rtc.c

421

#define WRITE_REG(rp, val) mips3_sd((register_t)(MIPS_PHYS_TO_KSEG1(rp)), (val))

sys/arch/sbmips/sbmips/sb1250_icu.c

94

#define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))