CMD_PHASE
case CMD_PHASE:
case SBIC_CSR_XFERRED | CMD_PHASE:
case SBIC_CSR_MIS | CMD_PHASE:
case SBIC_CSR_MIS_1 | CMD_PHASE:
case SBIC_CSR_MIS_2 | CMD_PHASE:
if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait))
cbuf, CMD_PHASE))
case SBIC_CSR_XFERRED | CMD_PHASE:
case SBIC_CSR_MIS | CMD_PHASE:
case SBIC_CSR_MIS_1 | CMD_PHASE:
case SBIC_CSR_MIS_2 | CMD_PHASE:
if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait))
&acb->cmd, CMD_PHASE))
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
if (csr == (SBIC_CSR_MIS_2 | CMD_PHASE)) {
&& csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO);
if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) {
case CMD_PHASE:
case SBIC_CSR_XFERRED|CMD_PHASE:
case SBIC_CSR_MIS|CMD_PHASE:
case SBIC_CSR_MIS_1|CMD_PHASE:
case SBIC_CSR_MIS_2|CMD_PHASE:
if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait))
cbuf, CMD_PHASE))
case SBIC_CSR_XFERRED|CMD_PHASE:
case SBIC_CSR_MIS|CMD_PHASE:
case SBIC_CSR_MIS_1|CMD_PHASE:
case SBIC_CSR_MIS_2|CMD_PHASE:
if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait))
&acb->cmd, CMD_PHASE))
phase = CMD_PHASE;
case CMD_PHASE:
phase = CMD_PHASE;
case CMD_PHASE:
phase = CMD_PHASE;
case CMD_PHASE:
} else if (hs->sc_phase == CMD_PHASE) {
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
case SBIC_CSR_XFERRED | CMD_PHASE:
case SBIC_CSR_MIS | CMD_PHASE:
case SBIC_CSR_MIS_1 | CMD_PHASE:
case SBIC_CSR_MIS_2 | CMD_PHASE:
case SBIC_CSR_XFERRED | CMD_PHASE:
case SBIC_CSR_MIS | CMD_PHASE:
case SBIC_CSR_MIS_1 | CMD_PHASE:
case SBIC_CSR_MIS_2 | CMD_PHASE:
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
case SBIC_CSR_XFERRED | CMD_PHASE:
case SBIC_CSR_MIS | CMD_PHASE:
case SBIC_CSR_MIS_1 | CMD_PHASE:
case SBIC_CSR_MIS_2 | CMD_PHASE:
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
case SBIC_CSR_XFERRED | CMD_PHASE:
case SBIC_CSR_MIS | CMD_PHASE:
case SBIC_CSR_MIS_1 | CMD_PHASE:
case SBIC_CSR_MIS_2 | CMD_PHASE:
case CMD_PHASE: