Symbol: crtc
sys/arch/arm/nvidia/tegra_drm.h
150
#define DC_READ(crtc, reg) \
sys/arch/arm/nvidia/tegra_drm.h
151
bus_space_read_4((crtc)->bst, (crtc)->bsh, (reg))
sys/arch/arm/nvidia/tegra_drm.h
152
#define DC_WRITE(crtc, reg, val) \
sys/arch/arm/nvidia/tegra_drm.h
153
bus_space_write_4((crtc)->bst, (crtc)->bsh, (reg), (val))
sys/arch/arm/nvidia/tegra_drm.h
154
#define DC_SET_CLEAR(crtc, reg, set, clr) \
sys/arch/arm/nvidia/tegra_drm.h
155
tegra_reg_set_clear((crtc)->bst, (crtc)->bsh, (reg), (set), (clr))
sys/arch/arm/nvidia/tegra_drm_mode.c
1303
tegra_drm_get_vblank_counter(struct drm_device *ddev, unsigned int crtc)
sys/arch/arm/nvidia/tegra_drm_mode.c
1307
if (crtc > 1)
sys/arch/arm/nvidia/tegra_drm_mode.c
1310
return sc->sc_vbl_received[crtc];
sys/arch/arm/nvidia/tegra_drm_mode.c
1314
tegra_drm_enable_vblank(struct drm_device *ddev, unsigned int crtc)
sys/arch/arm/nvidia/tegra_drm_mode.c
1320
if (to_tegra_crtc(iter)->index == crtc) {
sys/arch/arm/nvidia/tegra_drm_mode.c
1334
tegra_drm_disable_vblank(struct drm_device *ddev, unsigned int crtc)
sys/arch/arm/nvidia/tegra_drm_mode.c
1340
if (to_tegra_crtc(iter)->index == crtc) {
sys/arch/arm/nvidia/tegra_drm_mode.c
279
struct tegra_crtc *crtc;
sys/arch/arm/nvidia/tegra_drm_mode.c
307
crtc = kmem_zalloc(sizeof(*crtc), KM_SLEEP);
sys/arch/arm/nvidia/tegra_drm_mode.c
308
crtc->index = index;
sys/arch/arm/nvidia/tegra_drm_mode.c
309
crtc->bst = sc->sc_bst;
sys/arch/arm/nvidia/tegra_drm_mode.c
310
error = bus_space_map(crtc->bst, offset, size, 0, &crtc->bsh);
sys/arch/arm/nvidia/tegra_drm_mode.c
312
kmem_free(crtc, sizeof(*crtc));
sys/arch/arm/nvidia/tegra_drm_mode.c
315
crtc->size = size;
sys/arch/arm/nvidia/tegra_drm_mode.c
316
crtc->intr = intr;
sys/arch/arm/nvidia/tegra_drm_mode.c
317
crtc->ih = intr_establish_xname(intr, IPL_VM, IST_LEVEL | IST_MPSAFE,
sys/arch/arm/nvidia/tegra_drm_mode.c
318
tegra_crtc_intr, crtc, device_xname(sc->sc_dev)); /* XXX */
sys/arch/arm/nvidia/tegra_drm_mode.c
319
if (crtc->ih == NULL) {
sys/arch/arm/nvidia/tegra_drm_mode.c
323
crtc->cursor_obj = drm_gem_cma_create(ddev, cursor_size);
sys/arch/arm/nvidia/tegra_drm_mode.c
324
if (crtc->cursor_obj == NULL) {
sys/arch/arm/nvidia/tegra_drm_mode.c
325
kmem_free(crtc, sizeof(*crtc));
sys/arch/arm/nvidia/tegra_drm_mode.c
356
crtc->clk_parent = sc->sc_clk_hdmi_parent;
sys/arch/arm/nvidia/tegra_drm_mode.c
358
DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK);
sys/arch/arm/nvidia/tegra_drm_mode.c
360
drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs);
sys/arch/arm/nvidia/tegra_drm_mode.c
361
drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs);
sys/arch/arm/nvidia/tegra_drm_mode.c
367
tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
sys/arch/arm/nvidia/tegra_drm_mode.c
370
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
510
tegra_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
sys/arch/arm/nvidia/tegra_drm_mode.c
512
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
531
tegra_crtc_destroy(struct drm_crtc *crtc)
sys/arch/arm/nvidia/tegra_drm_mode.c
533
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
534
drm_crtc_cleanup(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
544
tegra_crtc_dpms(struct drm_crtc *crtc, int mode)
sys/arch/arm/nvidia/tegra_drm_mode.c
546
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
563
tegra_crtc_mode_fixup(struct drm_crtc *crtc,
sys/arch/arm/nvidia/tegra_drm_mode.c
570
tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
sys/arch/arm/nvidia/tegra_drm_mode.c
574
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
612
tegra_crtc_do_set_base(crtc, old_fb, x, y, 0);
sys/arch/arm/nvidia/tegra_drm_mode.c
665
tegra_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb,
sys/arch/arm/nvidia/tegra_drm_mode.c
668
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
671
to_tegra_framebuffer(crtc->primary->fb);
sys/arch/arm/nvidia/tegra_drm_mode.c
692
tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
sys/arch/arm/nvidia/tegra_drm_mode.c
695
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
697
tegra_crtc_do_set_base(crtc, old_fb, x, y, 0);
sys/arch/arm/nvidia/tegra_drm_mode.c
709
tegra_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
sys/arch/arm/nvidia/tegra_drm_mode.c
712
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
714
tegra_crtc_do_set_base(crtc, fb, x, y, 1);
sys/arch/arm/nvidia/tegra_drm_mode.c
726
tegra_crtc_disable(struct drm_crtc *crtc)
sys/arch/arm/nvidia/tegra_drm_mode.c
731
tegra_crtc_prepare(struct drm_crtc *crtc)
sys/arch/arm/nvidia/tegra_drm_mode.c
733
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
744
tegra_crtc_commit(struct drm_crtc *crtc)
sys/arch/arm/nvidia/tegra_drm_mode.c
746
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
sys/arch/arm/nvidia/tegra_drm_mode.c
839
if (encoder->crtc == NULL)
sys/arch/arm/nvidia/tegra_drm_mode.c
904
struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc);
sys/arch/arm/nxp/imx6_dwhdmi.c
137
struct drm_crtc *crtc;
sys/arch/arm/nxp/imx6_dwhdmi.c
152
crtc = fdt_endpoint_get_data(in_ep);
sys/arch/arm/nxp/imx6_dwhdmi.c
155
crtc = NULL;
sys/arch/arm/nxp/imx6_dwhdmi.c
159
if (crtc == NULL)
sys/arch/arm/nxp/imx6_dwhdmi.c
163
drm_encoder_init(crtc->dev, &sc->sc_encoder, &imx6_dwhdmi_encoder_funcs,
sys/arch/arm/rockchip/rk_anxdp.c
115
const u_int crtc_index = drm_crtc_index(encoder->crtc);
sys/arch/arm/rockchip/rk_anxdp.c
138
struct drm_crtc *crtc;
sys/arch/arm/rockchip/rk_anxdp.c
153
crtc = fdt_endpoint_get_data(in_ep);
sys/arch/arm/rockchip/rk_anxdp.c
161
drm_encoder_init(crtc->dev, &sc->sc_encoder, &rk_anxdp_encoder_funcs,
sys/arch/arm/rockchip/rk_dwhdmi.c
113
const u_int crtc_index = drm_crtc_index(encoder->crtc);
sys/arch/arm/rockchip/rk_dwhdmi.c
132
struct drm_crtc *crtc;
sys/arch/arm/rockchip/rk_dwhdmi.c
147
crtc = fdt_endpoint_get_data(in_ep);
sys/arch/arm/rockchip/rk_dwhdmi.c
150
crtc = NULL;
sys/arch/arm/rockchip/rk_dwhdmi.c
154
if (crtc == NULL)
sys/arch/arm/rockchip/rk_dwhdmi.c
158
drm_encoder_init(crtc->dev, &sc->sc_encoder, &rk_dwhdmi_encoder_funcs,
sys/arch/arm/rockchip/rk_vop.c
290
if (state->crtc == NULL)
sys/arch/arm/rockchip/rk_vop.c
293
crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
sys/arch/arm/rockchip/rk_vop.c
310
struct drm_display_mode *mode = &plane->state->crtc->mode;
sys/arch/arm/rockchip/rk_vop.c
418
rk_vop_crtc_dpms(struct drm_crtc *crtc, int mode)
sys/arch/arm/rockchip/rk_vop.c
420
struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
sys/arch/arm/rockchip/rk_vop.c
444
rk_vop_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
sys/arch/arm/rockchip/rk_vop.c
446
bool enabled = state->plane_mask & drm_plane_mask(crtc->primary);
sys/arch/arm/rockchip/rk_vop.c
451
return drm_atomic_add_affected_planes(state->state, crtc);
sys/arch/arm/rockchip/rk_vop.c
455
rk_vop_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *state)
sys/arch/arm/rockchip/rk_vop.c
457
struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
sys/arch/arm/rockchip/rk_vop.c
459
struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
sys/arch/arm/rockchip/rk_vop.c
487
drm_connector_list_iter_begin(crtc->dev, &conn_iter);
sys/arch/arm/rockchip/rk_vop.c
491
if (connector->encoder->crtc == crtc) {
sys/arch/arm/rockchip/rk_vop.c
550
drm_crtc_vblank_on(crtc);
sys/arch/arm/rockchip/rk_vop.c
554
rk_vop_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *state)
sys/arch/arm/rockchip/rk_vop.c
556
struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
sys/arch/arm/rockchip/rk_vop.c
560
drm_crtc_vblank_off(crtc);
sys/arch/arm/rockchip/rk_vop.c
566
if (crtc->state->event && !crtc->state->active) {
sys/arch/arm/rockchip/rk_vop.c
567
spin_lock(&crtc->dev->event_lock);
sys/arch/arm/rockchip/rk_vop.c
568
drm_crtc_send_vblank_event(crtc, crtc->state->event);
sys/arch/arm/rockchip/rk_vop.c
569
spin_unlock(&crtc->dev->event_lock);
sys/arch/arm/rockchip/rk_vop.c
571
crtc->state->event = NULL;
sys/arch/arm/rockchip/rk_vop.c
576
rk_vop_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state)
sys/arch/arm/rockchip/rk_vop.c
578
struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
sys/arch/arm/rockchip/rk_vop.c
589
spin_lock(&crtc->dev->event_lock);
sys/arch/arm/rockchip/rk_vop.c
590
if (crtc->state->event) {
sys/arch/arm/rockchip/rk_vop.c
591
if ((ret = drm_crtc_vblank_get_locked(crtc)) != 0)
sys/arch/arm/rockchip/rk_vop.c
596
sc->sc_event = crtc->state->event;
sys/arch/arm/rockchip/rk_vop.c
597
crtc->state->event = NULL;
sys/arch/arm/rockchip/rk_vop.c
599
spin_unlock(&crtc->dev->event_lock);
sys/arch/arm/rockchip/rk_vop.c
611
rk_vop_crtc_enable_vblank(struct drm_crtc *crtc)
sys/arch/arm/rockchip/rk_vop.c
613
struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
sys/arch/arm/rockchip/rk_vop.c
625
rk_vop_crtc_disable_vblank(struct drm_crtc *crtc)
sys/arch/arm/rockchip/rk_vop.c
627
struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
sys/arch/arm/rockchip/rk_vop.c
710
struct drm_crtc *crtc = &sc->sc_crtc.base;
sys/arch/arm/rockchip/rk_vop.c
731
drm_crtc_send_vblank_event(crtc, sc->sc_event);
sys/arch/arm/rockchip/rk_vop.c
733
drm_crtc_vblank_put(crtc);
sys/arch/arm/sunxi/sunxi_drm.h
57
struct drm_crtc *crtc;
sys/arch/arm/sunxi/sunxi_lcdc.c
385
struct drm_crtc *crtc;
sys/arch/arm/sunxi/sunxi_lcdc.c
396
crtc = fdt_endpoint_get_data(in_ep);
sys/arch/arm/sunxi/sunxi_lcdc.c
399
sc->sc_encoder.base.possible_crtcs = 1 << drm_crtc_index(crtc);
sys/arch/arm/sunxi/sunxi_lcdc.c
403
drm_encoder_init(crtc->dev, &sc->sc_encoder.base, &sunxi_lcdc_funcs,
sys/arch/arm/sunxi/sunxi_lcdc.c
414
drm_encoder_init(crtc->dev, &sc->sc_encoder.base, &sunxi_lcdc_funcs,
sys/arch/arm/sunxi/sunxi_lcdc.c
449
struct drm_crtc *crtc = drm_sc->sc_vbl[crtc_index].crtc;
sys/arch/arm/sunxi/sunxi_lcdc.c
452
if (crtc != NULL) {
sys/arch/arm/sunxi/sunxi_lcdc.c
453
drm_crtc_handle_vblank(crtc);
sys/arch/arm/sunxi/sunxi_lcdc.c
456
drm_crtc_send_vblank_event(crtc,
sys/arch/arm/sunxi/sunxi_lcdc.c
459
drm_crtc_vblank_put(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
283
if (state->crtc == NULL) {
sys/arch/arm/sunxi/sunxi_mixer.c
287
crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
378
sunxi_mixer_crtc_atomic_check(struct drm_crtc *crtc,
sys/arch/arm/sunxi/sunxi_mixer.c
381
bool enabled = state->plane_mask & drm_plane_mask(crtc->primary);
sys/arch/arm/sunxi/sunxi_mixer.c
387
return drm_atomic_add_affected_planes(state->state, crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
391
sunxi_mixer_crtc_atomic_enable(struct drm_crtc *crtc,
sys/arch/arm/sunxi/sunxi_mixer.c
394
struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
396
struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
sys/arch/arm/sunxi/sunxi_mixer.c
432
drm_crtc_vblank_on(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
434
if (drm_crtc_index(crtc) == 0) {
sys/arch/arm/sunxi/sunxi_mixer.c
440
sunxi_mixer_crtc_atomic_disable(struct drm_crtc *crtc,
sys/arch/arm/sunxi/sunxi_mixer.c
443
drm_crtc_vblank_off(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
445
if (crtc->state->event && !crtc->state->active) {
sys/arch/arm/sunxi/sunxi_mixer.c
446
spin_lock(&crtc->dev->event_lock);
sys/arch/arm/sunxi/sunxi_mixer.c
447
drm_crtc_send_vblank_event(crtc, crtc->state->event);
sys/arch/arm/sunxi/sunxi_mixer.c
448
spin_unlock(&crtc->dev->event_lock);
sys/arch/arm/sunxi/sunxi_mixer.c
450
crtc->state->event = NULL;
sys/arch/arm/sunxi/sunxi_mixer.c
453
if (drm_crtc_index(crtc) == 0) {
sys/arch/arm/sunxi/sunxi_mixer.c
459
sunxi_mixer_crtc_atomic_flush(struct drm_crtc *crtc,
sys/arch/arm/sunxi/sunxi_mixer.c
462
struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
473
spin_lock(&crtc->dev->event_lock);
sys/arch/arm/sunxi/sunxi_mixer.c
474
if (crtc->state->event) {
sys/arch/arm/sunxi/sunxi_mixer.c
475
struct sunxi_drm_softc *drm_sc = device_private(crtc->dev->dev);
sys/arch/arm/sunxi/sunxi_mixer.c
476
const int crtc_index = drm_crtc_index(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
479
if ((ret = drm_crtc_vblank_get_locked(crtc)) != 0) {
sys/arch/arm/sunxi/sunxi_mixer.c
486
vbl->event = crtc->state->event;
sys/arch/arm/sunxi/sunxi_mixer.c
487
crtc->state->event = NULL;
sys/arch/arm/sunxi/sunxi_mixer.c
489
spin_unlock(&crtc->dev->event_lock);
sys/arch/arm/sunxi/sunxi_mixer.c
493
sunxi_mixer_crtc_enable_vblank(struct drm_crtc *crtc)
sys/arch/arm/sunxi/sunxi_mixer.c
495
struct drm_device *ddev = crtc->dev;
sys/arch/arm/sunxi/sunxi_mixer.c
497
const int crtc_index = drm_crtc_index(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
508
sunxi_mixer_crtc_disable_vblank(struct drm_crtc *crtc)
sys/arch/arm/sunxi/sunxi_mixer.c
510
struct drm_device *ddev = crtc->dev;
sys/arch/arm/sunxi/sunxi_mixer.c
512
const int crtc_index = drm_crtc_index(crtc);
sys/arch/arm/sunxi/sunxi_mixer.c
596
drm_sc->sc_vbl[drm_crtc_index(&sc->sc_crtc.base)].crtc = &sc->sc_crtc.base;
sys/arch/arm/ti/ti_lcdc.c
100
tilcdc_mode_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb,
sys/arch/arm/ti/ti_lcdc.c
103
struct tilcdc_crtc *mixer_crtc = to_tilcdc_crtc(crtc);
sys/arch/arm/ti/ti_lcdc.c
107
to_tilcdc_framebuffer(crtc->primary->fb);
sys/arch/arm/ti/ti_lcdc.c
120
tilcdc_destroy(struct drm_crtc *crtc)
sys/arch/arm/ti/ti_lcdc.c
122
drm_crtc_cleanup(crtc);
sys/arch/arm/ti/ti_lcdc.c
131
tilcdc_dpms(struct drm_crtc *crtc, int mode)
sys/arch/arm/ti/ti_lcdc.c
136
tilcdc_mode_fixup(struct drm_crtc *crtc,
sys/arch/arm/ti/ti_lcdc.c
154
tilcdc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
sys/arch/arm/ti/ti_lcdc.c
158
struct tilcdc_crtc *mixer_crtc = to_tilcdc_crtc(crtc);
sys/arch/arm/ti/ti_lcdc.c
229
tilcdc_mode_do_set_base(crtc, old_fb, x, y, 0);
sys/arch/arm/ti/ti_lcdc.c
235
tilcdc_mode_set_base(struct drm_crtc *crtc, int x, int y,
sys/arch/arm/ti/ti_lcdc.c
238
tilcdc_mode_do_set_base(crtc, old_fb, x, y, 0);
sys/arch/arm/ti/ti_lcdc.c
244
tilcdc_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
sys/arch/arm/ti/ti_lcdc.c
247
tilcdc_mode_do_set_base(crtc, fb, x, y, 1);
sys/arch/arm/ti/ti_lcdc.c
253
tilcdc_disable(struct drm_crtc *crtc)
sys/arch/arm/ti/ti_lcdc.c
258
tilcdc_prepare(struct drm_crtc *crtc)
sys/arch/arm/ti/ti_lcdc.c
263
tilcdc_commit(struct drm_crtc *crtc)
sys/arch/arm/ti/ti_lcdc.c
265
struct tilcdc_crtc *mixer_crtc = to_tilcdc_crtc(crtc);
sys/arch/x68k/dev/grf_gv.c
138
volatile struct crtc *crtc = &IODEVbase->io_crtc;
sys/arch/x68k/dev/grf_gv.c
140
crtc->r20 = (crtc->r20 & 0xFF00) | 0x1a;
sys/arch/x68k/dev/grf_gv.c
141
crtc->r08 = 0x1b;
sys/arch/x68k/dev/grf_gv.c
142
crtc->r07 = 0x19c;
sys/arch/x68k/dev/grf_gv.c
143
crtc->r06 = 0x1c;
sys/arch/x68k/dev/grf_gv.c
144
crtc->r05 = 0x02;
sys/arch/x68k/dev/grf_gv.c
145
crtc->r04 = 0x019f;
sys/arch/x68k/dev/grf_gv.c
146
crtc->r03 = 0x9a;
sys/arch/x68k/dev/grf_gv.c
147
crtc->r02 = 0x1a;
sys/arch/x68k/dev/grf_gv.c
148
crtc->r01 = 0x09;
sys/arch/x68k/dev/grf_gv.c
149
crtc->r00 = 0xa4;
sys/arch/x68k/dev/grf_tv.c
138
volatile struct crtc *crtc = &IODEVbase->io_crtc;
sys/arch/x68k/dev/grf_tv.c
140
crtc->r20 = (crtc->r20 & 0xFF00) | 0x1a;
sys/arch/x68k/dev/grf_tv.c
141
crtc->r08 = 0x1b;
sys/arch/x68k/dev/grf_tv.c
142
crtc->r07 = 0x19c;
sys/arch/x68k/dev/grf_tv.c
143
crtc->r06 = 0x1c;
sys/arch/x68k/dev/grf_tv.c
144
crtc->r05 = 0x02;
sys/arch/x68k/dev/grf_tv.c
145
crtc->r04 = 0x019f;
sys/arch/x68k/dev/grf_tv.c
146
crtc->r03 = 0x9a;
sys/arch/x68k/dev/grf_tv.c
147
crtc->r02 = 0x1a;
sys/arch/x68k/dev/grf_tv.c
148
crtc->r01 = 0x09;
sys/arch/x68k/dev/grf_tv.c
149
crtc->r00 = 0xa4;
sys/arch/x68k/x68k/iodevice.h
305
struct crtc io_crtc; /* 0x00e80000 */
sys/dev/ic/vga_raster.c
1024
_vga_6845_write(vh, i, regs->crtc[i]);
sys/dev/ic/vga_raster.c
147
u_int8_t crtc[MC6845_NREGS]; /* CRTC controller */
sys/dev/ic/vga_raster.c
929
regs->crtc[0] = (mode->htotal >> 3) - 5;
sys/dev/ic/vga_raster.c
930
regs->crtc[1] = (mode->hdisplay >> 3) - 1;
sys/dev/ic/vga_raster.c
931
regs->crtc[2] = (mode->hsync_start >> 3) - 1;
sys/dev/ic/vga_raster.c
932
regs->crtc[3] = (((mode->hsync_end >> 3) - 1) & 0x1f) | 0x80;
sys/dev/ic/vga_raster.c
933
regs->crtc[4] = mode->hsync_start >> 3;
sys/dev/ic/vga_raster.c
934
regs->crtc[5] = ((((mode->hsync_end >> 3) - 1) & 0x20) << 2)
sys/dev/ic/vga_raster.c
936
regs->crtc[6] = (mode->vtotal - 2) & 0xff;
sys/dev/ic/vga_raster.c
937
regs->crtc[7] = (((mode->vtotal - 2) & 0x100) >> 8)
sys/dev/ic/vga_raster.c
945
regs->crtc[8] = 0x00;
sys/dev/ic/vga_raster.c
946
regs->crtc[9] = (((mode->vsync_start - 1) & 0x200) >> 4) | 0x40;
sys/dev/ic/vga_raster.c
948
regs->crtc[9] |= 0x80;
sys/dev/ic/vga_raster.c
949
regs->crtc[10] = 0x00;
sys/dev/ic/vga_raster.c
950
regs->crtc[11] = 0x00;
sys/dev/ic/vga_raster.c
951
regs->crtc[12] = 0x00;
sys/dev/ic/vga_raster.c
952
regs->crtc[13] = 0x00;
sys/dev/ic/vga_raster.c
953
regs->crtc[14] = 0x00;
sys/dev/ic/vga_raster.c
954
regs->crtc[15] = 0x00;
sys/dev/ic/vga_raster.c
955
regs->crtc[16] = mode->vsync_start & 0xff;
sys/dev/ic/vga_raster.c
956
regs->crtc[17] = (mode->vsync_end & 0x0f) | 0x20;
sys/dev/ic/vga_raster.c
957
regs->crtc[18] = (mode->vdisplay - 1) & 0xff;
sys/dev/ic/vga_raster.c
958
regs->crtc[19] = mode->hdisplay >> 4; /* XXXBJY */
sys/dev/ic/vga_raster.c
959
regs->crtc[20] = 0x00;
sys/dev/ic/vga_raster.c
960
regs->crtc[21] = (mode->vsync_start - 1) & 0xff;
sys/dev/ic/vga_raster.c
961
regs->crtc[22] = (mode->vsync_end - 1) & 0xff;
sys/dev/ic/vga_raster.c
963
regs->crtc[23] = 0xe3;
sys/dev/ic/vga_raster.c
965
regs->crtc[23] = 0xc3;
sys/dev/ic/vga_raster.c
966
regs->crtc[24] = 0xff;
sys/dev/pci/machfb.c
1064
mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc,
sys/dev/pci/machfb.c
1072
crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) |
sys/dev/pci/machfb.c
1074
crtc->h_sync_strt_wid =
sys/dev/pci/machfb.c
1078
crtc->v_total_disp = ((mode->vdisplay - 1) << 16) |
sys/dev/pci/machfb.c
1080
crtc->v_sync_strt_wid =
sys/dev/pci/machfb.c
1085
crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG;
sys/dev/pci/machfb.c
1089
crtc->color_depth = CRTC_PIX_WIDTH_8BPP;
sys/dev/pci/machfb.c
1092
crtc->color_depth = CRTC_PIX_WIDTH_16BPP;
sys/dev/pci/machfb.c
1095
crtc->color_depth = CRTC_PIX_WIDTH_32BPP;
sys/dev/pci/machfb.c
1099
crtc->gen_cntl = 0;
sys/dev/pci/machfb.c
1101
crtc->gen_cntl |= CRTC_INTERLACE_EN;
sys/dev/pci/machfb.c
1104
crtc->gen_cntl |= CRTC_CSYNC_EN;
sys/dev/pci/machfb.c
1106
crtc->dot_clock = mode->dot_clock;
sys/dev/pci/machfb.c
1112
mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc)
sys/dev/pci/machfb.c
1115
mach64_set_pll(sc, crtc->dot_clock);
sys/dev/pci/machfb.c
1121
crtc->h_total_disp, crtc->h_sync_strt_wid);
sys/dev/pci/machfb.c
1123
crtc->v_total_disp, crtc->v_sync_strt_wid);
sys/dev/pci/machfb.c
1124
regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp);
sys/dev/pci/machfb.c
1125
regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
sys/dev/pci/machfb.c
1126
regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp);
sys/dev/pci/machfb.c
1127
regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
sys/dev/pci/machfb.c
1133
regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth |
sys/dev/pci/machfb.c
1140
struct mach64_crtcregs crtc;
sys/dev/pci/machfb.c
1142
memset(&crtc, 0, sizeof crtc); /* XXX gcc */
sys/dev/pci/machfb.c
1144
if (mach64_calc_crtcregs(sc, &crtc, mode))
sys/dev/pci/machfb.c
1146
aprint_debug("crtc dot clock: %d\n", crtc.dot_clock);
sys/dev/pci/machfb.c
1147
if (crtc.dot_clock == 0) {
sys/dev/pci/machfb.c
1149
device_xname(sc->sc_dev), crtc.dot_clock);
sys/dev/pci/machfb.c
1152
mach64_set_crtcregs(sc, &crtc);
sys/dev/pci/mgafb.c
1590
uint8_t crtc[25], crtcext[6], misc, vsyncpol;
sys/dev/pci/mgafb.c
1607
crtc, crtcext, &misc, &vsyncpol);
sys/dev/pci/mgafb.c
1631
MGA_WRITE1(sc, MGA_VGA_CRTC_DATA, crtc[i]);
sys/dev/pci/mgafb.c
1635
MGA_WRITE1(sc, MGA_VGA_CRTC_DATA, crtc[0x11] | 0x80); /* re-lock */
sys/dev/pci/radeonfb.c
2136
radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc)
sys/dev/pci/radeonfb.c
2138
if (crtc) {
sys/dev/pci/radeonfb.c
2150
radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc)
sys/dev/pci/radeonfb.c
2155
if (crtc) {
sys/dev/pci/radeonfb.c
2168
radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags)
sys/dev/pci/radeonfb.c
2176
if (crtc == 0) {
sys/dev/pci/radeonfb.c
2241
radeonfb_pllwriteupdate(sc, crtc);
sys/dev/pci/radeonfb.c
2244
radeonfb_pllwaitatomicread(sc, crtc);
sys/dev/pci/radeonfb.c
2303
radeonfb_pllwriteupdate(sc, crtc);
sys/dev/pci/radeonfb.c
2306
radeonfb_pllwaitatomicread(sc, crtc);
sys/dev/pci/radeonfb.c
2410
int crtc, flags = 0;
sys/dev/pci/radeonfb.c
2434
crtc = cp->rc_number;
sys/dev/pci/radeonfb.c
2443
switch (crtc) {
sys/dev/pci/radeonfb.c
2479
if (crtc == 1) {
sys/dev/pci/radeonfb.c
2493
if (crtc == 1)
sys/dev/pci/radeonfb.c
2498
DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2508
if (crtc == 0) {
sys/dev/pci/radeonfb.c
2532
DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2536
DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2546
DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2549
DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2558
DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2561
DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2572
DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2575
DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
sys/dev/pci/radeonfb.c
2578
radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags);
sys/dev/pci/radeonfb.c
2580
switch (crtc) {
sys/dev/pci/radeonfb.c
2963
int crtc, cc;
sys/dev/pci/radeonfb.c
2968
crtc = dp->rd_crtcs[cc].rc_number;
sys/dev/pci/radeonfb.c
2970
if (crtc)
sys/dev/pci/radeonfb.c
2986
crtc = dp->rd_crtcs[cc].rc_number;
sys/dev/pci/radeonfb.c
2988
if (crtc)
sys/dev/pci/unichromefb.c
634
crt = vtbl->crtc;
sys/dev/pci/unichromefb.c
762
crtreg = ctbl[index].crtc;
sys/dev/pci/unichromemode.h
41
struct crt_mode_table *crtc;
sys/dev/pci/unichromereg.h
716
struct display_timing crtc;