_reg_write_1
_reg_write_1(EXTINTR_MASK4, reg);
_reg_write_1(EXTINTR_MASK3, reg);
_reg_write_1(EXTINTR_MASK2, reg);
_reg_write_1(EXTINTR_MASK1, reg);
_reg_write_1(EXTINTR_MASK4, reg);
_reg_write_1(EXTINTR_MASK3, reg);
_reg_write_1(EXTINTR_MASK2, reg);
_reg_write_1(EXTINTR_MASK1, reg);
_reg_write_1(EXTINTR_MASK1, 0);
_reg_write_1(EXTINTR_MASK2, 0);
_reg_write_1(EXTINTR_MASK3, 0);
_reg_write_1(EXTINTR_MASK4, 0);
_reg_write_1(BSC_SDMR2_VAL, 0);
_reg_write_1(BSC_SDMR3_VAL, 0);
_reg_write_1(BSC_SDMR3_VAL, 0);
_reg_write_1((reg), _r); \
_reg_write_1((reg), _r); \
_reg_write_1((reg), _r); \
_reg_write_1((reg), _r); \
_reg_write_1(SSUMCI_SPIDR, v);
_reg_write_1(SH3_SCTDR, c); \
_reg_write_1(SH3_SCSSR, \
_reg_write_1(SH3_SCFTDR2, c); \
_reg_write_1(SH3_SCSSR2, \
_reg_write_1(SH7709_PKDR, 0); /* Green LED on */
_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ0);
_reg_write_1(SH7709_PKDR, 0xff); /* Green LED off */
_reg_write_1(SH7709_PKDR, 0); /* Green LED on */
_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ3);
_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ3);
_reg_write_1(SH7709_SCPDR, scpdr);
_reg_write_1(SH7709_SCPDR, scpdr);
_reg_write_1(SH7709_SCPDR, scpdr);
_reg_write_1(SH7709_PDDR, scan[column].d);
_reg_write_1(SH7709_PEDR, scan[column].e);
_reg_write_1(SH7709_PDDR, 0xff);
_reg_write_1(SH7709_PEDR, 0xff);
_reg_write_1(SH7709_PCDR, cd | scan[i].c);
_reg_write_1(SH7709_PDDR, dd | scan[i].d);
_reg_write_1(SH7709_PEDR, ed | scan[i].e);
_reg_write_1(SH7709_PCDR, cd | poll.c);
_reg_write_1(SH7709_PDDR, dd | poll.d);
_reg_write_1(SH7709_PEDR, ed | poll.e);
_reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_xx0_bcd[index].reg1);
_reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_xx0_bcd[index].reg2);
_reg_write_1(PSH3LCD_BRIGHTNESS_REG0, psh3lcd_x0_bcd[index].reg0);
_reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_x0_bcd[index].reg1);
_reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_x0_bcd[index].reg2);
_reg_write_1(SH7709_PDDR, pddr);
_reg_write_1(SH7709_PHDR, phdr | PSH3_GREEN_LED_ON);
_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ0);
_reg_write_1(SH7709_SCPDR, scpdr | PSH3PWR_PLUG_OUT);
_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ1);
_reg_write_1(SH7709_SCPDR, scpdr & ~PSH3PWR_PLUG_OUT);
_reg_write_1(SH7709_PHDR, phdr & ~PSH3_GREEN_LED_ON);
_reg_write_1(SH7709_PHDR, phdr | PSH3_GREEN_LED_ON);
_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ2);
_reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ2);
_reg_write_1(SH7709_SCPDR, scpdr);
_reg_write_1(SH7709_SCPDR, scpdr);
_reg_write_1(SH7709_SCPDR, scpdr);
_reg_write_1(LANDISK_PWRSW_INTCLR, 1);
_reg_write_1(LANDISK_PWRMNG, PWRMNG_RTC_CE);
_reg_write_1(LANDISK_PWRMNG, 0);
_reg_write_1(LANDISK_INTEN, inten);
_reg_write_1(LANDISK_INTEN, INTEN_ALL_MASK);
_reg_write_1(LANDISK_INTEN, inten & ~bit);
_reg_write_1(LANDISK_PWRMNG, PWRMNG_POWEROFF);
_reg_write_1(BSC_SDMR2_VAL, 0);
_reg_write_1(BSC_SDMR3_VAL, 0);
_reg_write_1(0xb0000003, (1 << 1));
_reg_write_1(0xb0000003, (0 << 1));
_reg_write_1(SH_(TOCR), TOCR_TCOE);
_reg_write_1(SMAP_DESC_MODE_REG8, 0);
_reg_write_1(SMAP_RXFIFO_FRAME_DEC_REG8, 1);
_reg_write_1(SMAP_TXFIFO_FRAME_INC_REG8, 1);
_reg_write_1(a, SMAP_FIFO_RESET);
_reg_write_1(SPD_IO_DIR_REG8, SPD_IO_CLK | SPD_IO_CS | SPD_IO_IN);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SPD_IO_DATA_REG8, r);
_reg_write_1(SH_(RCR1), 0);
_reg_write_1(SH_(RCR2), SH_RCR2_ENABLE | SH_RCR2_START);
_reg_write_1(SH_(RCR1), r);
_reg_write_1(SH_(RCR2), (r & ~SH_RCR2_START) | SH_RCR2_RESET);
_reg_write_1(SH3_RYRCNT, year);
_reg_write_1(SH_(R ## x ## CNT), bintobcd(dt->dt_ ## y))
_reg_write_1(SH_(RCR2), r);
_reg_write_1(SH_(RCR1), 0);
_reg_write_1(SH_(TSTR), 0);
_reg_write_1(SH_(TSTR), 0);
_reg_write_1(SH4_BAMRA, SH4_UBC_MASK_NONE | SH4_UBC_MASK_ASID);