_reg_read_1
reg = _reg_read_1(EXTINTR_MASK4);
reg = _reg_read_1(EXTINTR_MASK3);
reg = _reg_read_1(EXTINTR_MASK2);
reg = _reg_read_1(EXTINTR_MASK1);
reg = _reg_read_1(EXTINTR_MASK4);
reg = _reg_read_1(EXTINTR_MASK3);
reg = _reg_read_1(EXTINTR_MASK2);
reg = _reg_read_1(EXTINTR_MASK1);
while (_reg_read_1(EXTINTR_STAT1) & MASK1_INT12)
_r = _reg_read_1((reg)); \
_r = _reg_read_1((reg)); \
reg = _reg_read_1(SH7709_PGDR);
_r = _reg_read_1((reg)); \
_r = _reg_read_1((reg)); \
while (_reg_read_1(SSUMCI_SPISR) == 0x00)
return _reg_read_1(SSUMCI_SPIBR);
reg = _reg_read_1(SH7709_SCPDR);
if ((_reg_read_1(SSUMCI_SPIDR) & 0x0f) != 5) {
c = _reg_read_1(SSUMCI_SPIDR);
#define IS_SH7706LSR (_reg_read_1(T_SH7706LSR_ID) == 0xab)
while ((_reg_read_1(SH3_SCSSR) & SCSSR_TDRE) == 0)
_reg_read_1(SH3_SCSSR) & ~SCSSR_TDRE); \
_reg_read_1(SH3_SCSSR2) & ~(SCSSR2_TDFE | SCSSR2_TEND)); \
DPRINTF((TEXT("IRR0 0x%08x\n"), _reg_read_1(SH3_IRR0)));
DPRINTF((TEXT("IRR1 0x%08x\n"), _reg_read_1(SH3_IRR1)));
DPRINTF((TEXT("IRR2 0x%08x\n"), _reg_read_1(SH3_IRR2)));
bitdisp(_reg_read_1(SH3_P##x##DR))
bitdisp(_reg_read_1(SH3_SCPDR));
r8 = _reg_read_1(SH3_TOCR);
r8 = _reg_read_1(SH3_TSTR);
r8 = _reg_read_1(HD64461_PCC0ISR_REG8);
r8 = _reg_read_1(HD64461_PCC0GCR_REG8);
r8 = _reg_read_1(HD64461_PCC0CSCR_REG8);
r8 = _reg_read_1(HD64461_PCC0CSCIER_REG8);
r8 = _reg_read_1(HD64461_PCC0SCR_REG8);
r8 = _reg_read_1(HD64461_PCC1ISR_REG8);
r8 = _reg_read_1(HD64461_PCC1GCR_REG8);
r8 = _reg_read_1(HD64461_PCC1CSCR_REG8);
r8 = _reg_read_1(HD64461_PCC1CSCIER_REG8);
r8 = _reg_read_1(HD64461_PCC1SCR_REG8);
r8 = _reg_read_1(HD64461_PCCP0OCR_REG8);
r8 = _reg_read_1(HD64461_PCCP1OCR_REG8);
r8 = _reg_read_1(HD64461_PCCPGCR_REG8);
return (uint32_t)_reg_read_1(va);
pgdr = _reg_read_1(SH7709_PGDR);
irr0 = _reg_read_1(SH7709_IRR0);
return _reg_read_1(SH7709_PGDR) & PGDR_MAIN_BATTERY_OUT;
return _reg_read_1(SH7709_PJDR) & PJDR_AC_POWER_OUT;
return _reg_read_1(SH7709_PLDR) & PLDR_BATTERY_CHARGED;
irr0 = _reg_read_1(SH7709_IRR0);
phdr = _reg_read_1(SH7709_PHDR);
phdr = _reg_read_1(SH7709_PHDR);
irr0 = _reg_read_1(SH7709_IRR0);
phdr = _reg_read_1(SH7709_PHDR);
phdr = _reg_read_1(SH7709_PHDR);
scpdr = _reg_read_1(SH7709_SCPDR);
scpdr = _reg_read_1(SH7709_SCPDR);
scpdr = _reg_read_1(SH7709_SCPDR);
data = _reg_read_1(SH7709_PFDR)
| (_reg_read_1(SH7709_PCDR) << 8);
data = _reg_read_1(SH7709_PGDR) | (_reg_read_1(SH7709_PHDR) << 8);
cd = _reg_read_1(SH7709_PCDR) & ~PFCKBD_HITACHI_PCDR_SCN_MASK;
dd = _reg_read_1(SH7709_PDDR) & ~PFCKBD_HITACHI_PDDR_SCN_MASK;
ed = _reg_read_1(SH7709_PEDR) & ~PFCKBD_HITACHI_PEDR_SCN_MASK;
(_reg_read_1(SH7709_PCDR) & PFCKBD_HITACHI_PCDR_SNS_MASK)
| (_reg_read_1(SH7709_PFDR) & PFCKBD_HITACHI_PFDR_SNS_MASK);
cd = _reg_read_1(SH7709_PCDR) & ~PFCKBD_HITACHI_PCDR_SCN_MASK;
dd = _reg_read_1(SH7709_PDDR) & ~PFCKBD_HITACHI_PDDR_SCN_MASK;
ed = _reg_read_1(SH7709_PEDR) & ~PFCKBD_HITACHI_PEDR_SCN_MASK;
while (_reg_read_1(SH7709_PCDR) & PFCKBD_HITACHI_PCDR_SNS_MASK & 0x01);
bcr0 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG0);
bcr1 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG1);
bcr2 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG2);
bcr1 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG1);
bcr2 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG2);
pddr = _reg_read_1(SH7709_PDDR);
bcr0 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG0);
bcr0 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG0);
(void)_reg_read_1(PSH3LCD_BRIGHTNESS_REG1);
(void)_reg_read_1(PSH3LCD_BRIGHTNESS_REG2);
phdr = _reg_read_1(SH7709_PHDR);
irr0 = _reg_read_1(SH7709_IRR0);
scpdr = _reg_read_1(SH7709_SCPDR);
irr0 = _reg_read_1(SH7709_IRR0);
scpdr = _reg_read_1(SH7709_SCPDR);
phdr = _reg_read_1(SH7709_PHDR);
phdr = _reg_read_1(SH7709_PHDR);
return _reg_read_1(SH7709_SCPDR) & PSH3PWR_PLUG_OUT;
irr0 = _reg_read_1(SH7709_IRR0);
phdr = _reg_read_1(SH7709_PHDR);
phdr = _reg_read_1(SH7709_PHDR);
irr0 = _reg_read_1(SH7709_IRR0);
phdr = _reg_read_1(SH7709_PHDR);
scpdr = _reg_read_1(SH7709_SCPDR);
scpdr = _reg_read_1(SH7709_SCPDR);
scpdr = _reg_read_1(SH7709_SCPDR);
status = (int8_t)_reg_read_1(LANDISK_BTNSTAT);
status = (int8_t)_reg_read_1(LANDISK_BTNSTAT);
inten = _reg_read_1(LANDISK_INTEN);
if (_reg_read_1(SMAP_RXFIFO_FRAME_REG8) > 0)
sc->tx_desc_cnt > _reg_read_1(SMAP_TXFIFO_FRAME_REG8))
while ((_reg_read_1(a) & SMAP_FIFO_RESET) && --retry > 0)
_reg_read_1(SMAP_TXFIFO_FRAME_REG8),
_reg_read_1(SMAP_RXFIFO_FRAME_REG8), __sc->tx_desc_cnt,
ret = (_reg_read_1(SPD_IO_DATA_REG8) >> 4) & 0x1;
uint8_t r = _reg_read_1(SH_(RCR1));
year = _reg_read_1(SH3_RYRCNT);
dt->dt_ ## x = bcdtobin(_reg_read_1(SH_(R ## y ## CNT)))
} while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);
r = _reg_read_1(SH_(RCR2));
r = _reg_read_1(SH_(RCR2));