include/bitstring.h

100

bit_clear(_name, _start); \

include/bitstring.h

107

bitstr_t *_name = name; \

include/bitstring.h

110

bit_set(_name, _start); \

include/bitstring.h

117

const bitstr_t *_name = name; \

include/bitstring.h

121

if (!bit_test(_name, _bit)) { \

include/bitstring.h

130

const bitstr_t *_name = name; \

include/bitstring.h

134

if (bit_test(_name, _bit)) { \

include/bitstring.h

97

bitstr_t *_name = name; \

sbin/newfs_msdos/mkfs_msdos.h

60

#define AOPT(_opt, _type, _name, _min, _desc) _type _name;

sbin/newfs_msdos/newfs_msdos.c

279

#define AOPT(_opt, _type, _name, _min, _desc) { _opt, _desc },

sys/arch/arm/amlogic/meson_clk.h

105

#define MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, _flags) \

sys/arch/arm/amlogic/meson_clk.h

108

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

118

#define MESON_CLK_GATE(_id, _name, _pname, _reg, _bit) \

sys/arch/arm/amlogic/meson_clk.h

119

MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, 0)

sys/arch/arm/amlogic/meson_clk.h

142

#define MESON_CLK_DIV(_id, _name, _parent, _reg, _div, _flags) \

sys/arch/arm/amlogic/meson_clk.h

145

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

172

#define MESON_CLK_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \

sys/arch/arm/amlogic/meson_clk.h

175

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

199

#define MESON_CLK_MUX_RATE(_id, _name, _parents, _reg, _sel, \

sys/arch/arm/amlogic/meson_clk.h

203

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

215

#define MESON_CLK_MUX(_id, _name, _parents, _reg, _sel, _flags) \

sys/arch/arm/amlogic/meson_clk.h

218

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

262

#define MESON_CLK_PLL_RATE(_id, _name, _parent, _enable, _m, _n, _frac, _l, \

sys/arch/arm/amlogic/meson_clk.h

266

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

280

#define MESON_CLK_PLL(_id, _name, _parent, _enable, _m, _n, _frac, _l, \

sys/arch/arm/amlogic/meson_clk.h

284

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

315

#define MESON_CLK_MPLL(_id, _name, _parent, _sdm, _sdm_enable, _n2, \

sys/arch/arm/amlogic/meson_clk.h

319

.base.name = (_name), \

sys/arch/arm/amlogic/meson_clk.h

79

#define MESON_CLK_FIXED(_id, _name, _rate) \

sys/arch/arm/amlogic/meson_clk.h

82

.base.name = (_name), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

337

#define GPIO_MUX_PINCTRL_GROUP(_name, _reg, _off, _group, _func) \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

338

{ .name = _name, .reg = CBUS_REG(_reg), .bit = (_func), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

593

#define AOBUS_MUX_PINCTRL_GROUP(_name, _bit, _group, _func) \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

594

{ .name = _name, .reg = CBUS_REG((_bit) / 8), .bit = (_func), \

sys/arch/arm/fdt/arm_fdtvar.h

41

#define _ARM_CPU_METHOD_REGISTER(_name) \

sys/arch/arm/fdt/arm_fdtvar.h

42

__link_set_add_rodata(arm_cpu_methods, __CONCAT(_name,_cpu_method));

sys/arch/arm/fdt/arm_fdtvar.h

44

#define ARM_CPU_METHOD(_name, _compat, _enable) \

sys/arch/arm/fdt/arm_fdtvar.h

45

static const struct arm_cpu_method __CONCAT(_name,_cpu_method) = { \

sys/arch/arm/fdt/arm_fdtvar.h

49

_ARM_CPU_METHOD_REGISTER(_name)

sys/arch/arm/nvidia/tegra124_car.c

292

#define CLK_FIXED(_name, _rate) { \

sys/arch/arm/nvidia/tegra124_car.c

293

.base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \

sys/arch/arm/nvidia/tegra124_car.c

297

#define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \

sys/arch/arm/nvidia/tegra124_car.c

298

.base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \

sys/arch/arm/nvidia/tegra124_car.c

310

#define CLK_MUX(_name, _reg, _bits, _p) { \

sys/arch/arm/nvidia/tegra124_car.c

311

.base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \

sys/arch/arm/nvidia/tegra124_car.c

322

#define CLK_FIXED_DIV(_name, _parent, _div) { \

sys/arch/arm/nvidia/tegra124_car.c

323

.base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \

sys/arch/arm/nvidia/tegra124_car.c

332

#define CLK_DIV(_name, _parent, _reg, _bits) { \

sys/arch/arm/nvidia/tegra124_car.c

333

.base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \

sys/arch/arm/nvidia/tegra124_car.c

343

#define CLK_GATE(_name, _parent, _set, _clr, _bits) { \

sys/arch/arm/nvidia/tegra124_car.c

344

.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \

sys/arch/arm/nvidia/tegra124_car.c

356

#define CLK_GATE_L(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra124_car.c

357

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra124_car.c

361

#define CLK_GATE_H(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra124_car.c

362

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra124_car.c

366

#define CLK_GATE_U(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra124_car.c

367

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra124_car.c

371

#define CLK_GATE_V(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra124_car.c

372

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra124_car.c

376

#define CLK_GATE_W(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra124_car.c

377

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra124_car.c

381

#define CLK_GATE_X(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra124_car.c

382

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra124_car.c

386

#define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \

sys/arch/arm/nvidia/tegra124_car.c

387

CLK_GATE(_name, _parent, _reg, _reg, _bits)

sys/arch/arm/nvidia/tegra210_car.c

304

#define CLK_FIXED(_name, _rate) { \

sys/arch/arm/nvidia/tegra210_car.c

305

.base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \

sys/arch/arm/nvidia/tegra210_car.c

309

#define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \

sys/arch/arm/nvidia/tegra210_car.c

310

.base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \

sys/arch/arm/nvidia/tegra210_car.c

322

#define CLK_MUX(_name, _reg, _bits, _p) { \

sys/arch/arm/nvidia/tegra210_car.c

323

.base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \

sys/arch/arm/nvidia/tegra210_car.c

334

#define CLK_FIXED_DIV(_name, _parent, _div) { \

sys/arch/arm/nvidia/tegra210_car.c

335

.base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \

sys/arch/arm/nvidia/tegra210_car.c

344

#define CLK_DIV(_name, _parent, _reg, _bits) { \

sys/arch/arm/nvidia/tegra210_car.c

345

.base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \

sys/arch/arm/nvidia/tegra210_car.c

355

#define CLK_GATE(_name, _parent, _set, _clr, _bits) { \

sys/arch/arm/nvidia/tegra210_car.c

356

.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \

sys/arch/arm/nvidia/tegra210_car.c

368

#define CLK_GATE_L(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

369

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra210_car.c

373

#define CLK_GATE_H(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

374

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra210_car.c

378

#define CLK_GATE_U(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

379

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra210_car.c

383

#define CLK_GATE_V(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

384

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra210_car.c

388

#define CLK_GATE_W(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

389

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra210_car.c

393

#define CLK_GATE_X(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

394

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra210_car.c

398

#define CLK_GATE_Y(_name, _parent, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

399

CLK_GATE(_name, _parent, \

sys/arch/arm/nvidia/tegra210_car.c

404

#define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \

sys/arch/arm/nvidia/tegra210_car.c

405

CLK_GATE(_name, _parent, _reg, _reg, _bits)

sys/arch/arm/nxp/imx6_ccmvar.h

161

#define CLK_FIXED(_name, _rate) { \

sys/arch/arm/nxp/imx6_ccmvar.h

162

.base = { .name = (_name) }, \

sys/arch/arm/nxp/imx6_ccmvar.h

171

#define CLK_FIXED_FACTOR(_name, _parent, _div, _mult) { \

sys/arch/arm/nxp/imx6_ccmvar.h

172

.base = { .name = (_name) }, \

sys/arch/arm/nxp/imx6_ccmvar.h

183

#define CLK_PFD(_name, _parent, _reg, _index) { \

sys/arch/arm/nxp/imx6_ccmvar.h

184

.base = { .name = (_name) }, \

sys/arch/arm/nxp/imx6_ccmvar.h

195

#define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \

sys/arch/arm/nxp/imx6_ccmvar.h

196

.base = { .name = (_name) }, \

sys/arch/arm/nxp/imx6_ccmvar.h

210

#define CLK_DIV(_name, _parent, _reg, _mask) { \

sys/arch/arm/nxp/imx6_ccmvar.h

211

.base = { .name = (_name) }, \

sys/arch/arm/nxp/imx6_ccmvar.h

224

#define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \

sys/arch/arm/nxp/imx6_ccmvar.h

225

.base = { .name = (_name) }, \

sys/arch/arm/nxp/imx6_ccmvar.h

240

#define CLK_DIV_TABLE(_name, _parent, _reg, _mask, _tbl) { \

sys/arch/arm/nxp/imx6_ccmvar.h

241

.base = { .name = (_name) }, \

sys/arch/arm/nxp/imx6_ccmvar.h

255

#define CLK_MUX(_name, _parents, _base, _reg, _mask) { \

sys/arch/arm/nxp/imx6_ccmvar.h

256

.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \

sys/arch/arm/nxp/imx6_ccmvar.h

270

#define CLK_MUX_BUSY(_name, _parents, _reg, _mask, _busy_reg, _busy_mask) { \

sys/arch/arm/nxp/imx6_ccmvar.h

271

.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \

sys/arch/arm/nxp/imx6_ccmvar.h

287

#define CLK_GATE(_name, _parent, _base, _reg, _mask) { \

sys/arch/arm/nxp/imx6_ccmvar.h

288

.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \

sys/arch/arm/nxp/imx6_ccmvar.h

301

#define CLK_GATE_EXCLUSIVE(_name, _parent, _base, _reg, _mask, _exclusive_mask) { \

sys/arch/arm/nxp/imx6_ccmvar.h

302

.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \

sys/arch/arm/nxp/imx7d_ccm.c

101

#define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \

sys/arch/arm/nxp/imx7d_ccm.c

102

IMX_MUX_INDEX(_id, REGIDX_ANATOP, _name, _parents, _reg, _mask)

sys/arch/arm/nxp/imx7d_ccm.c

103

#define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \

sys/arch/arm/nxp/imx7d_ccm.c

104

IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)

sys/arch/arm/nxp/imx7d_ccm.c

105

#define ANATOP_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \

sys/arch/arm/nxp/imx7d_ccm.c

106

IMX_PLL_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _div_mask, _flags)

sys/arch/arm/nxp/imx_ccm.h

102

#define IMX_ROOT_GATE(_id, _name, _pname, _reg) \

sys/arch/arm/nxp/imx_ccm.h

103

IMX_ROOT_GATE_INDEX(_id, 0, _name, _pname, _reg)

sys/arch/arm/nxp/imx_ccm.h

104

#define IMX_ROOT_GATE_INDEX(_id, _regidx, _name, _pname, _reg) \

sys/arch/arm/nxp/imx_ccm.h

105

IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, __BITS(1,0))

sys/arch/arm/nxp/imx_ccm.h

124

#define IMX_COMPOSITE(_id, _name, _parents, _reg, _flags) \

sys/arch/arm/nxp/imx_ccm.h

125

IMX_COMPOSITE_INDEX(_id, 0, _name, _parents, _reg, _flags)

sys/arch/arm/nxp/imx_ccm.h

127

#define IMX_COMPOSITE_INDEX(_id, _regidx, _name, _parents, _reg, _flags) \

sys/arch/arm/nxp/imx_ccm.h

132

.base.name = (_name), \

sys/arch/arm/nxp/imx_ccm.h

161

#define IMX_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \

sys/arch/arm/nxp/imx_ccm.h

162

IMX_PLL_INDEX(_id, 0, _name, _parent, _reg, _div_mask, _flags)

sys/arch/arm/nxp/imx_ccm.h

163

#define IMX_PLL_INDEX(_id, _regidx, _name, _parent, _reg, _div_mask, _flags) \

sys/arch/arm/nxp/imx_ccm.h

168

.base.name = (_name), \

sys/arch/arm/nxp/imx_ccm.h

187

#define IMX_FIXED(_id, _name, _rate) \

sys/arch/arm/nxp/imx_ccm.h

191

.base.name = (_name), \

sys/arch/arm/nxp/imx_ccm.h

209

#define IMX_FIXED_FACTOR(_id, _name, _parent, _mult, _div) \

sys/arch/arm/nxp/imx_ccm.h

213

.base.name = (_name), \

sys/arch/arm/nxp/imx_ccm.h

235

#define IMX_MUX(_id, _name, _parents, _reg, _sel) \

sys/arch/arm/nxp/imx_ccm.h

236

IMX_MUX_INDEX(_id, 0, _name, _parents, _reg, _sel)

sys/arch/arm/nxp/imx_ccm.h

238

#define IMX_MUX_INDEX(_id, _regidx, _name, _parents, _reg, _sel) \

sys/arch/arm/nxp/imx_ccm.h

243

.base.name = (_name), \

sys/arch/arm/nxp/imx_ccm.h

268

#define IMX_DIV(_id, _name, _parent, _reg, _mask, _flags) \

sys/arch/arm/nxp/imx_ccm.h

269

IMX_DIV_INDEX(_id, 0, _name, _parent, _reg, _mask, _flags)

sys/arch/arm/nxp/imx_ccm.h

270

#define IMX_DIV_INDEX(_id, _regidx, _name, _parent, _reg, _mask, _flags) \

sys/arch/arm/nxp/imx_ccm.h

275

.base.name = (_name), \

sys/arch/arm/nxp/imx_ccm.h

61

#define IMX_EXTCLK(_id, _name) \

sys/arch/arm/nxp/imx_ccm.h

65

.base.name = (_name), \

sys/arch/arm/nxp/imx_ccm.h

67

.u.extclk = (_name), \

sys/arch/arm/nxp/imx_ccm.h

87

#define IMX_GATE(_id, _name, _pname, _reg, _mask) \

sys/arch/arm/nxp/imx_ccm.h

88

IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)

sys/arch/arm/nxp/imx_ccm.h

89

#define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \

sys/arch/arm/nxp/imx_ccm.h

94

.base.name = (_name), \

sys/arch/arm/rockchip/rk3399_cru.c

340

#define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \

sys/arch/arm/rockchip/rk3399_cru.c

344

.base.name = (_name), \

sys/arch/arm/rockchip/rk3399_pmucru.c

267

#define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \

sys/arch/arm/rockchip/rk3399_pmucru.c

271

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

111

#define RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, _flags) \

sys/arch/arm/rockchip/rk_cru.h

115

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

131

#define RK_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \

sys/arch/arm/rockchip/rk_cru.h

132

RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, 0)

sys/arch/arm/rockchip/rk_cru.h

134

#define RK3288_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \

sys/arch/arm/rockchip/rk_cru.h

135

RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, RK_PLL_RK3288)

sys/arch/arm/rockchip/rk_cru.h

137

#define RK3588_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \

sys/arch/arm/rockchip/rk_cru.h

138

RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, RK_PLL_RK3588)

sys/arch/arm/rockchip/rk_cru.h

190

#define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \

sys/arch/arm/rockchip/rk_cru.h

194

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

212

#define _RK_CPU_COMMON_INITIALIZER(_id, _name, _parents, \

sys/arch/arm/rockchip/rk_cru.h

216

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

231

#define RK_CPU(_id, _name, _parents, _mux_reg, _mux_mask, _mux_main, _mux_alt, \

sys/arch/arm/rockchip/rk_cru.h

234

_RK_CPU_COMMON_INITIALIZER(_id, _name, _parents, \

sys/arch/arm/rockchip/rk_cru.h

240

#define RK_CPU_CORE2(_id, _name, _parents, \

sys/arch/arm/rockchip/rk_cru.h

246

_RK_CPU_COMMON_INITIALIZER(_id, _name, _parents, \

sys/arch/arm/rockchip/rk_cru.h

254

#define RK_CPU_CORE4(_id, _name, _parents, \

sys/arch/arm/rockchip/rk_cru.h

262

_RK_CPU_COMMON_INITIALIZER(_id, _name, _parents, \

sys/arch/arm/rockchip/rk_cru.h

299

#define _RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _frac_reg, _flags) \

sys/arch/arm/rockchip/rk_cru.h

303

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

321

#define RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _flags) \

sys/arch/arm/rockchip/rk_cru.h

322

_RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, 0, _flags)

sys/arch/arm/rockchip/rk_cru.h

324

#define RK_COMPOSITE_HALF(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _flags) \

sys/arch/arm/rockchip/rk_cru.h

325

_RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, 0, (_flags) | RK_COMPOSITE_HALFDIV)

sys/arch/arm/rockchip/rk_cru.h

327

#define RK_COMPOSITE_NOMUX(_id, _name, _parent, _div_reg, _div_mask, _gate_reg, _gate_mask, _flags) \

sys/arch/arm/rockchip/rk_cru.h

328

_RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, _gate_reg, _gate_mask, 0, _flags)

sys/arch/arm/rockchip/rk_cru.h

330

#define RK_COMPOSITE_NODIV(_id, _name, _parents, _muxdiv_reg, _mux_mask, _gate_reg, _gate_mask, _flags) \

sys/arch/arm/rockchip/rk_cru.h

331

_RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, 0, _gate_reg, _gate_mask, 0, _flags)

sys/arch/arm/rockchip/rk_cru.h

333

#define RK_COMPOSITE_NOGATE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _flags) \

sys/arch/arm/rockchip/rk_cru.h

334

_RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, 0, 0, 0, _flags)

sys/arch/arm/rockchip/rk_cru.h

336

#define RK_COMPOSITE_FRAC(_id, _name, _parent, _frac_reg, _flags) \

sys/arch/arm/rockchip/rk_cru.h

337

_RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, 0, 0, 0, 0, 0, _frac_reg, (_flags) | RK_COMPOSITE_FRACDIV)

sys/arch/arm/rockchip/rk_cru.h

339

#define RK_DIV(_id, _name, _parent, _div_reg, _div_mask, _flags) \

sys/arch/arm/rockchip/rk_cru.h

340

_RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, 0, 0, 0, _flags)

sys/arch/arm/rockchip/rk_cru.h

355

#define RK_GATE(_id, _name, _pname, _reg, _bit) \

sys/arch/arm/rockchip/rk_cru.h

359

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

368

#define RK_SECURE_GATE(_id, _name, _pname) \

sys/arch/arm/rockchip/rk_cru.h

372

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

391

#define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \

sys/arch/arm/rockchip/rk_cru.h

395

.base.name = (_name), \

sys/arch/arm/rockchip/rk_cru.h

405

#define RK_MUX(_id, _name, _parents, _reg, _mask) \

sys/arch/arm/rockchip/rk_cru.h

406

RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0)

sys/arch/arm/rockchip/rk_cru.h

407

#define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \

sys/arch/arm/rockchip/rk_cru.h

408

RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, RK_MUX_GRF)

sys/arch/arm/samsung/exynos5410_clock.c

159

#define CLK_FIXED(_name, _rate) { \

sys/arch/arm/samsung/exynos5410_clock.c

160

.base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \

sys/arch/arm/samsung/exynos5410_clock.c

164

#define CLK_PLL35XX(_name, _parent, _lock, _con0) { \

sys/arch/arm/samsung/exynos5410_clock.c

165

.base = { .name = (_name) }, \

sys/arch/arm/samsung/exynos5410_clock.c

176

#define CLK_PLL2650X(_name, _parent, _lock, _con0, _con1) { \

sys/arch/arm/samsung/exynos5410_clock.c

177

.base = { .name = (_name) }, \

sys/arch/arm/samsung/exynos5410_clock.c

189

#define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \

sys/arch/arm/samsung/exynos5410_clock.c

190

.base = { .name = (_name), .flags = (_f) }, \

sys/arch/arm/samsung/exynos5410_clock.c

203

#define CLK_MUXA(_name, _alias, _reg, _bits, _p) \

sys/arch/arm/samsung/exynos5410_clock.c

204

CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)

sys/arch/arm/samsung/exynos5410_clock.c

206

#define CLK_MUX(_name, _reg, _bits, _p) \

sys/arch/arm/samsung/exynos5410_clock.c

207

CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)

sys/arch/arm/samsung/exynos5410_clock.c

209

#define CLK_DIVF(_name, _parent, _reg, _bits, _f) { \

sys/arch/arm/samsung/exynos5410_clock.c

210

.base = { .name = (_name), .flags = (_f) }, \

sys/arch/arm/samsung/exynos5410_clock.c

221

#define CLK_DIV(_name, _parent, _reg, _bits) \

sys/arch/arm/samsung/exynos5410_clock.c

222

CLK_DIVF(_name, _parent, _reg, _bits, 0)

sys/arch/arm/samsung/exynos5410_clock.c

224

#define CLK_GATE(_name, _parent, _reg, _bits, _f) { \

sys/arch/arm/samsung/exynos5410_clock.c

225

.base = { .name = (_name), .flags = (_f) }, \

sys/arch/arm/samsung/exynos5422_clock.c

275

#define CLK_FIXED(_name, _rate) { \

sys/arch/arm/samsung/exynos5422_clock.c

276

.base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \

sys/arch/arm/samsung/exynos5422_clock.c

280

#define CLK_PLL35XX(_name, _parent, _lock, _con0) { \

sys/arch/arm/samsung/exynos5422_clock.c

281

.base = { .name = (_name) }, \

sys/arch/arm/samsung/exynos5422_clock.c

292

#define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \

sys/arch/arm/samsung/exynos5422_clock.c

293

.base = { .name = (_name), .flags = (_f) }, \

sys/arch/arm/samsung/exynos5422_clock.c

306

#define CLK_MUXA(_name, _alias, _reg, _bits, _p) \

sys/arch/arm/samsung/exynos5422_clock.c

307

CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)

sys/arch/arm/samsung/exynos5422_clock.c

309

#define CLK_MUX(_name, _reg, _bits, _p) \

sys/arch/arm/samsung/exynos5422_clock.c

310

CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)

sys/arch/arm/samsung/exynos5422_clock.c

312

#define CLK_DIV(_name, _parent, _reg, _bits) { \

sys/arch/arm/samsung/exynos5422_clock.c

313

.base = { .name = (_name) }, .type = EXYNOS_CLK_DIV, \

sys/arch/arm/samsung/exynos5422_clock.c

323

#define CLK_GATE(_name, _parent, _reg, _bits, _f) { \

sys/arch/arm/samsung/exynos5422_clock.c

324

.base = { .name = (_name), .flags = (_f) }, \

sys/arch/arm/sunxi/sunxi_ccu.h

129

#define SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \

sys/arch/arm/sunxi/sunxi_ccu.h

133

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

150

#define SUNXI_CCU_NKMP(_id, _name, _parent, _reg, _n, _k, _m, \

sys/arch/arm/sunxi/sunxi_ccu.h

152

SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \

sys/arch/arm/sunxi/sunxi_ccu.h

182

#define SUNXI_CCU_NM(_id, _name, _parents, _reg, _n, _m, _sel, \

sys/arch/arm/sunxi/sunxi_ccu.h

186

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

228

#define SUNXI_CCU_DIV(_id, _name, _parents, _reg, _div, \

sys/arch/arm/sunxi/sunxi_ccu.h

230

SUNXI_CCU_DIV_GATE(_id, _name, _parents, _reg, _div, \

sys/arch/arm/sunxi/sunxi_ccu.h

233

#define SUNXI_CCU_DIV_GATE(_id, _name, _parents, _reg, _div, \

sys/arch/arm/sunxi/sunxi_ccu.h

237

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

288

#define SUNXI_CCU_PREDIV(_id, _name, _parents, _reg, _prediv, \

sys/arch/arm/sunxi/sunxi_ccu.h

290

SUNXI_CCU_PREDIV_FIXED(_id, _name, _parents, _reg, _prediv, \

sys/arch/arm/sunxi/sunxi_ccu.h

293

#define SUNXI_CCU_PREDIV_FIXED(_id, _name, _parents, _reg, _prediv, \

sys/arch/arm/sunxi/sunxi_ccu.h

297

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

326

#define SUNXI_CCU_PHASE(_id, _name, _parent, _reg, _mask) \

sys/arch/arm/sunxi/sunxi_ccu.h

329

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

351

#define SUNXI_CCU_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \

sys/arch/arm/sunxi/sunxi_ccu.h

354

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

391

#define SUNXI_CCU_FRACTIONAL(_id, _name, _parent, _reg, _m, _m_min, _m_max, \

sys/arch/arm/sunxi/sunxi_ccu.h

396

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

431

#define SUNXI_CCU_MUX(_id, _name, _parents, _reg, _sel, _flags) \

sys/arch/arm/sunxi/sunxi_ccu.h

434

.base.name = (_name), \

sys/arch/arm/sunxi/sunxi_ccu.h

81

#define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \

sys/arch/arm/sunxi/sunxi_ccu.h

84

.base.name = (_name), \

sys/arch/arm/ti/am18xx_pllc.c

103

#define PLLC_CLK(_i, _name, _rate) \

sys/arch/arm/ti/am18xx_pllc.c

105

.clk_base.name = (_name), \

sys/arch/arm/ti/am18xx_psc.c

106

#define PSC_CLK(_i, _name, _p) \

sys/arch/arm/ti/am18xx_psc.c

110

.clk_base.name = (_name), \

sys/arch/arm/ti/am3_prcm.c

129

#define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \

sys/arch/arm/ti/am3_prcm.c

130

TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable)

sys/arch/arm/ti/am3_prcm.c

131

#define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \

sys/arch/arm/ti/am3_prcm.c

132

TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display)

sys/arch/arm/ti/am3_prcm.c

133

#define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \

sys/arch/arm/ti/am3_prcm.c

134

TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable)

sys/arch/arm/ti/omap3_cm.c

100

TI_PRCM_HWMOD_MASK((_name), CM_USBHOST_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))

sys/arch/arm/ti/omap3_cm.c

101

#define OMAP3_CM_HWMOD_NOP(_name, _parent) \

sys/arch/arm/ti/omap3_cm.c

102

TI_PRCM_HWMOD_MASK((_name), 0, 0, (_parent), omap3_cm_hwmod_nopenable, 0)

sys/arch/arm/ti/omap3_cm.c

91

#define OMAP3_CM_HWMOD_CORE1(_name, _bit, _parent, _flags) \

sys/arch/arm/ti/omap3_cm.c

92

TI_PRCM_HWMOD_MASK((_name), CM_CORE1_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))

sys/arch/arm/ti/omap3_cm.c

93

#define OMAP3_CM_HWMOD_CORE3(_name, _bit, _parent, _flags) \

sys/arch/arm/ti/omap3_cm.c

94

TI_PRCM_HWMOD_MASK((_name), CM_CORE3_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))

sys/arch/arm/ti/omap3_cm.c

95

#define OMAP3_CM_HWMOD_WKUP(_name, _bit, _parent, _flags) \

sys/arch/arm/ti/omap3_cm.c

96

TI_PRCM_HWMOD_MASK((_name), CM_WKUP_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))

sys/arch/arm/ti/omap3_cm.c

97

#define OMAP3_CM_HWMOD_PER(_name, _bit, _parent, _flags) \

sys/arch/arm/ti/omap3_cm.c

98

TI_PRCM_HWMOD_MASK((_name), CM_PER_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))

sys/arch/arm/ti/omap3_cm.c

99

#define OMAP3_CM_HWMOD_USBHOST(_name, _bit, _parent, _flags) \

sys/arch/arm/ti/omap4_prcm.c

130

#define OMAP4_PRCM_HWMOD_CM1_ABE(_name, _reg, _parent) \

sys/arch/arm/ti/omap4_prcm.c

131

TI_PRCM_HWMOD((_name), CM1_ABE + (_reg), (_parent), omap4_prcm_hwmod_enable)

sys/arch/arm/ti/omap4_prcm.c

132

#define OMAP4_PRCM_HWMOD_CM2_L3INIT(_name, _reg, _parent) \

sys/arch/arm/ti/omap4_prcm.c

133

TI_PRCM_HWMOD((_name), CM2_L3INIT + (_reg), (_parent), omap4_prcm_hwmod_enable)

sys/arch/arm/ti/omap4_prcm.c

134

#define OMAP4_PRCM_HWMOD_CM2_L3INIT_AUTO(_name, _reg, _parent) \

sys/arch/arm/ti/omap4_prcm.c

135

TI_PRCM_HWMOD((_name), CM2_L3INIT + (_reg), (_parent), omap4_prcm_hwmod_enable_auto)

sys/arch/arm/ti/omap4_prcm.c

136

#define OMAP4_PRCM_HWMOD_CM2_L4PER(_name, _reg, _parent) \

sys/arch/arm/ti/omap4_prcm.c

137

TI_PRCM_HWMOD((_name), CM2_L4PER + (_reg), (_parent), omap4_prcm_hwmod_enable)

sys/arch/arm/ti/omap4_prcm.c

138

#define OMAP4_PRCM_HWMOD_CM2_L4PER_AUTO(_name, _reg, _parent) \

sys/arch/arm/ti/omap4_prcm.c

139

TI_PRCM_HWMOD((_name), CM2_L4PER + (_reg), (_parent), omap4_prcm_hwmod_enable_auto)

sys/arch/arm/ti/omap4_prcm.c

140

#define OMAP4_PRCM_HWMOD_CM_WKUP(_name, _reg, _parent) \

sys/arch/arm/ti/omap4_prcm.c

141

TI_PRCM_HWMOD((_name), CM_WKUP + (_reg), (_parent), omap4_prcm_hwmod_enable)

sys/arch/arm/ti/omap4_prcm.c

142

#define OMAP4_PRCM_HWMOD_CM_WKUP_AUTO(_name, _reg, _parent) \

sys/arch/arm/ti/omap4_prcm.c

143

TI_PRCM_HWMOD((_name), CM_WKUP + (_reg), (_parent), omap4_prcm_hwmod_enable_auto)

sys/arch/arm/ti/ti_prcm.h

126

#define TI_PRCM_FIXED_FACTOR(_name, _mult, _div, _parent) \

sys/arch/arm/ti/ti_prcm.h

128

.type = TI_PRCM_FIXED_FACTOR, .base.name = (_name), \

sys/arch/arm/ti/ti_prcm.h

143

#define TI_PRCM_HWMOD(_name, _reg, _parent, _enable) \

sys/arch/arm/ti/ti_prcm.h

144

TI_PRCM_HWMOD_MASK(_name, _reg, 0, _parent, _enable, 0)

sys/arch/arm/ti/ti_prcm.h

146

#define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \

sys/arch/arm/ti/ti_prcm.h

148

.type = TI_PRCM_HWMOD, .base.name = (_name), \

sys/arch/arm/ti/ti_prcm.h

97

#define TI_PRCM_FIXED(_name, _rate) \

sys/arch/arm/ti/ti_prcm.h

99

.type = TI_PRCM_FIXED, .base.name = (_name), \

sys/arch/evbppc/nintendo/dev/hwgpio.c

47

#define PIN(_num, _name, _caps) \

sys/arch/evbppc/nintendo/dev/hwgpio.c

50

.pin_defname = (_name), \

sys/arch/hpc/stand/hpcboot/menu/tabwindow.cpp

131

(_app._instance, _name, _base._window,

sys/arch/hpc/stand/hpcboot/menu/tabwindow.h

81

const TCHAR *_name;

sys/arch/hpc/stand/hpcboot/menu/tabwindow.h

84

: Window(base._app, base._window), _base(base), _name(name) {

sys/arch/ia64/stand/common/bitstring.h

101

_name[_startbyte] |= 0xff << ((_start)&0x7); \

sys/arch/ia64/stand/common/bitstring.h

103

_name[_startbyte] = 0xff; \

sys/arch/ia64/stand/common/bitstring.h

104

_name[_stopbyte] |= 0xff >> (7 - (_stop&0x7)); \

sys/arch/ia64/stand/common/bitstring.h

110

register bitstr_t *_name = (name); \

sys/arch/ia64/stand/common/bitstring.h

115

if (_name[_byte] != 0xff) { \

sys/arch/ia64/stand/common/bitstring.h

118

for (_lb = _name[_byte]; (_lb&0x1); \

sys/arch/ia64/stand/common/bitstring.h

129

register bitstr_t *_name = (name); \

sys/arch/ia64/stand/common/bitstring.h

134

if (_name[_byte]) { \

sys/arch/ia64/stand/common/bitstring.h

137

for (_lb = _name[_byte]; !(_lb&0x1); \

sys/arch/ia64/stand/common/bitstring.h

76

register bitstr_t *_name = (name); \

sys/arch/ia64/stand/common/bitstring.h

81

_name[_startbyte] &= ((0xff >> (8 - (_start&0x7))) | \

sys/arch/ia64/stand/common/bitstring.h

84

_name[_startbyte] &= 0xff >> (8 - (_start&0x7)); \

sys/arch/ia64/stand/common/bitstring.h

86

_name[_startbyte] = 0; \

sys/arch/ia64/stand/common/bitstring.h

87

_name[_stopbyte] &= 0xff << ((_stop&0x7) + 1); \

sys/arch/ia64/stand/common/bitstring.h

93

register bitstr_t *_name = (name); \

sys/arch/ia64/stand/common/bitstring.h

98

_name[_startbyte] |= ((0xff << (_start&0x7)) & \

sys/arch/mips/include/signal.h

90

#define _SIGCONTEXT_DEFINE(_name, _reg_t, _fp_t) \

sys/arch/riscv/starfive/jh71x0_clkc.h

111

#define JH71X0CLKC_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \

sys/arch/riscv/starfive/jh71x0_clkc.h

114

.jcc_clk.name = (_name), \

sys/arch/riscv/starfive/jh71x0_clkc.h

137

#define JH71X0CLKC_GATE(_id, _name, _pname) \

sys/arch/riscv/starfive/jh71x0_clkc.h

141

.name = (_name), \

sys/arch/riscv/starfive/jh71x0_clkc.h

171

#define JH71X0CLKC_DIV_FLAGS(_id, _name, _maxdiv, _parent, _flags) \

sys/arch/riscv/starfive/jh71x0_clkc.h

175

.name = (_name), \

sys/arch/riscv/starfive/jh71x0_clkc.h

213

#define JH71X0CLKC_FRACDIV(_id, _name, _parent) \

sys/arch/riscv/starfive/jh71x0_clkc.h

217

.name = (_name), \

sys/arch/riscv/starfive/jh71x0_clkc.h

246

#define JH71X0CLKC_MUX_FLAGSX2(_id, _name, _parents, _cflags, _mflags) \

sys/arch/riscv/starfive/jh71x0_clkc.h

250

.name = (_name), \

sys/arch/riscv/starfive/jh71x0_clkc.h

300

#define JH71X0CLKC_MUXDIV_FLAGSX2(_id, _name, _maxdiv, _parents, _cf, _mf) \

sys/arch/riscv/starfive/jh71x0_clkc.h

304

.name = (_name), \

sys/arch/riscv/starfive/jh71x0_clkc.h

340

#define JH71X0CLKC_INV(_id, _name, _pname) \

sys/arch/riscv/starfive/jh71x0_clkc.h

344

.name = (_name), \

sys/dev/fdt/fdt_console.h

46

#define FDT_CONSOLE(_name, _ops) \

sys/dev/fdt/fdt_console.h

47

static const struct fdt_console_info __CONCAT(_name,_consinfo) = { \

sys/dev/fdt/fdt_console.h

50

_FDT_CONSOLE_REGISTER(_name)

sys/dev/fdt/fdt_opp.h

40

#define FDT_OPP(_name, _compat, _suppfn) \

sys/dev/fdt/fdt_opp.h

41

static const struct fdt_opp_info __CONCAT(_name,_oppinfo) = { \

sys/dev/fdt/fdt_opp.h

45

_FDT_OPP_REGISTER(_name)

sys/dev/fdt/fdt_platform.h

47

#define FDT_PLATFORM(_name, _compat, _ops) \

sys/dev/fdt/fdt_platform.h

48

static const struct fdt_platform_info __CONCAT(_name,_platinfo) = { \

sys/dev/fdt/fdt_platform.h

52

_FDT_PLATFORM_REGISTER(_name)

sys/dev/pci/if_aq.c

1288

char sc_evcount_##name##_name[32]; \

sys/dev/pci/if_aq.c

1292

snprintf((sc)->sc_evcount_##name##_name, \

sys/dev/pci/if_aq.c

1293

sizeof((sc)->sc_evcount_##name##_name), \

sys/dev/pci/if_aq.c

1297

(sc)->sc_evcount_##name##_name); \

sys/dev/pci/if_aq.c

1302

if ((sc)->sc_evcount_##name##_name[0] != '\0') \

sys/dev/pci/ixgbe/ixgbe.h

655

#define IXGBE_CORE_LOCK_INIT(_sc, _name) \

sys/dev/pci/pvscsi.c

181

#define pvscsi_get_tunable(_sc, _name, _value) (_value)

sys/net/lagg/if_lagg_lacp.c

244

#define LACP_TLV_PARSE(_du, _st, _name, _tlvlist) \

sys/net/lagg/if_lagg_lacp.c

245

tlv_parse(&(_du)->_name, \

sys/net/lagg/if_lagg_lacp.c

246

sizeof(_st) - offsetof(_st, _name), \

sys/net80211/ieee80211_netbsd.h

108

#define IEEE80211_NODE_SAVEQ_INIT(_ni, _name) do { \

sys/net80211/ieee80211_netbsd.h

148

#define ACL_LOCK_INIT(_as, _name) \

sys/net80211/ieee80211_netbsd.h

149

IEEE80211_LOCK_INIT_IMPL(_as, _name, as_lock)

sys/net80211/ieee80211_netbsd.h

43

#define IEEE80211_LOCK_INIT_IMPL(_ic, _name, _member) \

sys/net80211/ieee80211_netbsd.h

61

#define IEEE80211_BEACON_LOCK_INIT(_ic, _name) \

sys/net80211/ieee80211_netbsd.h

62

IEEE80211_LOCK_INIT_IMPL(_ic, _name, ic_beaconlock)

sys/net80211/ieee80211_netbsd.h

77

#define IEEE80211_NODE_LOCK_INIT(_nt, _name) \

sys/net80211/ieee80211_netbsd.h

78

IEEE80211_LOCK_INIT_IMPL(_nt, _name, nt_nodelock)

sys/net80211/ieee80211_netbsd.h

94

#define IEEE80211_SCAN_LOCK_INIT(_nt, _name) \

sys/net80211/ieee80211_netbsd.h

95

IEEE80211_LOCK_INIT_IMPL(_nt, _name, nt_scanlock)

usr.sbin/cpuctl/arch/aarch64.c

127

#define FIELDNAME(_bitpos, _bitwidth, _name) \

usr.sbin/cpuctl/arch/aarch64.c

130

.name = _name

usr.sbin/cpuctl/arch/aarch64.c

132

#define FIELDINFO(_bitpos, _bitwidth, _name) \

usr.sbin/cpuctl/arch/aarch64.c

133

FIELDNAME(_bitpos, _bitwidth, _name), \

usr.sbin/makefs/msdos.c

78

#define AOPT(_opt, _type, _name, _min, _desc) { \

usr.sbin/makefs/msdos.c

80

.name = # _name, \

usr.sbin/makefs/msdos.c

86

.value = &msdos_opt->options._name, \

usr.sbin/netgroup_mkdb/netgroup_mkdb.c

61

char *_name;

usr.sbin/netgroup_mkdb/netgroup_mkdb.c

64

#define n_name _n._name

usr.sbin/npf/npfctl/npf_parse.y

459

npfctl_build_maprset($3.rg_name, $3.rg_attr, $3.rg_ifname);

usr.sbin/npf/npfctl/npf_parse.y

531

npfctl_build_group($2.rg_name, $2.rg_attr,

usr.sbin/npf/npfctl/npf_parse.y

545

npfctl_build_group($2.rg_name, $2.rg_attr | NPF_RULE_DYNAMIC,