WRITE4
WRITE4(sc, RNG200_CONTROL, ctl);
WRITE4(sc, RNG200_STATUS, 0xffffffff);
WRITE4(sc, RNG200_RBG_RESET, rbg | RBG_RESET);
WRITE4(sc, RNG200_RNG_RESET, rng | RNG_RESET);
WRITE4(sc, RNG200_RNG_RESET, rng);
WRITE4(sc, RNG200_RBG_RESET, rbg);
WRITE4(sc, RNG200_CONTROL, ctl | RNG200_RBG_ENABLE);
WRITE4(sc, RTSX_HCBAR, sc->sc_regs4[0]);
WRITE4(sc, RTSX_HCBCTLR, sc->sc_regs4[1]);
WRITE4(sc, RTSX_HDBAR, sc->sc_regs4[2]);
WRITE4(sc, RTSX_HDBCTLR, sc->sc_regs4[3]);
WRITE4(sc, RTSX_HAIMR, sc->sc_regs4[4]);
WRITE4(sc, RTSX_BIER, sc->sc_regs4[5]);
WRITE4(sc, RTSX_HCBAR, sc->sc_dmap_cmd->dm_segs[0].ds_addr);
WRITE4(sc, RTSX_HCBCTLR,
WRITE4(sc, RTSX_HDBAR, cmd->c_dmamap->dm_segs[0].ds_addr);
WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) |
WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD);
WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);
WRITE4(sc, RTSX_BIPR, status);
WRITE4(sc, RTSX_BIER, 0);
WRITE4(sc, RTSX_BIPR, status);
WRITE4(sc, RTSX_BIER,
WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY |
WRITE4(sc, RTSX_HAIMR,
WRITE4(AGP_AMD751_ATTBASE, gatt->ag_physical);
WRITE4(AGP_AMD751_ATTBASE, 0);
WRITE4(AGP_AMD751_TLBCTRL, 1);
WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
WRITE4(AGP_I810_PGTBL_CTL, 0);
WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31));
WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
WRITE4(sc, ALI_SCR, reg);
WRITE4(sc, ALI_RTSR, reg | 0x80);
WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
WRITE4(sc, ALI_FIFOCR1, 0x83838383);
WRITE4(sc, ALI_FIFOCR2, 0x83838383);
WRITE4(sc, ALI_FIFOCR3, 0x83838383);
WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
WRITE4(sc, ALI_SCR, control);
WRITE4(sc, ALI_DMACR, val);
WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port));
WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
WRITE4(sc, ALI_DMACR, val);