libexec/getty/subr.c

305

if (RW) {

sys/arch/mips/ingenic/ingenic_regs.h

676

#define JZ_MSC_RDTO RW 0x14 /* 32bit read timeout in MSC_CLK */

sys/dev/ic/arn5008.c

1778

reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);

sys/dev/ic/arn5008.c

1779

reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);

sys/dev/ic/arn5008.c

1788

reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);

sys/dev/ic/arn5008.c

1789

reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);

sys/dev/ic/arn5008.c

1892

reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);

sys/dev/ic/arn5008.c

1896

reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);

sys/dev/ic/arn5008.c

1991

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);

sys/dev/ic/arn5008.c

2079

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);

sys/dev/ic/arn5008.c

2080

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);

sys/dev/ic/arn5008.c

2130

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);

sys/dev/ic/arn5008.c

2131

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);

sys/dev/ic/arn5008.c

2183

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,

sys/dev/ic/arn5008.c

2185

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,

sys/dev/ic/arn5008.c

2705

reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);

sys/dev/ic/arn5008.c

2709

reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);

sys/dev/ic/arn5008.c

2710

reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);

sys/dev/ic/arn5008.c

2714

reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);

sys/dev/ic/arn5008.c

2726

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);

sys/dev/ic/arn5008.c

2727

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);

sys/dev/ic/arn5008.c

2728

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);

sys/dev/ic/arn5008.c

2732

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);

sys/dev/ic/arn5008.c

2733

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);

sys/dev/ic/arn5008.c

2734

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);

sys/dev/ic/arn5008.c

2738

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);

sys/dev/ic/arn5008.c

2739

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);

sys/dev/ic/arn5008.c

2740

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);

sys/dev/ic/arn5008.c

2741

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);

sys/dev/ic/arn5008.c

2755

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2756

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2757

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);

sys/dev/ic/arn5008.c

2761

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);

sys/dev/ic/arn5008.c

2762

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);

sys/dev/ic/arn5008.c

2763

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);

sys/dev/ic/arn5008.c

2767

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2768

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2769

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);

sys/dev/ic/arn5008.c

2770

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);

sys/dev/ic/arn5008.c

2784

reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);

sys/dev/ic/arn5008.c

2795

reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);

sys/dev/ic/arn5008.c

2806

reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);

sys/dev/ic/arn5008.c

458

reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);

sys/dev/ic/arn5416.c

248

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,

sys/dev/ic/arn5416.c

250

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

sys/dev/ic/arn5416.c

259

reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN,

sys/dev/ic/arn5416.c

261

reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN,

sys/dev/ic/arn5416.c

270

reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);

sys/dev/ic/arn5416.c

274

reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN,

sys/dev/ic/arn5416.c

279

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn5416.c

283

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn5416.c

284

reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize);

sys/dev/ic/arn5416.c

294

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn5416.c

298

reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn5416.c

302

reg = RW(reg, AR_PHY_EXT_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn5416.c

307

reg = RW(reg, AR_PHY_TX_END_DATA_START,

sys/dev/ic/arn5416.c

309

reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);

sys/dev/ic/arn5416.c

316

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn5416.c

453

reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);

sys/dev/ic/arn5416.c

454

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);

sys/dev/ic/arn5416.c

455

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);

sys/dev/ic/arn5416.c

456

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_3, xpdgains[2]);

sys/dev/ic/arn5416.c

474

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn5416.c

478

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn5416.c

482

reg = RW(reg, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, txgain);

sys/dev/ic/arn9003.c

1953

reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);

sys/dev/ic/arn9003.c

1954

reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);

sys/dev/ic/arn9003.c

1963

reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);

sys/dev/ic/arn9003.c

1964

reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);

sys/dev/ic/arn9003.c

2059

reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);

sys/dev/ic/arn9003.c

2063

reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);

sys/dev/ic/arn9003.c

2218

reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10);

sys/dev/ic/arn9003.c

2296

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff);

sys/dev/ic/arn9003.c

2297

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff);

sys/dev/ic/arn9003.c

2440

reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);

sys/dev/ic/arn9003.c

2482

reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,

sys/dev/ic/arn9003.c

2487

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,

sys/dev/ic/arn9003.c

2489

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,

sys/dev/ic/arn9003.c

2534

reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask);

sys/dev/ic/arn9003.c

2539

reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask);

sys/dev/ic/arn9003.c

2543

reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask);

sys/dev/ic/arn9003.c

2551

reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181);

sys/dev/ic/arn9003.c

2552

reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361);

sys/dev/ic/arn9003.c

2559

reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3);

sys/dev/ic/arn9003.c

2574

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28);

sys/dev/ic/arn9003.c

2575

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30);

sys/dev/ic/arn9003.c

2586

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4);

sys/dev/ic/arn9003.c

2587

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4);

sys/dev/ic/arn9003.c

2588

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7);

sys/dev/ic/arn9003.c

2589

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1);

sys/dev/ic/arn9003.c

2591

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3);

sys/dev/ic/arn9003.c

2593

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6);

sys/dev/ic/arn9003.c

2594

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15);

sys/dev/ic/arn9003.c

2599

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0);

sys/dev/ic/arn9003.c

2600

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400);

sys/dev/ic/arn9003.c

2601

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100);

sys/dev/ic/arn9003.c

2606

reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]);

sys/dev/ic/arn9003.c

2676

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN,

sys/dev/ic/arn9003.c

2678

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN,

sys/dev/ic/arn9003.c

2680

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN,

sys/dev/ic/arn9003.c

2682

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA,

sys/dev/ic/arn9003.c

2684

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB,

sys/dev/ic/arn9003.c

2686

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC,

sys/dev/ic/arn9003.c

2688

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND,

sys/dev/ic/arn9003.c

2695

reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);

sys/dev/ic/arn9003.c

3033

reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]);

sys/dev/ic/arn9003.c

3038

reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow);

sys/dev/ic/arn9003.c

3376

reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);

sys/dev/ic/arn9003.c

3380

reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64);

sys/dev/ic/arn9003.c

3381

reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14);

sys/dev/ic/arn9003.c

3385

reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);

sys/dev/ic/arn9003.c

3396

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);

sys/dev/ic/arn9003.c

3397

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);

sys/dev/ic/arn9003.c

3398

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);

sys/dev/ic/arn9003.c

3402

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);

sys/dev/ic/arn9003.c

3403

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);

sys/dev/ic/arn9003.c

3404

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);

sys/dev/ic/arn9003.c

3408

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);

sys/dev/ic/arn9003.c

3409

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);

sys/dev/ic/arn9003.c

3410

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);

sys/dev/ic/arn9003.c

3411

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);

sys/dev/ic/arn9003.c

3425

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3426

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3427

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);

sys/dev/ic/arn9003.c

3431

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);

sys/dev/ic/arn9003.c

3432

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);

sys/dev/ic/arn9003.c

3433

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);

sys/dev/ic/arn9003.c

3437

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3438

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3439

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);

sys/dev/ic/arn9003.c

3440

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);

sys/dev/ic/arn9003.c

3454

reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);

sys/dev/ic/arn9003.c

3465

reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);

sys/dev/ic/arn9003.c

3476

reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);

sys/dev/ic/arn9003.c

588

reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);

sys/dev/ic/arn9003.c

844

reg = RW(reg, AR_RXBP_THRESH_HP, 1);

sys/dev/ic/arn9003.c

845

reg = RW(reg, AR_RXBP_THRESH_LP, 1);

sys/dev/ic/arn9280.c

221

reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);

sys/dev/ic/arn9280.c

257

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,

sys/dev/ic/arn9280.c

259

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

sys/dev/ic/arn9280.c

265

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9280.c

267

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9280.c

269

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,

sys/dev/ic/arn9280.c

271

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,

sys/dev/ic/arn9280.c

280

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,

sys/dev/ic/arn9280.c

282

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,

sys/dev/ic/arn9280.c

288

reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);

sys/dev/ic/arn9280.c

289

reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);

sys/dev/ic/arn9280.c

295

reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);

sys/dev/ic/arn9280.c

296

reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);

sys/dev/ic/arn9280.c

303

reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);

sys/dev/ic/arn9280.c

304

reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);

sys/dev/ic/arn9280.c

310

reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);

sys/dev/ic/arn9280.c

311

reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);

sys/dev/ic/arn9280.c

323

reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);

sys/dev/ic/arn9280.c

326

reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);

sys/dev/ic/arn9280.c

343

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn9280.c

347

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn9280.c

357

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn9280.c

361

reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn9280.c

365

reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);

sys/dev/ic/arn9280.c

370

reg = RW(reg, AR_PHY_TX_END_DATA_START,

sys/dev/ic/arn9280.c

372

reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);

sys/dev/ic/arn9280.c

379

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn9280.c

385

reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,

sys/dev/ic/arn9280.c

403

reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,

sys/dev/ic/arn9280.c

408

reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,

sys/dev/ic/arn9280.c

623

reg = RW(reg, AR_PHY_TX_GAIN, txgain);

sys/dev/ic/arn9285.c

195

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);

sys/dev/ic/arn9285.c

196

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);

sys/dev/ic/arn9285.c

201

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9285.c

203

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9285.c

205

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,

sys/dev/ic/arn9285.c

207

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,

sys/dev/ic/arn9285.c

213

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9285.c

215

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9285.c

217

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,

sys/dev/ic/arn9285.c

219

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,

sys/dev/ic/arn9285.c

228

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);

sys/dev/ic/arn9285.c

229

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);

sys/dev/ic/arn9285.c

234

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);

sys/dev/ic/arn9285.c

235

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);

sys/dev/ic/arn9285.c

241

reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);

sys/dev/ic/arn9285.c

242

reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,

sys/dev/ic/arn9285.c

244

reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,

sys/dev/ic/arn9285.c

246

reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,

sys/dev/ic/arn9285.c

248

reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,

sys/dev/ic/arn9285.c

250

reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,

sys/dev/ic/arn9285.c

314

reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]);

sys/dev/ic/arn9285.c

315

reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]);

sys/dev/ic/arn9285.c

316

reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]);

sys/dev/ic/arn9285.c

317

reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]);

sys/dev/ic/arn9285.c

322

reg = RW(reg, AR9271_AN_RF2G4_DB2, (uint32_t)db2[0]);

sys/dev/ic/arn9285.c

331

reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]);

sys/dev/ic/arn9285.c

332

reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]);

sys/dev/ic/arn9285.c

333

reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]);

sys/dev/ic/arn9285.c

334

reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]);

sys/dev/ic/arn9285.c

335

reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]);

sys/dev/ic/arn9285.c

336

reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]);

sys/dev/ic/arn9285.c

337

reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);

sys/dev/ic/arn9285.c

338

reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);

sys/dev/ic/arn9285.c

343

reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);

sys/dev/ic/arn9285.c

344

reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]);

sys/dev/ic/arn9285.c

345

reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]);

sys/dev/ic/arn9285.c

346

reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]);

sys/dev/ic/arn9285.c

347

reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]);

sys/dev/ic/arn9285.c

348

reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);

sys/dev/ic/arn9285.c

349

reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);

sys/dev/ic/arn9285.c

356

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn9285.c

360

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn9285.c

370

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn9285.c

374

reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn9285.c

378

reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);

sys/dev/ic/arn9285.c

383

reg = RW(reg, AR_PHY_TX_END_PA_ON,

sys/dev/ic/arn9285.c

385

reg = RW(reg, AR_PHY_TX_END_DATA_START,

sys/dev/ic/arn9285.c

392

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn9285.c

441

reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);

sys/dev/ic/arn9285.c

445

reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);

sys/dev/ic/arn9285.c

452

reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf);

sys/dev/ic/arn9285.c

497

reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);

sys/dev/ic/arn9285.c

539

reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);

sys/dev/ic/arn9285.c

543

reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);

sys/dev/ic/arn9285.c

549

reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff);

sys/dev/ic/arn9285.c

695

reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5);

sys/dev/ic/arn9285.c

697

reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);

sys/dev/ic/arn9285.c

764

reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);

sys/dev/ic/arn9285.c

765

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);

sys/dev/ic/arn9285.c

766

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);

sys/dev/ic/arn9287.c

176

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,

sys/dev/ic/arn9287.c

178

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

sys/dev/ic/arn9287.c

183

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9287.c

185

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9287.c

190

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,

sys/dev/ic/arn9287.c

192

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,

sys/dev/ic/arn9287.c

200

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn9287.c

203

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn9287.c

207

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn9287.c

217

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn9287.c

221

reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn9287.c

225

reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);

sys/dev/ic/arn9287.c

229

reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);

sys/dev/ic/arn9287.c

230

reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);

sys/dev/ic/arn9287.c

231

reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);

sys/dev/ic/arn9287.c

232

reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);

sys/dev/ic/arn9287.c

233

reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);

sys/dev/ic/arn9287.c

234

reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);

sys/dev/ic/arn9287.c

240

reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);

sys/dev/ic/arn9287.c

241

reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);

sys/dev/ic/arn9287.c

242

reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);

sys/dev/ic/arn9287.c

243

reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);

sys/dev/ic/arn9287.c

244

reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);

sys/dev/ic/arn9287.c

245

reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);

sys/dev/ic/arn9287.c

251

reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);

sys/dev/ic/arn9287.c

252

reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);

sys/dev/ic/arn9287.c

256

reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);

sys/dev/ic/arn9287.c

368

reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);

sys/dev/ic/arn9287.c

369

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);

sys/dev/ic/arn9287.c

370

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);

sys/dev/ic/arn9287.c

384

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn9287.c

388

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn9287.c

393

reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);

sys/dev/ic/arn9287.c

549

reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,

sys/dev/ic/arn9287.c

583

reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);

sys/dev/ic/arn9287.c

587

reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);

sys/dev/ic/arn9287.c

627

reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);

sys/dev/ic/arn9380.c

317

reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,

sys/dev/ic/arn9380.c

323

reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,

sys/dev/ic/arn9380.c

327

reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB,

sys/dev/ic/arn9380.c

335

reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);

sys/dev/ic/arn9380.c

338

reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);

sys/dev/ic/arn9380.c

344

reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);

sys/dev/ic/arn9380.c

351

reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL,

sys/dev/ic/arn9380.c

369

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5);

sys/dev/ic/arn9380.c

370

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5);

sys/dev/ic/arn9380.c

371

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5);

sys/dev/ic/arn9380.c

372

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5);

sys/dev/ic/arn9380.c

373

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5);

sys/dev/ic/arn9380.c

374

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5);

sys/dev/ic/arn9380.c

378

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5);

sys/dev/ic/arn9380.c

379

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5);

sys/dev/ic/arn9380.c

380

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5);

sys/dev/ic/arn9380.c

381

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5);

sys/dev/ic/arn9380.c

382

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_4, 5);

sys/dev/ic/arn9380.c

383

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_5, 5);

sys/dev/ic/arn9380.c

384

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_6, 5);

sys/dev/ic/arn9380.c

385

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_7, 5);

sys/dev/ic/arn9380.c

386

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_8, 5);

sys/dev/ic/arn9380.c

390

reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_0, 5);

sys/dev/ic/arn9380.c

391

reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_1, 5);

sys/dev/ic/arn9380.c

392

reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_2, 5);

sys/dev/ic/arn9380.c

430

reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, db);

sys/dev/ic/arn9380.c

431

reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, margin);

sys/dev/ic/arn9380.c

445

reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC,

sys/dev/ic/arn9380.c

447

reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC,

sys/dev/ic/arn9380.c

536

reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);

sys/dev/ic/arn9380.c

539

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);

sys/dev/ic/arn9380.c

548

reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);

sys/dev/ic/arn9380.c

552

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq);

sys/dev/ic/arn9380.c

553

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);

sys/dev/ic/arn9380.c

554

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);

sys/dev/ic/arn9380.c

581

reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);

sys/dev/ic/arn9380.c

582

reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);

sys/dev/ic/arn9380.c

593

reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);

sys/dev/ic/arn9380.c

656

reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);

sys/dev/ic/arn9380.c

657

reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);

sys/dev/ic/arn9380.c

672

reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);

sys/dev/ic/arn9380.c

673

reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);

sys/dev/ic/arn9380.c

690

reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);

sys/dev/ic/arn9380.c

691

reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);

sys/dev/ic/arn9380.c

695

reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);

sys/dev/ic/arn9380.c

696

reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);

sys/dev/ic/arn9380.c

700

reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);

sys/dev/ic/arn9380.c

701

reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);

sys/dev/ic/arn9380.c

883

reg = RW(reg, AR_PHY_TPC_11_OLPC_GAIN_DELTA, corr);

sys/dev/ic/arn9380.c

888

reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3);

sys/dev/ic/arn9380.c

910

reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope);

sys/dev/ic/arn9380.c

914

reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0);

sys/dev/ic/athn.c

1193

reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,

sys/dev/ic/athn.c

1205

reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,

sys/dev/ic/athn.c

1207

reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,

sys/dev/ic/athn.c

1725

reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);

sys/dev/ic/athn.c

1729

reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);

sys/dev/ic/athn.c

1731

reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);

sys/dev/ic/athn.c

1736

reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B);

sys/dev/ic/athn.c

1770

reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);

sys/dev/ic/athn.c

2009

reg = RW(reg, AR_RSSI_THR_BM_THR, 10);

sys/dev/ic/athn.c

2277

reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff);

sys/dev/ic/athn.c

2278

reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,

sys/dev/pci/if_rtwn.c

1168

reg = RW(reg, R92C_CR_NETTYPE, type);

sys/dev/pci/if_rtwn.c

1379

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

1383

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

1417

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/pci/if_rtwn.c

1419

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

1425

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/pci/if_rtwn.c

1427

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

2433

reg = RW(reg, R92C_MCUFWDL_PAGE, page);

sys/dev/pci/if_rtwn.c

2923

reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);

sys/dev/pci/if_rtwn.c

2926

reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);

sys/dev/pci/if_rtwn.c

2927

reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);

sys/dev/pci/if_rtwn.c

2928

reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);

sys/dev/pci/if_rtwn.c

2932

reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);

sys/dev/pci/if_rtwn.c

2933

reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);

sys/dev/pci/if_rtwn.c

2934

reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);

sys/dev/pci/if_rtwn.c

2937

reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);

sys/dev/pci/if_rtwn.c

3109

RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));

sys/dev/pci/if_rtwn.c

3198

RW(rf_ac[i], R92C_RF_AC_MODE,

sys/dev/pci/if_rtwn.c

3308

reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL);

sys/dev/pci/if_rtwn.c

850

RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |

sys/dev/pci/if_rtwn.c

891

reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);

sys/dev/usb/if_urtwn.c

1256

RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |

sys/dev/usb/if_urtwn.c

1304

reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);

sys/dev/usb/if_urtwn.c

2054

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/usb/if_urtwn.c

2059

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/usb/if_urtwn.c

2098

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/usb/if_urtwn.c

2103

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/usb/if_urtwn.c

3493

reg = RW(reg, R92C_MCUFWDL_PAGE, page);

sys/dev/usb/if_urtwn.c

3977

RW(reg, R92C_AFE_XTAL_CTRL_ADDR,

sys/dev/usb/if_urtwn.c

3987

RW(reg, R92C_AFE_XTAL_CTRL_ADDR,

sys/dev/usb/if_urtwn.c

4219

reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);

sys/dev/usb/if_urtwn.c

4223

reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);

sys/dev/usb/if_urtwn.c

4224

reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);

sys/dev/usb/if_urtwn.c

4225

reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);

sys/dev/usb/if_urtwn.c

4229

reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);

sys/dev/usb/if_urtwn.c

4230

reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);

sys/dev/usb/if_urtwn.c

4231

reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);

sys/dev/usb/if_urtwn.c

4235

reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);

sys/dev/usb/if_urtwn.c

4496

RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));

sys/dev/usb/if_urtwn.c

4729

RW(rf_ac[i], R92C_RF_AC_MODE,

sys/dev/usb/if_urtwn.c

4884

reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);

sys/dev/usb/if_urtwn.c

4888

reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC);

sys/dev/usb/if_urtwn.c

4895

reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);

sys/dev/usb/if_urtwn.c

4927

reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);

usr.bin/uuencode/uuencode.c

100

mode = RW & ~umask(RW);

usr.sbin/lpr/common_source/common.c

99

long RW; /* open LP for reading and writing */

usr.sbin/lpr/common_source/lp.h

68

extern long RW; /* open LP for reading and writing */

usr.sbin/lpr/lpd/printjob.c

1303

RW = (cgetcap(bp, "rw", ':') != NULL);

usr.sbin/lpr/lpd/printjob.c

1444

pfd = open(LP, RW ? O_RDWR : O_WRONLY);