PCI_BAR
saved = pci_conf_read(NULL, tag, PCI_BAR(i));
pci_conf_write(NULL, tag, PCI_BAR(i), (pcireg_t) ~0x0);
val = pci_conf_read(NULL, tag, PCI_BAR(i));
pci_conf_write(NULL, tag, PCI_BAR(i), saved);
PCI_BAR(i), saved, val);
pci_conf_write(NULL, tag, PCI_BAR(j),
val = pci_conf_read(NULL, tag, PCI_BAR(j));
pci_conf_write(NULL, tag, PCI_BAR(j),
"mask %08x (io)\n", PCI_BAR(j),
pci_conf_write(NULL, tag, PCI_BAR(j),
"mask %08x (mem)\n", PCI_BAR(j),
basebar = pci_conf_read(pc, tag, PCI_BAR(bar));
pci_conf_write(pc, tag, PCI_BAR(bar), 0xffffffff);
sizebar = pci_conf_read(pc, tag, PCI_BAR(bar));
pci_conf_write(pc, tag, PCI_BAR(bar), basebar);
PCI_BAR(bar), basebar, sizebar);
basebar = pci_conf_read(pc, tag, PCI_BAR(bar));
pci_conf_write(pc, tag, PCI_BAR(bar), 0xffffffff);
sizebar = pci_conf_read(pc, tag, PCI_BAR(bar));
pci_conf_write(pc, tag, PCI_BAR(bar), basebar);
PCI_BAR(bar), basebar, sizebar);
#define ATH_PCI_MMBA PCI_BAR(0) /* memory mapped base */
#define ATHN_PCI_MMBA PCI_BAR(0) /* memory mapped base */
#define ATW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
#define ATW_PCI_MMBA PCI_BAR(1) /* memory mapped base */
#define RTW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
#define RTW_PCI_MMBA PCI_BAR(1) /* memory mapped base */
#define TULIP_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
#define TULIP_PCI_MMBA PCI_BAR(1) /* memory mapped base */
#define CX23885_MMBASE PCI_BAR(0)
PCI_BAR(i), sc->sc_bars[i]);
#define AN_PCI_IOBA PCI_BAR(2) /* i/o base */
bar = pci_conf_read(pc, tag, PCI_BAR(0));
memtype = pci_mapreg_type(pc, tag, PCI_BAR(0));
if (pci_mapreg_map(pa, PCI_BAR(0), memtype, 0, &sc->sc_iot, &sc->sc_ioh,
#define ATH_PCI_MMBA PCI_BAR(0) /* memory mapped base */
#define ATHN_PCI_MMBA PCI_BAR(0) /* memory mapped base */
#define ATW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
#define ATW_PCI_MMBA PCI_BAR(1) /* memory mapped base */
#define BWI_PCI_BAR0 PCI_BAR(0)
#define ENA_REG_BAR PCI_BAR(0)
#define ENA_MEM_BAR PCI_BAR(2)
#define PCI_CBIO PCI_BAR(0) /* Configuration Base IO Address */
#define EPIC_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
#define EPIC_PCI_MMBA PCI_BAR(1) /* memory mapped base */
#define PCI_CBIO PCI_BAR(0) /* Configuration Base IO Address */
#define PCI_FUNCMEM PCI_BAR(2)
#define PCI_HME_BASEADDR PCI_BAR(0)
#define PCI_IO_MAP_REG PCI_BAR(0)
#define PCI_MEM_MAP_REG PCI_BAR(1)
#define PCI_CBIO PCI_BAR(0) /* Configuration Base IO Address */
#define PCI_CBMA_SCA PCI_BAR(2)
#define PCI_CBMA_ASIC PCI_BAR(0) /* Configuration Base Memory Address */
#define RAL_PCI_BAR0 PCI_BAR(0)
#define RTW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
#define RTW_PCI_MMBA PCI_BAR(1) /* memory mapped base */
#define TULIP_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
#define TULIP_PCI_MMBA PCI_BAR(1) /* memory mapped base */
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR(0));
if (pci_mapreg_map(pa, PCI_BAR(0), memtype, 0, &sc->vmx_iot0, &sc->vmx_ioh0,
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR(1));
if (pci_mapreg_map(pa, PCI_BAR(1), memtype, 0, &sc->vmx_iot1, &sc->vmx_ioh1,
#define WI_PCI_CBMA PCI_BAR(0) /* Configuration Base Memory Address */
#define WI_PCI_PLX_LOIO PCI_BAR(1) /* PLX chip iobase */
#define WI_PCI_LOMEM PCI_BAR(2) /* ISA membase */
#define WI_PCI_LOIO PCI_BAR(3) /* ISA iobase */
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR(0));
if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_BAR(0),
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR(0));
if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_BAR(0),
PCI_BAR(pi->pi_bar),
PCI_BAR(pi->pi_bar));
PCI_BAR(pi->pi_bar), base);
PCI_BAR(pi->pi_bar + 1), base);
PCI_BAR(pi->pi_bar), 0);
bar = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BAR(i));
PCI_BAR(i), type, 0,
if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0,
if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel),
reg = PCI_BAR(i);