/* SPDX-License-Identifier: GPL-2.0 */
/*
 * USB4 port sideband registers found on routers and retimers
 *
 * Copyright (C) 2020, Intel Corporation
 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
 *          Rajmohan Mani <rajmohan.mani@intel.com>
 */

#ifndef _SB_REGS
#define _SB_REGS

#define USB4_SB_VENDOR_ID                       0x00
#define USB4_SB_PRODUCT_ID                      0x01
#define USB4_SB_FW_VERSION                      0x02
#define USB4_SB_DEBUG_CONF                      0x05
#define USB4_SB_DEBUG                           0x06
#define USB4_SB_LRD_TUNING                      0x07
#define USB4_SB_OPCODE                          0x08

enum usb4_sb_opcode {
        USB4_SB_OPCODE_ERR = 0x20525245,                        /* "ERR " */
        USB4_SB_OPCODE_ONS = 0x444d4321,                        /* "!CMD" */
        USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c,             /* "LSEN" */
        USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45,         /* "ENUM" */
        USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c,           /* "LSUP" */
        USB4_SB_OPCODE_UNSET_INBOUND_SBTX = 0x50555355,         /* "USUP" */
        USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c,         /* "LAST" */
        USB4_SB_OPCODE_QUERY_CABLE_RETIMER = 0x524c4243,        /* "CBLR" */
        USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47,        /* "GNSS" */
        USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42,             /* "BOPS" */
        USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42,            /* "BLKW" */
        USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541,             /* "AUTH" */
        USB4_SB_OPCODE_NVM_READ = 0x52524641,                   /* "AFRR" */
        USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452,    /* "RDCP" */
        USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852,      /* "RHMG" */
        USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352,      /* "RSMG" */
        USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452,         /* "RDSW" */
};

#define USB4_SB_METADATA                        0x09
#define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK    GENMASK(5, 0)
#define USB4_SB_LINK_CONF                       0x0c
#define USB4_SB_GEN23_TXFFE                     0x0d
#define USB4_SB_GEN4_TXFFE                      0x0e
#define USB4_SB_VERSION                         0x0f
#define USB4_SB_DATA                            0x12

/* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */
#define USB4_MARGIN_CAP_0_MODES_HW              BIT(0)
#define USB4_MARGIN_CAP_0_MODES_SW              BIT(1)
#define USB4_MARGIN_CAP_0_ALL_LANES             BIT(2)
#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK     GENMASK(4, 3)
#define USB4_MARGIN_CAP_0_VOLTAGE_MIN           0x0
#define USB4_MARGIN_CAP_0_VOLTAGE_HL            0x1
#define USB4_MARGIN_CAP_0_VOLTAGE_BOTH          0x2
#define USB4_MARGIN_CAP_0_TIME                  BIT(5)
#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK    GENMASK(12, 6)
#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13)
#define USB4_MARGIN_CAP_0_OPT_VOLTAGE_SUPPORT   BIT(19)
#define USB4_MARGIN_CAP_0_VOLT_STEPS_OPT_MASK   GENMASK(26, 20)
#define USB4_MARGIN_CAP_1_MAX_VOLT_OFS_OPT_MASK GENMASK(7, 0)
#define USB4_MARGIN_CAP_1_TIME_DESTR            BIT(8)
#define USB4_MARGIN_CAP_1_TIME_INDP_MASK        GENMASK(10, 9)
#define USB4_MARGIN_CAP_1_TIME_MIN              0x0
#define USB4_MARGIN_CAP_1_TIME_LR               0x1
#define USB4_MARGIN_CAP_1_TIME_BOTH             0x2
#define USB4_MARGIN_CAP_1_TIME_STEPS_MASK       GENMASK(15, 11)
#define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK      GENMASK(20, 16)
#define USB4_MARGIN_CAP_1_MIN_BER_MASK          GENMASK(25, 21)
#define USB4_MARGIN_CAP_1_MAX_BER_MASK          GENMASK(30, 26)
#define USB4_MARGIN_CAP_2_MODES_HW              BIT(0)
#define USB4_MARGIN_CAP_2_MODES_SW              BIT(1)
#define USB4_MARGIN_CAP_2_TIME                  BIT(2)
#define USB4_MARGIN_CAP_2_MAX_VOLTAGE_OFFSET_MASK GENMASK(8, 3)
#define USB4_MARGIN_CAP_2_VOLTAGE_STEPS_MASK    GENMASK(15, 9)
#define USB4_MARGIN_CAP_2_VOLTAGE_INDP_MASK     GENMASK(17, 16)
#define USB4_MARGIN_CAP_2_VOLTAGE_MIN           0x0
#define USB4_MARGIN_CAP_2_VOLTAGE_BOTH          0x1
#define USB4_MARGIN_CAP_2_TIME_INDP_MASK        GENMASK(19, 18)
#define USB4_MARGIN_CAP_2_TIME_MIN              0x0
#define USB4_MARGIN_CAP_2_TIME_BOTH             0x1

/* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */
#define USB4_MARGIN_HW_TIME                     BIT(3)
#define USB4_MARGIN_HW_RHU                      BIT(4)
#define USB4_MARGIN_HW_BER_MASK                 GENMASK(9, 5)
#define USB4_MARGIN_HW_BER_SHIFT                5
#define USB4_MARGIN_HW_OPT_VOLTAGE              BIT(10)

/* Applicable to all margin values */
#define USB4_MARGIN_HW_RES_MARGIN_MASK          GENMASK(6, 0)
#define USB4_MARGIN_HW_RES_EXCEEDS              BIT(7)

/* Shifts for parsing the lane results */
#define USB4_MARGIN_HW_RES_LANE_SHIFT           16
#define USB4_MARGIN_HW_RES_LL_SHIFT             8

/* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */
#define USB4_MARGIN_SW_LANES_MASK               GENMASK(2, 0)
#define USB4_MARGIN_SW_TIME                     BIT(3)
#define USB4_MARGIN_SW_RH                       BIT(4)
#define USB4_MARGIN_SW_OPT_VOLTAGE              BIT(5)
#define USB4_MARGIN_SW_VT_MASK                  GENMASK(12, 6)
#define USB4_MARGIN_SW_COUNTER_MASK             GENMASK(14, 13)
#define USB4_MARGIN_SW_UPPER_EYE                BIT(15)

#define USB4_MARGIN_SW_ERR_COUNTER_LANE_0_MASK  GENMASK(3, 0)
#define USB4_MARGIN_SW_ERR_COUNTER_LANE_1_MASK  GENMASK(7, 4)
#define USB4_MARGIN_SW_ERR_COUNTER_LANE_2_MASK  GENMASK(11, 8)

#endif