/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __SOC_MEDIATEK_MT6735_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT6735_PM_DOMAINS_H

#include "mtk-pm-domains.h"
#include <dt-bindings/power/mediatek,mt6735-power-controller.h>

/*
 * MT6735 power domain support
 */

static const struct scpsys_domain_data scpsys_domain_data_mt6735[] = {
        [MT6735_POWER_DOMAIN_MD1] = {
                .name = "md1",
                .sta_mask = PWR_STATUS_MD1,
                .ctl_offs = SPM_MD1_PWR_CON,
                .pwr_sta_offs = SPM_PWR_STATUS,
                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
                .sram_pdn_bits = GENMASK(8, 8),
                .sram_pdn_ack_bits = 0,
                .bp_cfg = {
                        BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_MD1),
                },
        },
        [MT6735_POWER_DOMAIN_CONN] = {
                .name = "conn",
                .sta_mask = PWR_STATUS_CONN,
                .ctl_offs = SPM_CONN_PWR_CON,
                .pwr_sta_offs = SPM_PWR_STATUS,
                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
                .sram_pdn_bits = GENMASK(8, 8),
                .sram_pdn_ack_bits = 0,
                .bp_cfg = {
                        BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_CONN),
                },
        },
        [MT6735_POWER_DOMAIN_DIS] = {
                .name = "dis",
                .sta_mask = PWR_STATUS_DISP,
                .ctl_offs = SPM_DIS_PWR_CON,
                .pwr_sta_offs = SPM_PWR_STATUS,
                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
                .sram_pdn_bits = GENMASK(11, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
                .bp_cfg = {
                        BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0),
                },
        },
        [MT6735_POWER_DOMAIN_MFG] = {
                .name = "mfg",
                .sta_mask = PWR_STATUS_MFG,
                .ctl_offs = SPM_MFG_PWR_CON,
                .pwr_sta_offs = SPM_PWR_STATUS,
                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
                .sram_pdn_bits = GENMASK(11, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
                .bp_cfg = {
                        BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S),
                },
        },
        [MT6735_POWER_DOMAIN_ISP] = {
                .name = "isp",
                .sta_mask = PWR_STATUS_ISP,
                .ctl_offs = SPM_ISP_PWR_CON,
                .pwr_sta_offs = SPM_PWR_STATUS,
                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
                .sram_pdn_bits = GENMASK(11, 8),
                .sram_pdn_ack_bits = GENMASK(13, 12),
        },
        [MT6735_POWER_DOMAIN_VDE] = {
                .name = "vde",
                .sta_mask = PWR_STATUS_VDEC,
                .ctl_offs = SPM_VDE_PWR_CON,
                .pwr_sta_offs = SPM_PWR_STATUS,
                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
                .sram_pdn_bits = GENMASK(11, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
        },
        [MT6735_POWER_DOMAIN_VEN] = {
                .name = "ven",
                .sta_mask = BIT(8),
                .ctl_offs = SPM_VEN_PWR_CON,
                .pwr_sta_offs = SPM_PWR_STATUS,
                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
                .sram_pdn_bits = GENMASK(11, 8),
                .sram_pdn_ack_bits = GENMASK(15, 12),
        },
};

static const struct scpsys_soc_data mt6735_scpsys_data = {
        .domains_data = scpsys_domain_data_mt6735,
        .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6735),
};

#endif /* __SOC_MEDIATEK_MT6735_PM_DOMAINS_H */