/* Only for QMP V5 PHY - PCS_PCIE registers */
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_
#define QCOM_PHY_QMP_PCS_PCIE_V5_H_

/* Only for QMP V5 PHY - PCS_PCIE registers */
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2            0x0c
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4            0x14
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE          0x20
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L  0x44
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H  0x48
#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L  0x4c
#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H  0x50
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1            0x54
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1               0x5c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2               0x60
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4               0x68
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2         0x7c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4         0x84
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5         0x88
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6         0x8c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS               0x94
#define QPHY_V5_PCS_PCIE_EQ_CONFIG1                     0xa4
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2                     0xa8
#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE                 0xc0
#define QPHY_V5_PCS_PCIE_PRESET_P10_POST                0xe4

#endif