__raw_readq
extern u64 __raw_readq(const volatile void __iomem *addr);
#define __raw_readq __raw_readq
ret = __raw_readq(addr);
return __raw_readq(addr);
EXPORT_SYMBOL(__raw_readq);
ret = __raw_readq(addr);
return __raw_readq(addr);
*(u64 *)to = __raw_readq(from);
#define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })
#define __raw_readq __raw_readq
be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
#define __raw_readq __raw_readq
return __raw_readq(addr_##unit##_##name()); \
val = __raw_readq(addr) >> intr % 64; \
_val = __raw_readq(addr); \
#define LOCAL_HUB_L(_r) __raw_readq(LOCAL_HUB_PTR(_r))
#define REMOTE_HUB_L(_n, _r) __raw_readq(REMOTE_HUB_PTR((_n), (_r)))
((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
return __raw_readq(addr);
return (u64) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));
return __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));
plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
count = G_SCD_TIMER_CNT(__raw_readq(addr));
*dst++ = __raw_readq(src++);
while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
(unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
(unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
if (__raw_readq(&tx4938_ccfgptr->pcfg) &
if (__raw_readq(&tx4938_ccfgptr->pcfg) &
(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
__u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
mask_h = __raw_readq(
mask_l = __raw_readq(
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
(long long)__raw_readq(IOADDR(A_SCD_TRACE_READ)));
scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
return __raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff;
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
return __raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff;
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
val = __raw_readq(addr);
u64 pcfg = __raw_readq(&tx4927_ccfgptr->pcfg);
if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
ebccr = __raw_readq(&tx4938_ebuscptr->cr[i]);
if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful;
return __raw_readq(addr);
__raw_readq(__x_eoi_page(xd) + XIVE_ESB_LOAD_EOI);
__raw_readq((void __iomem *)(vcpu->arch.xive_esc_vaddr +
__be64 qw1 = __raw_readq(xive_tima + TM_QW1_OS);
pq = __raw_readq((void __iomem *)(vcpu->arch.xive_esc_vaddr +
vcpu->arch.xive_saved_state.w01 = __raw_readq(tima + TM_QW1_OS);
__raw_readq(esc_vaddr + XIVE_ESB_SET_PQ_10);
__raw_readq(esc_vaddr + XIVE_ESB_SET_PQ_00);
val = __raw_readq(__x_eoi_page(xd) + offset);
#define __raw_readq __raw_readq
#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
#define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; })
tmp = __raw_readq(src_addr);
return __raw_readq(addr);
#define __raw_readq __raw_readq
__raw_readq(&(__dma_regs(dc)->name))
mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));
mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));
stat = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
__be64 rd = cpu_to_be64(__raw_readq(i2c->twsi_base + OCTEON_REG_BLOCK_FIFO(i2c)));
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
return (__raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)) & SW_TWSI_V) == 0;
mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));
__raw_readq(addr); /* wait for write to land */
tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));
*(u64 *)to = __raw_readq(from);
return be64_to_cpu((__force __be64)__raw_readq(cd->mmio + byte_offs));
#define mci_fifo_readq(__reg) __raw_readq(__reg)
+= __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
reg = __raw_readq(sc->sbm_rxfilter);
reg = __raw_readq(sc->sbm_rxfilter);
reg = __raw_readq(sc->sbm_rxfilter);
cfg = __raw_readq(s->sbm_maccfg);
framecfg = __raw_readq(s->sbm_framecfg);
cfg = __raw_readq(s->sbm_maccfg);
isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
reg = __raw_readq(sc->sbm_rxfilter);
reg = __raw_readq(sc->sbm_rxfilter);
reg = __raw_readq(sc->sbm_rxfilter);
ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
__raw_readq(sc->sbm_isr);
sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
return __raw_readq((void __iomem *)(epa.addr + offset));
#ifdef __raw_readq
*wrptr64++ = __raw_readq(rdptr64++);
value->u64[0] = (__force __le64)__raw_readq(membase + addr);
return (__force __le64)__raw_readq(efx->membase + reg);
return (__force __le64)__raw_readq(efx->membase + reg);
value->u64[0] = (__force __le64)__raw_readq(membase + addr);
return (__force __le64)__raw_readq(efx->membase + reg);
u8 value = __raw_readq(p->membase + (offset << p->regshift));
__raw_readq(p->membase + (UART_LCR << p->regshift));
return __raw_readq(csr);
return __raw_readq(csr);
ret = put_user((u32)__raw_readq(user_dog - 8) / 1000000, p);
wd_init = __raw_readq(wd_cfg_reg - 8) & 0x7fffff;
#ifndef __raw_readq
#define __raw_readq __raw_readq
val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
u64 x = __raw_readq(addr);
#define __raw_readq __raw_readq
u64 __raw_readq(const volatile void __iomem *addr);
#if defined(__raw_readq)
return __raw_readq(addr);
r.x[0] = __raw_readq(map->virt + ofs);
long val = __raw_readq(src);
#ifndef __raw_readq
#define __raw_readq __raw_readq
val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
u64 x = __raw_readq(addr);
#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })