__fls
lene = __fls(ctrl->len);
shift = val ? (31 - __fls(val)) & ~1 : 32;
unsigned int hwirq = 1 + __fls(stat);
unsigned int hwirq = 33 + __fls(stat);
unsigned int hwirq = __fls(stat);
unsigned int hwirq = 32 + __fls(stat);
unsigned int hwirq = 64 + __fls(stat);
unsigned int hwirq = 1 + __fls(stat);
if (__fls(count) < order) {
phys_addr_t p2size = 1 << __fls(asize);
phys_addr_t p2size = (1 << __fls(diff)) - 1;
BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
lene = __fls(ctrl->len);
phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT;
gfn_t end = base_gfn + __fls(mask) + 1;
return __fls(word & -word);
gfn_t end = base_gfn + __fls(mask);
irq = __fls(irq);
return ~1ul << __fls(mask);
phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT;
if (!ctr_mask || (ctr_base + __fls(ctr_mask) >= kvm_pmu_num_counters(kvpmu)))
char *p = dst + max(pad, (int)__fls(val | 1) / 4 + 1);
return __fls(data);
isc = __fls(active_mask) ^ (BITS_PER_LONG - 1);
return result + (__fls(tmp) ^ (BITS_PER_LONG - 1));
return result + (__fls(tmp) ^ (BITS_PER_LONG - 1));
int __attribute_const__ __fls(unsigned long word);
return __fls(*reg) + vec;
last = (base + __fls(bits)) & mask;
align = __fls(range_sizek);
return (__fls(stack_mask(ctxt)) + 1) >> 3;
max_updated_irr = __fls(irr_val ^ prev_irr_val) + vec;
*max_irr = __fls(irr_val) + vec;
gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
index = __fls(state);
pm_state = __fls(pm_state);
shift = __fls(biggest) - (BITS_PER_BYTE * sizeof(unsigned int)) + 1;
reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
delta = 1 << __fls(addrmid);
cs_ht_sz = __fls(asize - cs_rc_max) - 2;
*maxburst = __fls(*maxburst);
q_num = __fls(val);
tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
return __fls(mask) - __ffs(mask) + 1;
*size = __fls(mask) - *pos + 1;
st->color_depth = __fls(avail_depths);
info->bpc = __fls(kcrtc->master->improc->supported_color_depths);
u32 largest_pgsize = 1 << __fls(pgsizes);
GEM_WARN_ON(eu_mask && __fls(eu_mask) >= sseu->max_eus_per_subslice);
pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0);
pgsize_idx = __fls(pgsizes);
return min_t(unsigned int, highest, __fls(alloc->remaining_pages));
xe_assert(xe, !mask || patternbits * (__fls(mask) + 1) <= XE_MAX_L3_BANK_MASK_BITS);
return pci_iov_vf_bar_set_size(pdev, VF_LMEM_BAR, __fls(sizes));
exp = __fls(val);
BIT(__fls(avg)) != avg) {
BIT(__fls(avg)) != avg) {
rate = 7 - __fls(val * 4 / (125 * 3));
rate = 7 - __fls(interval * 4 / (125 * 3));
rate = 8 - __fls((val * 8 / (625 * 7)));
mask, speed_mode << __fls(mask));
it = __fls(sta & ien);
biter->__pg_bit = __fls(pgsz);
log_max_size = __fls(supported_size_mask);
int size_alignment = __fls(size);
for (order_mask &= GENMASK(__fls(count), 0);
unsigned int order = __fls(order_mask);
size = 1UL << __fls(cfg->pgsize_bitmap);
granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
pgsizes = domain->pgsize_bitmap & GENMASK(__fls(size), 0);
pgsize_idx = __fls(pgsizes);
generic_handle_domain_irq(root_domain, irq_base + __fls(hwirq));
hwirq = __fls(pending);
hwirq = __fls(pending);
int bit = __fls(pending);
u32 hwirq = __fls(reg);
u32 hwirq = __fls(stat);
u32 hwirq = __fls(stat);
hwirq = __fls(stat);
global->hart_index_bits = __fls(*nr_parent_irqs);
unsigned remaining_order = __fls((remaining_size + PAGE_SIZE - 1) >> PAGE_SHIFT);
unsigned remaining_order = __fls((remaining_size + PAGE_SIZE - 1) >> PAGE_SHIFT);
unsigned int log2_max_io_len = __fls(ti->max_io_len);
ic->sb->log2_interleave_sectors = __fls(interleave_sectors);
ic->log2_buffer_sectors = min((int)__fls(buffer_sectors), 31 - SECTOR_SHIFT);
log2_sectors_per_bitmap_bit = __fls(DEFAULT_SECTORS_PER_BITMAP_BIT);
__fls((1 << v->hash_dev_block_bits) / v->digest_size);
cluster = 1 << __fls(cluster);
V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
__fls(*valid_link_freqs), ~*valid_link_freqs,
__fls(imx283->link_freq_bitmap),
__fls(imx334->link_freq_bitmap),
__fls(imx334->link_freq_bitmap),
__fls(imx335->link_freq_bitmap),
__fls(imx335->link_freq_bitmap),
__fls(ov08x->link_freq_bitmap),
int j, order = __fls(count);
unsigned int wmaxa = __fls(wmax ^ (wmin - 1));
unsigned int hmaxa = __fls(hmax ^ (hmin - 1));
emif_bus_width = __fls(emif_bus_width) - 1;
timeout = __fls(timeout) - 3;
dev_info->density = __fls(density) - 5;
dev_info->io_width = __fls(io_width) - 1;
dlyb->max = __fls(lng);
val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET);
val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET);
unsigned dsize_log2 = __fls(dsize);
shift_count = (8 - __fls(var_len_off_mask));
tx_chn->dsize_log2 = __fls(hdesc_size_out);
rx_chn->dsize_log2 = __fls(hdesc_size_out);
channel_id = __fls(mask);
channel_id = __fls(mask);
matched_caps = GENMASK(__fls(caps), __fls(MAC_10HD));
matched_caps = GENMASK(__fls(caps), __fls(MAC_10HD));
if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap)))
rate_idx = __fls(rate_cfg);
fls = __fls(reg->mask);
val_integerd_b = __fls(val) + 1;
c = __fls(rate_ctrl);
regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
return __fls(supported_speeds);
__fls(PCI_EXP_LNKCAP2_SLS_2_5GB));
return __fls(sizes);
#define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
#define TSI721_IBWIN_SIZE(size) (__fls(size) - 12)
#define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
#define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
field.msb = __fls(args[1]);
i = __fls(en_bitmap); /* number of the last "low" queue */
i = __fls(req_bitmap); /* number of the last "high" queue */
i = __fls(req_bitmap); /* number of the last queue */
for (order_mask &= (2U << __fls(count)) - 1;
unsigned int order = __fls(order_mask);
int j, order = __fls(count);
channel = __fls(usb->idle_hardware_channels);
channel = __fls(usbc_haint.u32);
if (__ffs(dirty.flags) != __fls(dirty.flags))
max_shift = BITS_PER_LONG - 2 - __fls(GL_GLOCK_HOLD_INCR);
return __fls(x) + 1;
#define zero_bytemask(mask) (~1ul << __fls(mask))
return val ? __fls(val) : size;
#define PP_DMA_INDEX_SHIFT (1 + __fls(PP_SIGNATURE - POISON_POINTER_DELTA))
return ((__fls(mask) >> 3) << interleaved) + 1 + offset;
return i * 32 + 31 - __fls(ntohl(xb));
return i * 64 + 63 - __fls(be64_to_cpu(xb));
return __fls(mask->bits[i]) + (i << 5);
flags & CLOSURE_GUARD_MASK, (unsigned) __fls(r)))
flags & ~CLOSURE_DESTRUCTOR, (unsigned) __fls(flags));
return idx * BITS_PER_LONG + __fls(val);
return (BITS_PER_LONG - 1 - __fls(val)) >> 3;
m = 1UL << (__fls(x) & ~1UL);
fls_0based = __fls(input);
validate_ffs_result(test, tc->input, __fls(tc->input),
CREATE_WRAPPER(__fls)
new_prio = __fls(mask);
new_prio = __fls(mask);
new_prio = mask ? __fls(mask) : 0;
tn = tnode_new(key, __fls(key ^ n->key), 1);
mask = ~((1UL << __fls(mask)) - 1);
max_cl_shift = __fls(max_classes);
index = __fls(size_map) + 1; /* basically a log_2 */
__fls(n2->maps[i]);
order = __fls(border) - __fls(runtime->buffer_size);
mask &= ~(1 << __fls(mask));
last_slot = __fls(tx_mask);
last_bit = __fls(tx_mask);
if ((lsb + 1) != __fls(tx_mask)) {
last_slot = __fls(rx_mask);
if (tx_mask != GENMASK(__fls(tx_mask), 0)) {
if ((lsb + 1) != __fls(tx_mask)) {
(unsigned long)__fls(mach->mach_params.i2s_link_mask));
return volume ? __fls(volume) : 0;
if (__fls(mask) > h2link->slcount) {
hchan = __fls(channel_mask);
return __fls(x) + 1;
static inline unsigned long __fls(unsigned long x);
return ~1ul << __fls(mask);
if (!memslot || (offset + __fls(mask)) >= memslot->npages)