BMCR_RESET
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
if (val & BMCR_RESET)
} else if (val & BMCR_RESET) {
mask = BMCR_RESET | BMCR_LOOPBACK | BMCR_PDOWN;
mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE |
val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE |
cr = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
cr = BMCR_RESET;
u16 mii_bmcr_data = BMCR_RESET;
u16 mii_bmcr_data = BMCR_RESET;
phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
if (val & BMCR_RESET) {
bcma_mdio_phy_write(bgmac, phyaddr, MII_BMCR, BMCR_RESET);
if (bcma_mdio_phy_read(bgmac, phyaddr, MII_BMCR) & BMCR_RESET)
bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
if (!(reg & BMCR_RESET)) {
phy_control = BMCR_RESET;
if ((phy_control & BMCR_RESET) == 0) {
tg3_writephy(tp, MII_BMCR, BMCR_RESET);
mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
ctl &= BMCR_RESET;
dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET);
(tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
(tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
BMCR_RESET);
mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
bmcr |= BMCR_RESET;
mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
bmcr = BMCR_RESET;
mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
val |= BMCR_RESET;
if (val >= 0 && (val & BMCR_RESET) == 0)
val |= BMCR_RESET;
if (val >= 0 && (val & BMCR_RESET) == 0)
bmcr |= BMCR_RESET;
mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
phy_data |= BMCR_RESET;
phy_ctrl |= BMCR_RESET;
MII_BMCR, val | BMCR_RESET);
if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
if (!(bmcr & BMCR_RESET))
miicontrol = BMCR_RESET | bmcr_setup;
while (miicontrol & BMCR_RESET) {
pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET);
pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET);
if (value & BMCR_RESET || !(value & BMCR_PDOWN))
!(val & BMCR_RESET),
BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
if (val & BMCR_RESET) {
smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
if (!(bmcr & BMCR_RESET))
return bmcr & BMCR_RESET;
cas_phy_write(cp, MII_BMCR, BMCR_RESET);
if ((val & BMCR_RESET) == 0)
err |= BMCR_RESET;
if (!(err & BMCR_RESET))
err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
if (!(err & BMCR_RESET))
bp->sw_bmcr = (BMCR_RESET);
if ((bp->sw_bmcr & BMCR_RESET) == 0)
bp->sw_bmcr = (BMCR_RESET);
if ((bp->sw_bmcr & BMCR_RESET) == 0)
sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
if (!(result & BMCR_RESET))
tsi108_write_mii(data, MII_BMCR, BMCR_RESET);
if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET))
data |= BMCR_RESET;
if (val & (BMCR_RESET|BMCR_ANENABLE))
val < 0 || !(val & BMCR_RESET),
ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET);
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
MII_BMCR, BMCR_RESET);
BMCR_ANENABLE | BMCR_RESET);
BMCR_RESET | BMCR_SPEED100 | BMCR_FULLDPLX);
phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET);
return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
if (set == BMCR_RESET) {
if (!(ret & BMCR_RESET))
return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET);
if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0) {
val & BMCR_RESET)
ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
u16 res = BMCR_RESET;
phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
value |= BMCR_RESET;
} while (value & BMCR_RESET);
sungem_phy_write(phy, MII_BMCR, BMCR_RESET);
sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
val |= BMCR_RESET;
ctl |= BMCR_RESET;
if ((val & BMCR_RESET) == 0)
asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
& BMCR_RESET)
asix_phy_reset(dev, BMCR_RESET);
dm9601_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
bmcr |= BMCR_RESET;
if (bmcr & BMCR_RESET) {
if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
} while ((bmcr & BMCR_RESET) && (timeout < 100));
sr_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
#define MDIO_CTRL1_RESET BMCR_RESET