BMCR_ANRESTART
reg |= BMCR_ANRESTART;
if (val & BMCR_ANRESTART)
*val |= BMCR_ANRESTART;
marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_ANRESTART, BMCR_ANRESTART);
BMCR_ANRESTART, BMCR_ANRESTART);
reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
val = MII_BMCR << 16 | BMCR_ANENABLE | BMCR_ANRESTART;
BMCR_ANRESTART;
BMCR_ANRESTART;
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
cr = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART;
mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART;
phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
bmcr | BMCR_ANRESTART);
BMCR_ANRESTART))) != 0)
bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
BMCR_ANRESTART | BMCR_ANENABLE);
bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
BMCR_ANENABLE | BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART);
bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
BMCR_ANRESTART |
ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
(void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART, 1);
BMCR_ANENABLE | BMCR_ANRESTART, 1);
BMCR_ANENABLE | BMCR_ANRESTART);
BMCR_ANRESTART);
new_bmcr |= BMCR_ANRESTART;
bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
mii_ctrl &= ~(BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100);
mii_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
tmp |= (BMCR_ANRESTART);
mii_control |= BMCR_ANRESTART;
mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
_sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
BMCR_ANRESTART);
ctl |= BMCR_ANRESTART;
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
hp->sw_bmcr |= BMCR_ANRESTART;
if (!(hp->sw_bmcr & BMCR_ANRESTART))
BMCR_ANENABLE | BMCR_ANRESTART);
while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART)
MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
bmcr |= BMCR_ANRESTART;
regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART);
xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART,
BMCR_ANRESTART);
if (*bmcr & BMCR_ANRESTART) {
(BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
if (lrecr & BMCR_ANRESTART)
BMCR_ANENABLE | BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART);
if (bmcr & BMCR_ANRESTART)
res |= BMCR_ANRESTART;
val |= BMCR_ANRESTART;
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
BMCR_ANENABLE | BMCR_ANRESTART );
bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART