arch/arm/mach-footbridge/dc21285.c

252

dma_direct_set_offset(data, PHYS_OFFSET, BUS_OFFSET, SZ_256M);

arch/arm/mach-footbridge/dma-isa.c

226

dma_direct_set_offset(&isa_dma_dev, PHYS_OFFSET, BUS_OFFSET, SZ_256M);

arch/arm/mach-orion5x/kurobox_pro-setup.c

62

.size = SZ_256M - (SZ_4M + SZ_64M),

arch/arm/mach-versatile/realview.c

19

.dma_zone_size = SZ_256M,

arch/loongarch/include/asm/pgtable.h

99

#define MODULES_END (MODULES_VADDR + SZ_256M)

arch/mips/generic/board-sead3.c

31

{ 0, SZ_256M + SZ_128M },

arch/mips/mti-malta/malta-dtshim.c

103

if (size <= SZ_256M)

arch/mips/mti-malta/malta-dtshim.c

105

size -= SZ_256M;

arch/mips/mti-malta/malta-dtshim.c

122

mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_2G + SZ_256M);

arch/mips/mti-malta/malta-dtshim.c

89

size_preio = min_t(unsigned long, size, SZ_256M);

arch/powerpc/include/asm/book3s/32/mmu-hash.h

203

if (n << 28 < ALIGN(TASK_SIZE, SZ_256M))

arch/powerpc/include/asm/kasan.h

28

#define KASAN_KERN_START ALIGN_DOWN(PAGE_OFFSET - SZ_256M, SZ_256M)

arch/powerpc/include/asm/task_size_32.h

20

#define MODULES_END (ASM_CONST(CONFIG_PAGE_OFFSET) & ~(UL(SZ_256M) - 1))

arch/powerpc/include/asm/task_size_32.h

23

#define MODULES_BASE (MODULES_VADDR & ~(UL(SZ_256M) - 1))

arch/powerpc/kernel/asm-offsets.c

334

DEFINE(NUM_USER_SEGMENTS, ALIGN(TASK_SIZE, SZ_256M) >> 28);

arch/powerpc/mm/book3s32/mmu.c

104

unsigned int max_size = SZ_256M;

arch/powerpc/mm/book3s32/mmu.c

189

if (addr < ALIGN_DOWN(MODULES_VADDR, SZ_256M))

arch/powerpc/mm/book3s32/mmu.c

191

if (addr > ALIGN(MODULES_END, SZ_256M) - 1)

arch/powerpc/mm/book3s32/mmu.c

226

for (i = ALIGN(TASK_SIZE, SZ_256M) >> 28; i < 16; i++) {

arch/powerpc/mm/book3s32/mmu.c

432

memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_256M));

arch/powerpc/mm/init_64.c

590

if (*block_size > SZ_256M)

arch/powerpc/mm/init_64.c

591

*block_size = SZ_256M;

arch/powerpc/mm/ptdump/segment_regs.c

34

for (i = 0; i < ALIGN(TASK_SIZE, SZ_256M) >> 28; i++)

arch/powerpc/platforms/powernv/pci-ioda-tce.c

34

mask |= SZ_16M | SZ_256M;

arch/powerpc/platforms/pseries/iommu.c

1386

__builtin_ctzll(SZ_256M), __builtin_ctzll(SZ_16G), __builtin_ctzll(SZ_2M)

arch/powerpc/platforms/pseries/iommu.c

1788

(SZ_256M), (SZ_16G), (SZ_2M)

arch/sh/drivers/pci/pcie-sh7786.c

104

.end = 0x20000000 + SZ_256M - 1,

arch/sh/drivers/pci/pcie-sh7786.c

80

.end = 0x30000000 + SZ_256M - 1,

arch/x86/kernel/e820.c

703

max_gap_start = SZ_256M;

drivers/accel/ivpu/ivpu_hw.c

177

ivpu_hw_range_init(vdev, &vdev->hw->ranges.global, 0x90000000, SZ_256M);

drivers/accel/ivpu/ivpu_hw.c

183

ivpu_hw_range_init(vdev, &vdev->hw->ranges.global, 0x90000000, SZ_256M);

drivers/acpi/numa/srat.c

443

if (align >= SZ_256M) {

drivers/block/ublk_drv.c

955

if (p->physical_bs_shift > ilog2(SZ_256M))

drivers/block/ublk_drv.c

958

if (p->io_min_shift > ilog2(SZ_256M))

drivers/block/ublk_drv.c

961

if (p->io_opt_shift > ilog2(SZ_256M))

drivers/cxl/acpi.c

172

if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {

drivers/cxl/acpi.c

177

if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {

drivers/cxl/core/atl.c

116

hpa_range.start = ALIGN_DOWN(hpa_range.start, SZ_256M);

drivers/cxl/core/atl.c

117

hpa_range.end = ALIGN(hpa_range.end, SZ_256M) - 1;

drivers/cxl/core/port.c

266

if (!IS_ALIGNED(size, SZ_256M))

drivers/cxl/core/region.c

3356

div64_u64_rem(p->res->start, (u64)hbiw * SZ_256M, &rem);

drivers/cxl/core/region.c

677

div64_u64_rem(size, (u64)SZ_256M * p->interleave_ways, &remainder);

drivers/cxl/core/region.c

681

res = alloc_free_mem_region(cxlrd->res, size, SZ_256M,

drivers/cxl/cxlmem.h

225

#define CXL_CAPACITY_MULTIPLIER SZ_256M

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

564

bo->placements[0].fpfn = ALIGN_DOWN(vcpu_cur.start, SZ_256M) >> PAGE_SHIFT;

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

565

bo->placements[0].lpfn = bo->placements[0].fpfn + (SZ_256M >> PAGE_SHIFT);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

340

amdgpu_gmc_set_gart_size(adev, SZ_256M);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

409

amdgpu_gmc_set_gart_size(adev, SZ_256M);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

600

amdgpu_gmc_set_gart_size(adev, SZ_256M);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

959

GEM_BUG_ON(pci_resource_len(pdev, GEN12_LMEM_BAR) != SZ_256M);

drivers/gpu/drm/i915/selftests/intel_memory_region.c

571

io_size = max_t(u64, io_size, SZ_256M); /* 256M seems to be the common lower limit */

drivers/gpu/drm/imagination/pvr_rogue_heap_config.h

72

#define ROGUE_RGNHDR_HEAP_SIZE SZ_256M

drivers/gpu/drm/imagination/pvr_rogue_riscv.h

13

#define ROGUE_RISCVFW_REGION_SIZE SZ_256M

drivers/gpu/drm/panthor/panthor_mmu.c

1456

#define PANTHOR_VM_MIN_KERNEL_VA_SIZE SZ_256M

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

227

KUNIT_ASSERT_EQ(test, SZ_256M, pf_profile_fair_ggtt(gt, num_vfs));

drivers/iommu/sprd-iommu.c

149

dom->domain.geometry.aperture_end = SZ_256M - 1;

drivers/mtd/nand/raw/loongson-nand-controller.c

690

case SZ_256M:

drivers/mtd/spi-nor/micron-st.c

220

.size = SZ_256M,

drivers/mtd/spi-nor/micron-st.c

433

.size = SZ_256M,

drivers/mtd/spi-nor/micron-st.c

507

.size = SZ_256M,

drivers/mtd/spi-nor/spansion.c

645

if (params->size == SZ_256M)

drivers/mtd/spi-nor/spansion.c

716

if (params->size == SZ_256M)

drivers/pci/controller/dwc/pcie-designware-host.c

57

#define IS_256MB_ALIGNED(x) IS_ALIGNED(x, SZ_256M)

drivers/pci/controller/pci-ftpci100.c

152

case SZ_256M:

drivers/pci/controller/pci-rcar-gen2.c

225

window_size = SZ_256M;

drivers/pci/controller/pci-rcar-gen2.c

227

case SZ_256M:

drivers/pci/controller/pci-v3-semi.c

544

if (resource_size(mem) != SZ_256M) {

drivers/pci/controller/pci-v3-semi.c

549

(mem->start != v3->non_pre_mem + SZ_256M)) {

drivers/pci/controller/pci-v3-semi.c

569

if (resource_size(mem) != SZ_256M) {

drivers/pci/controller/pci-v3-semi.c

644

case SZ_256M:

drivers/scsi/sg.c

797

if (hp->dxfer_len >= SZ_256M) {

drivers/spi/spi-stm32-ospi.c

100

#define STM32_OSPI_MAX_MMAP_SZ SZ_256M

drivers/spi/spi-stm32-qspi.c

84

#define STM32_QSPI_MAX_MMAP_SZ SZ_256M

fs/btrfs/block-group.c

3491

cache_size = div_u64(block_group->length, SZ_256M);

fs/btrfs/inode.c

9036

cur_bytes = min_t(u64, num_bytes, SZ_256M);

fs/btrfs/ioctl.c

1101

if (new_size < SZ_256M) {

fs/btrfs/space-info.c

236

return SZ_256M;

fs/btrfs/sysfs.c

800

val &= ~((u64)SZ_256M - 1);

fs/btrfs/sysfs.c

803

if (val < SZ_256M)

fs/btrfs/tests/extent-map-tests.c

1106

.data_stripe_size = SZ_256M,

fs/btrfs/tests/extent-map-tests.c

1110

{SZ_64M - SZ_4M, SZ_64M - SZ_4M + SZ_256M},

fs/btrfs/tests/extent-map-tests.c

1123

.data_stripe_size = SZ_256M,

fs/btrfs/tests/extent-map-tests.c

1126

.data_stripe_phys_start = {SZ_256M},

fs/btrfs/tests/zoned-tests.c

16

#define ZONE_SIZE SZ_256M

tools/testing/cxl/test/cxl.c

246

.window_size = SZ_256M * 4UL,

tools/testing/cxl/test/cxl.c

261

.window_size = SZ_256M * 8UL,

tools/testing/cxl/test/cxl.c

276

.window_size = SZ_256M * 4UL,

tools/testing/cxl/test/cxl.c

291

.window_size = SZ_256M * 8UL,

tools/testing/cxl/test/cxl.c

306

.window_size = SZ_256M * 4UL,

tools/testing/cxl/test/cxl.c

321

.window_size = SZ_256M > PMD_SIZE ? SZ_256M : PMD_SIZE,

tools/testing/cxl/test/cxl.c

338

.window_size = SZ_256M * 8UL,

tools/testing/cxl/test/cxl.c

354

.window_size = SZ_256M * 8UL,

tools/testing/cxl/test/cxl.c

502

int align = SZ_256M;

tools/testing/cxl/test/cxl.c

506

align = max_t(int, SZ_256M, PMD_SIZE);

tools/testing/cxl/test/mem.c

632

cpu_to_le64(SZ_256M / CXL_CAPACITY_MULTIPLIER),

tools/testing/memblock/tests/basic_api.c

1447

.size = SZ_256M

tools/testing/memblock/tests/basic_api.c

182

.base = SZ_256M,

tools/testing/memblock/tests/basic_api.c

234

.base = SZ_256M,

tools/testing/memblock/tests/basic_api.c

589

.base = SZ_256M,

tools/testing/selftests/kvm/memslot_perf_test.c

33

#define MEM_GPA SZ_256M