drivers/crypto/hisilicon/sec/sec_drv.c

360

void __iomem *addr = info->regs[SEC_SAA] + SEC_CTRL2_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

374

void __iomem *addr = info->regs[SEC_SAA] + SEC_CTRL_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

387

void __iomem *addr = info->regs[SEC_SAA] + SEC_CTRL2_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

399

void __iomem *addr = info->regs[SEC_SAA] + SEC_CTRL2_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

411

void __iomem *addr = info->regs[SEC_SAA] + SEC_CTRL2_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

424

void __iomem *addr = info->regs[SEC_SAA] + SEC_COMMON_CNT_CLR_CE_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

437

void __iomem *addr = info->regs[SEC_SAA] + SEC_COMMON_CNT_CLR_CE_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

450

void __iomem *base = info->regs[SEC_SAA];

drivers/crypto/hisilicon/sec/sec_drv.c

466

info->regs[SEC_SAA] + SEC_IPV4_MASK_TABLE_REG);

drivers/crypto/hisilicon/sec/sec_drv.c

473

void __iomem *addr = info->regs[SEC_SAA] + SEC_DEBUG_BD_CFG_REG;

drivers/crypto/hisilicon/sec/sec_drv.c

490

void __iomem *addr = info->regs[SEC_SAA] + SEC_SAA_BASE +

drivers/crypto/hisilicon/sec/sec_drv.c

506

info->regs[SEC_SAA] + SEC_SAA_BASE + SEC_ST_INTMSK1_REG +

drivers/crypto/hisilicon/sec/sec_drv.c

516

info->regs[SEC_SAA] + SEC_Q_VMID_CFG_REG(i));

drivers/crypto/hisilicon/sec/sec_drv.c

941

info->regs[SEC_SAA] + SEC_CLK_EN_REG);

drivers/crypto/hisilicon/sec/sec_drv.c

961

writel_relaxed((u32)~0, info->regs[SEC_SAA] + SEC_FSM_MAX_CNT_REG);

drivers/crypto/hisilicon/sec/sec_drv.c

979

info->regs[SEC_SAA] +