drivers/gpu/drm/i915/display/g4x_dp.c

1390

intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);

drivers/gpu/drm/i915/display/g4x_dp.c

270

*pipe = PIPE_A;

drivers/gpu/drm/i915/display/g4x_dp.c

440

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_dp.c

441

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_dp.c

445

intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |

drivers/gpu/drm/i915/display/g4x_dp.c

454

intel_wait_for_vblank_if_active(display, PIPE_A);

drivers/gpu/drm/i915/display/g4x_dp.c

455

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_dp.c

456

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_hdmi.c

402

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_hdmi.c

403

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_hdmi.c

406

temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);

drivers/gpu/drm/i915/display/g4x_hdmi.c

420

intel_wait_for_vblank_if_active(display, PIPE_A);

drivers/gpu/drm/i915/display/g4x_hdmi.c

421

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_hdmi.c

422

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_hdmi.c

747

intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);

drivers/gpu/drm/i915/display/hsw_ips.c

189

return HAS_IPS(display) && crtc->pipe == PIPE_A;

drivers/gpu/drm/i915/display/i9xx_wm.c

1898

case PIPE_A:

drivers/gpu/drm/i915/display/i9xx_wm.c

294

case PIPE_A:

drivers/gpu/drm/i915/display/i9xx_wm.c

3365

if (dirty & WM_DIRTY_PIPE(PIPE_A))

drivers/gpu/drm/i915/display/i9xx_wm.c

3366

intel_de_write(display, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3670

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);

drivers/gpu/drm/i915/display/i9xx_wm.c

3677

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

drivers/gpu/drm/i915/display/i9xx_wm.c

3678

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);

drivers/gpu/drm/i915/display/i9xx_wm.c

3710

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);

drivers/gpu/drm/i915/display/i9xx_wm.c

3713

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);

drivers/gpu/drm/i915/display/i9xx_wm.c

3714

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

drivers/gpu/drm/i915/display/i9xx_wm.c

3715

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);

drivers/gpu/drm/i915/display/i9xx_wm.c

3741

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3742

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3743

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3754

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3755

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3756

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

818

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

drivers/gpu/drm/i915/display/i9xx_wm.c

824

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

drivers/gpu/drm/i915/display/i9xx_wm.c

825

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

drivers/gpu/drm/i915/display/i9xx_wm.c

868

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

drivers/gpu/drm/i915/display/i9xx_wm.c

870

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |

drivers/gpu/drm/i915/display/i9xx_wm.c

871

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

drivers/gpu/drm/i915/display/i9xx_wm.c

872

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

drivers/gpu/drm/i915/display/i9xx_wm.c

894

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

895

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

896

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

drivers/gpu/drm/i915/display/i9xx_wm.c

906

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

907

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

908

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

drivers/gpu/drm/i915/display/icl_dsi.c

1741

*pipe = PIPE_A;

drivers/gpu/drm/i915/display/icl_dsi.c

839

case PIPE_A:

drivers/gpu/drm/i915/display/intel_backlight.c

1401

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_backlight.c

188

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_color.c

4289

return pipe == PIPE_A || pipe == PIPE_B;

drivers/gpu/drm/i915/display/intel_color.c

4336

if (DISPLAY_VER(display) == 3 && crtc->pipe == PIPE_A)

drivers/gpu/drm/i915/display/intel_crt.c

1069

crt->base.pipe_mask = BIT(PIPE_A);

drivers/gpu/drm/i915/display/intel_crt.c

1135

FDI_RX_CTL(PIPE_A)) & fdi_config;

drivers/gpu/drm/i915/display/intel_crt.c

257

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_crt.c

286

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_crt.c

298

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_crt.c

343

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_cursor.c

301

intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0);

drivers/gpu/drm/i915/display/intel_cursor.c

302

intel_de_write_fw(display, CURBASE(display, PIPE_A), base);

drivers/gpu/drm/i915/display/intel_cursor.c

303

intel_de_write_fw(display, CURSIZE(display, PIPE_A), size);

drivers/gpu/drm/i915/display/intel_cursor.c

304

intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);

drivers/gpu/drm/i915/display/intel_cursor.c

305

intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl);

drivers/gpu/drm/i915/display/intel_cursor.c

311

intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);

drivers/gpu/drm/i915/display/intel_cursor.c

330

power_domain = POWER_DOMAIN_PIPE(PIPE_A);

drivers/gpu/drm/i915/display/intel_cursor.c

335

ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;

drivers/gpu/drm/i915/display/intel_cursor.c

337

*pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_ddi.c

2490

return BIT(PIPE_A) | BIT(PIPE_B);

drivers/gpu/drm/i915/display/intel_ddi.c

2492

return BIT(PIPE_A);

drivers/gpu/drm/i915/display/intel_ddi.c

4512

if (display->platform.haswell && crtc->pipe == PIPE_A &&

drivers/gpu/drm/i915/display/intel_ddi.c

557

case PIPE_A:

drivers/gpu/drm/i915/display/intel_ddi.c

835

*pipe_mask = BIT(PIPE_A);

drivers/gpu/drm/i915/display/intel_display.c

2206

(crtc->pipe == PIPE_A || display->platform.i915g);

drivers/gpu/drm/i915/display/intel_display.c

3492

pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);

drivers/gpu/drm/i915/display/intel_display.c

3807

trans_pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_display.c

8442

intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);

drivers/gpu/drm/i915/display/intel_display_clock_gating.c

140

intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);

drivers/gpu/drm/i915/display/intel_display_clock_gating.c

169

intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);

drivers/gpu/drm/i915/display/intel_display_device.c

1073

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

1162

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)

drivers/gpu/drm/i915/display/intel_display_device.c

1340

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \

drivers/gpu/drm/i915/display/intel_display_device.c

1363

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

170

[PIPE_A] = CURSOR_A_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

175

[PIPE_A] = CURSOR_A_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

1806

display_runtime->num_scalers[PIPE_A] = 2;

drivers/gpu/drm/i915/display/intel_display_device.c

181

[PIPE_A] = CURSOR_A_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

1830

display_runtime->num_sprites[PIPE_A] = 2;

drivers/gpu/drm/i915/display/intel_display_device.c

1876

display_runtime->pipe_mask &= ~BIT(PIPE_A);

drivers/gpu/drm/i915/display/intel_display_device.c

188

[PIPE_A] = CURSOR_A_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

195

[PIPE_A] = CURSOR_A_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

241

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

254

.__runtime_defaults.pipe_mask = BIT(PIPE_A), \

drivers/gpu/drm/i915/display/intel_display_device.c

304

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

393

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

450

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

479

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_device.c

504

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

533

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_device.c

581

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

634

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

654

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

678

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

828

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

drivers/gpu/drm/i915/display/intel_display_device.c

903

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

drivers/gpu/drm/i915/display/intel_display_device.c

995

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \

drivers/gpu/drm/i915/display/intel_display_device.h

268

DISPLAY_INFO((display))->pipe_offsets[PIPE_A] + \

drivers/gpu/drm/i915/display/intel_display_device.h

278

DISPLAY_INFO((display))->cursor_offsets[PIPE_A] + \

drivers/gpu/drm/i915/display/intel_display_irq.c

1353

pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_display_irq.c

1844

case PIPE_A:

drivers/gpu/drm/i915/display/intel_display_irq.c

2008

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2022

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2023

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2087

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

414

i915_enable_pipestat(display, PIPE_A,

drivers/gpu/drm/i915/display/intel_display_irq.c

563

case PIPE_A:

drivers/gpu/drm/i915/display/intel_display_irq.c

718

intel_pch_fifo_underrun_irq_handler(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_irq.c

727

case PIPE_A:

drivers/gpu/drm/i915/display/intel_display_irq.c

848

case PIPE_A:

drivers/gpu/drm/i915/display/intel_display_limits.h

34

TRANSCODER_A = PIPE_A,

drivers/gpu/drm/i915/display/intel_display_power.c

1801

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

drivers/gpu/drm/i915/display/intel_display_power.h

123

((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_A))

drivers/gpu/drm/i915/display/intel_display_power.h

125

((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_PANEL_FITTER_A))

drivers/gpu/drm/i915/display/intel_display_power_map.c

1326

.irq_pipe_mask = BIT(PIPE_A),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1482

.irq_pipe_mask = BIT(PIPE_A),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1648

.irq_pipe_mask = BIT(PIPE_A),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1720

.irq_pipe_mask = BIT(PIPE_A),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1148

if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1149

i830_enable_pipe(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1158

i830_disable_pipe(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1164

return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

1304

if (pipe != PIPE_A)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1583

assert_pll_disabled(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1738

enum pipe pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1769

enum pipe pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_display_power_well.c

201

if (irq_pipe_mask & BIT(PIPE_A))

drivers/gpu/drm/i915/display/intel_display_regs.h

2230

#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */

drivers/gpu/drm/i915/display/intel_display_trace.h

67

static_assert(PIPE_A == _TRACE_PIPE_A);

drivers/gpu/drm/i915/display/intel_dmc.c

258

#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))

drivers/gpu/drm/i915/display/intel_dmc.c

477

for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)

drivers/gpu/drm/i915/display/intel_dmc.c

494

MTL_PIPEDMC_GATING_DIS(PIPE_A) |

drivers/gpu/drm/i915/display/intel_dmc.c

938

PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A));

drivers/gpu/drm/i915/display/intel_dmc_regs.h

288

#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

693

case PIPE_A:

drivers/gpu/drm/i915/display/intel_dpio_phy.c

707

case PIPE_A:

drivers/gpu/drm/i915/display/intel_dpll.c

1409

if (crtc->pipe != PIPE_A)

drivers/gpu/drm/i915/display/intel_dpll.c

1435

if (crtc->pipe != PIPE_A)

drivers/gpu/drm/i915/display/intel_dpll.c

1947

if (pipe == PIPE_A)

drivers/gpu/drm/i915/display/intel_dpll.c

1953

if (pipe == PIPE_A)

drivers/gpu/drm/i915/display/intel_dpll.c

2152

if (pipe != PIPE_A) {

drivers/gpu/drm/i915/display/intel_dpll.c

2226

if (pipe != PIPE_A)

drivers/gpu/drm/i915/display/intel_dpll.c

2244

if (pipe != PIPE_A)

drivers/gpu/drm/i915/display/intel_dpll.c

401

if (display->platform.cherryview && crtc->pipe != PIPE_A)

drivers/gpu/drm/i915/display/intel_fdi.c

221

case PIPE_A:

drivers/gpu/drm/i915/display/intel_fdi.c

419

case PIPE_A:

drivers/gpu/drm/i915/display/intel_fdi.c

866

intel_de_write(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

876

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

877

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

882

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

911

intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));

drivers/gpu/drm/i915/display/intel_fdi.c

915

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

916

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

922

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

924

intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

946

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

947

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

959

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

962

intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

983

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

987

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

990

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

991

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

232

u32 bit = (pipe == PIPE_A) ?

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

296

u32 bit = (pch_transcoder == PIPE_A) ?

drivers/gpu/drm/i915/display/intel_gvt_api.c

38

if (pipe < PIPE_A || pipe >= I915_MAX_PIPES)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

670

enum pipe pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_pch.c

278

intel_de_rmw(display, TRANS_CHICKEN1(PIPE_A), 0,

drivers/gpu/drm/i915/display/intel_pch_display.c

123

(val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))

drivers/gpu/drm/i915/display/intel_pch_display.c

131

val |= SDVO_PIPE_SEL(PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

142

(val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))

drivers/gpu/drm/i915/display/intel_pch_display.c

150

val |= DP_PIPE_SEL(PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

28

(HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

36

return PIPE_A;

drivers/gpu/drm/i915/display/intel_pch_display.c

554

assert_fdi_rx_enabled(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

556

val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));

drivers/gpu/drm/i915/display/intel_pch_display.c

562

intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val);

drivers/gpu/drm/i915/display/intel_pch_display.c

588

intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);

drivers/gpu/drm/i915/display/intel_pch_display.c

598

assert_pch_transcoder_disabled(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

603

ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

629

tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_pfit.c

90

max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;

drivers/gpu/drm/i915/display/intel_pipe_crc.c

178

case PIPE_A:

drivers/gpu/drm/i915/display/intel_pipe_crc.c

239

case PIPE_A:

drivers/gpu/drm/i915/display/intel_pipe_crc.c

316

pipe_config->hw.active && crtc->pipe == PIPE_A &&

drivers/gpu/drm/i915/display/intel_pps.c

1162

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_pps.c

1252

if (pipe != PIPE_A && pipe != PIPE_B)

drivers/gpu/drm/i915/display/intel_pps.c

1255

if (pipe != PIPE_A && pipe != PIPE_B)

drivers/gpu/drm/i915/display/intel_pps.c

1256

pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_pps.c

173

unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);

drivers/gpu/drm/i915/display/intel_pps.c

230

pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_pps.c

301

for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {

drivers/gpu/drm/i915/display/intel_pps.c

46

case PIPE_A:

drivers/gpu/drm/i915/display/intel_psr.c

1276

return pipe == PIPE_A && port == PORT_A;

drivers/gpu/drm/i915/display/intel_psr.c

1856

if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&

drivers/gpu/drm/i915/display/intel_sdvo.c

1865

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_sdvo.c

1866

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_sdvo.c

1869

temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);

drivers/gpu/drm/i915/display/intel_sdvo.c

1875

intel_wait_for_vblank_if_active(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_sdvo.c

1876

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_sdvo.c

1877

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_vdsc.c

103

drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);

drivers/gpu/drm/i915/display/intel_vdsc.c

462

pipe == PIPE_A)

drivers/gpu/drm/i915/display/intel_vga.c

210

pipe = PIPE_A;

drivers/gpu/drm/i915/display/intel_vrr.c

380

((pipe == PIPE_A) || (pipe == PIPE_B)));

drivers/gpu/drm/i915/display/skl_universal_plane.c

445

return pipe - PIPE_A + INTEL_FBC_A;

drivers/gpu/drm/i915/display/skl_watermark.c

1012

.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1014

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1028

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1030

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

1045

.active_pipes = BIT(PIPE_A),

drivers/gpu/drm/i915/display/skl_watermark.c

1047

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1059

.active_pipes = BIT(PIPE_A),

drivers/gpu/drm/i915/display/skl_watermark.c

1061

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1073

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

1075

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1086

.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

1088

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1100

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

1102

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1114

.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1116

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1128

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1130

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1143

.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1145

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1159

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1161

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

3378

case PIPE_A:

drivers/gpu/drm/i915/display/skl_watermark.c

3380

active_pipes &= BIT(PIPE_A) | BIT(PIPE_D);

drivers/gpu/drm/i915/display/skl_watermark.c

756

.active_pipes = BIT(PIPE_A),

drivers/gpu/drm/i915/display/skl_watermark.c

758

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

768

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

770

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

781

.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

783

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

795

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

797

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

819

.active_pipes = BIT(PIPE_A),

drivers/gpu/drm/i915/display/skl_watermark.c

821

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

831

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

833

[PIPE_A] = BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

844

.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

846

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

858

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

860

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

872

.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

874

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

886

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

888

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

901

.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

903

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

917

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

919

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

930

.active_pipes = BIT(PIPE_A),

drivers/gpu/drm/i915/display/skl_watermark.c

932

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

942

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

944

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

955

.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

957

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

969

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

971

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

983

.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

985

[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

997

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

999

[PIPE_A] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/vlv_dsi.c

1962

encoder->pipe_mask = BIT(PIPE_A);

drivers/gpu/drm/i915/display/vlv_dsi.c

996

*pipe = port == PORT_A ? PIPE_A : PIPE_B;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1298

[0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},

drivers/gpu/drm/i915/gvt/cmd_parser.c

1300

[2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},

drivers/gpu/drm/i915/gvt/cmd_parser.c

1354

info->pipe = PIPE_A;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1367

info->pipe = PIPE_A;

drivers/gpu/drm/i915/gvt/display.c

60

pipe = PIPE_A;

drivers/gpu/drm/i915/gvt/display.c

643

[PIPE_A] = PIPE_A_VBLANK,

drivers/gpu/drm/i915/gvt/display.c

649

if (pipe < PIPE_A || pipe > PIPE_C)

drivers/gpu/drm/i915/gvt/display.c

91

pipe < PIPE_A || pipe >= I915_MAX_PIPES))

drivers/gpu/drm/i915/gvt/display_helpers.h

34

for ((__p) = PIPE_A; (__p) < I915_MAX_PIPES; (__p)++) \

drivers/gpu/drm/i915/gvt/handlers.c

1027

calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

1051

calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

2307

MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2308

MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2316

MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2317

MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2342

MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2345

MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2348

MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2495

MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2497

MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2499

MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2639

MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2640

MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2646

MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2647

MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2653

MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2654

MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2660

MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2661

MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2662

MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2663

MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2675

MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2679

MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2680

MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2681

MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2691

MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2695

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2696

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2697

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2698

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2710

MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2711

MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2712

MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2713

MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2725

MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2726

MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2727

MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2728

MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

713

vgpu->id, pipe_name(PIPE_A), new_rate);

drivers/gpu/drm/i915/gvt/handlers.c

913

calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

916

calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

919

calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))

drivers/gpu/drm/i915/gvt/interrupt.c

512

DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));

drivers/gpu/drm/i915/gvt/reg.h

68

(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \

drivers/gpu/drm/i915/gvt/reg.h

78

(((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1002

MMIO_D(PLANE_WM_TRANS(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1003

MMIO_D(PLANE_WM_TRANS(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1004

MMIO_D(PLANE_WM_TRANS(PIPE_A, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1011

MMIO_D(CUR_WM_TRANS(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1014

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1015

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1016

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1017

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1026

MMIO_D(PLANE_AUX_DIST(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1027

MMIO_D(PLANE_AUX_DIST(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1028

MMIO_D(PLANE_AUX_DIST(PIPE_A, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1029

MMIO_D(PLANE_AUX_DIST(PIPE_A, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1038

MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1039

MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1040

MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1041

MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1050

MMIO_D(PLANE_CTL(PIPE_A, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1053

MMIO_D(PLANE_SURF(PIPE_A, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1095

MMIO_D(PLANE_KEYVAL(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1098

MMIO_D(PLANE_KEYMAX(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1101

MMIO_D(PLANE_KEYMSK(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

145

MMIO_D(PIPEDSL(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

153

MMIO_D(PIPESTAT(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

157

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

161

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

165

MMIO_D(CURCNTR(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

168

MMIO_D(CURPOS(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

171

MMIO_D(CURBASE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

174

MMIO_D(CUR_FBC_CTL(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

184

MMIO_D(DSPCNTR(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

185

MMIO_D(DSPADDR(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

186

MMIO_D(DSPSTRIDE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

187

MMIO_D(DSPPOS(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

188

MMIO_D(DSPSIZE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

189

MMIO_D(DSPSURF(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

190

MMIO_D(DSPOFFSET(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

191

MMIO_D(DSPSURFLIVE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

192

MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

211

MMIO_D(SPRCTL(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

212

MMIO_D(SPRLINOFF(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

213

MMIO_D(SPRSTRIDE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

214

MMIO_D(SPRPOS(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

215

MMIO_D(SPRSIZE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

216

MMIO_D(SPRKEYVAL(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

217

MMIO_D(SPRKEYMSK(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

218

MMIO_D(SPRSURF(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

219

MMIO_D(SPRKEYMAX(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

220

MMIO_D(SPROFFSET(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

221

MMIO_D(SPRSCALE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

222

MMIO_D(SPRSURFLIVE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

223

MMIO_D(REG_50080(PIPE_A, PLANE_SPRITE0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

317

MMIO_D(PF_CTL(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

318

MMIO_D(PF_WIN_SZ(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

319

MMIO_D(PF_WIN_POS(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

320

MMIO_D(PF_VSCALE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

321

MMIO_D(PF_HSCALE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

332

MMIO_D(WM0_PIPE_ILK(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

351

MMIO_D(FDI_RX_IIR(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

354

MMIO_D(FDI_RX_IMR(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

357

MMIO_D(FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

382

MMIO_D(TRANS_DP_CTL(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

385

MMIO_D(TVIDEO_DIP_CTL(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

386

MMIO_D(TVIDEO_DIP_DATA(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

387

MMIO_D(TVIDEO_DIP_GCP(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

447

MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

448

MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

449

MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

450

MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

451

MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

452

MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

453

MMIO_D(PIPE_CSC_MODE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

454

MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

455

MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

456

MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

457

MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

458

MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

459

MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

486

MMIO_D(PREC_PAL_INDEX(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

487

MMIO_D(PREC_PAL_DATA(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

488

MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

500

MMIO_D(WM_LINETIME(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

522

MMIO_D(GAMMA_MODE(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

557

MMIO_D(HSW_AUD_CFG(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

559

MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

717

MMIO_F(LGC_PALETTE(PIPE_A, 0), 1024);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

769

MMIO_D(GEN8_DE_PIPE_IMR(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

770

MMIO_D(GEN8_DE_PIPE_IER(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

771

MMIO_D(GEN8_DE_PIPE_IIR(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

772

MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

820

MMIO_D(PIPE_MISC(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

839

MMIO_D(CHICKEN_PIPESL_1(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

957

MMIO_D(SKL_PS_WIN_POS(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

958

MMIO_D(SKL_PS_WIN_POS(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

963

MMIO_D(SKL_PS_WIN_SZ(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

964

MMIO_D(SKL_PS_WIN_SZ(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

969

MMIO_D(SKL_PS_CTRL(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

970

MMIO_D(SKL_PS_CTRL(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

975

MMIO_D(PLANE_BUF_CFG(PIPE_A, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

976

MMIO_D(PLANE_BUF_CFG(PIPE_A, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

977

MMIO_D(PLANE_BUF_CFG(PIPE_A, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

978

MMIO_D(PLANE_BUF_CFG(PIPE_A, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

987

MMIO_D(CUR_BUF_CFG(PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

990

MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

991

MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

992

MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

999

MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8);