PCI_D3hot
pci_set_power_state(dev, PCI_D3hot);
pci_power_t weakest = PCI_D3hot;
if (state > PCI_D3hot)
state = PCI_D3hot;
pwr->lss[i][j].state = PCI_D3hot;
else if (hdev->pdev->current_state == PCI_D3hot)
pci_set_power_state(hdev->pdev, PCI_D3hot);
pci_set_power_state(hdev->pdev, PCI_D3hot);
pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
pci_set_power_state(qdev->pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) {
if (pci_pme_capable(pdev, PCI_D3hot))
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
{ PCI_D3hot, 0x04 },
if (pwr == PCI_D3hot)
pci_set_power_state(pdev, PCI_D3hot);
intel_opregion_notify_adapter(display, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
csr |= PCI_D3hot;
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
if (typhoon_sleep(tp, PCI_D3hot, 0) < 0)
if (typhoon_sleep(tp, PCI_D3hot, 0) < 0)
err = typhoon_sleep(tp, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
ssb_pcihost_set_power_state(sdev, PCI_D3hot);
ssb_pcihost_set_power_state(sdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
case PCI_D3hot: {
pci_set_power_state(bp->pdev, PCI_D3hot);
pci_set_power_state(bp->pdev, PCI_D3hot);
bnx2_set_power_state(bp, PCI_D3hot);
case PCI_D3hot:
bp, PCI_D3hot);
bnx2x_set_power_state(bp, PCI_D3hot);
bnx2x_set_power_state(bp, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
bnx2x_set_power_state(bp, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(tp->pdev, PCI_D3hot);
pci_set_power_state(tp->pdev, PCI_D3hot);
pci_enable_wake(tp->pdev, PCI_D3hot, 0);
pci_enable_wake(adapter->pdev, PCI_D3hot, enable);
pci_enable_wake(adapter->pdev, PCI_D3hot, adapter->wol_en);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_enable_wake(pdev, PCI_D3hot, 1);
qed_set_power_state(cdev, PCI_D3hot);
edev->ops->common->set_power_state(edev->cdev, PCI_D3hot);
pci_set_power_state (cp->pdev, PCI_D3hot);
return pci_set_power_state(pci_dev, PCI_D3hot);
return pci_set_power_state(pci_dev, PCI_D3hot);
return pci_set_power_state(pci_dev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
velocity_set_power_state(vptr, PCI_D3hot);
velocity_set_power_state(vptr, PCI_D3hot);
velocity_set_power_state(vptr, PCI_D3hot);
pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
velocity_set_power_state(vptr, PCI_D3hot);
velocity_set_power_state(vptr, PCI_D3hot);
velocity_set_power_state(vptr, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
writel((u32 __force)PCI_D3hot, ts->ep_pmstate);
pci_enable_wake(pdev, PCI_D3hot, 1);
pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
[PCI_D3hot] = ACPI_STATE_D3_HOT,
case PCI_D3hot:
[ACPI_STATE_D3_HOT] = PCI_D3hot,
return PCI_D3hot;
if (kexec_in_progress && (pci_dev->current_state <= PCI_D3hot))
need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
if (state == PCI_D3hot)
if (state == PCI_D3hot)
if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
error = pci_set_low_power_state(dev, PCI_D3hot, locked);
pci_enable_wake(dev, PCI_D3hot, enable);
return PCI_D3hot;
return PCI_D3hot;
pci_power_t state = PCI_D3hot;
return PCI_D3hot;
pci_dev->current_state != PCI_D3hot;
csr |= PCI_D3hot;
pci_set_power_state(pcidev, PCI_D3hot);
(__force int)PCI_D3hot) ? 1 : 0;
rc = pci_set_power_state(pdev, PCI_D3hot);
pci_set_power_state(dev, PCI_D3hot);
pci_set_power_state(pdev, PCI_D3hot);
return pdev->current_state < PCI_D3hot &&
if (state >= PCI_D3hot) {
state = PCI_D3hot;
if (pdev->current_state < PCI_D3hot && state >= PCI_D3hot) {
if (pdev->current_state >= PCI_D3hot && state <= PCI_D0)
if (needs_save && pdev->current_state >= PCI_D3hot) {
pci_set_power_state(pci, PCI_D3hot);
catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot);