PCI_CACHE_LINE_SIZE
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
case PCI_CACHE_LINE_SIZE:
case PCI_CACHE_LINE_SIZE:
case PCI_CACHE_LINE_SIZE:
case PCI_CACHE_LINE_SIZE:
case PCI_CACHE_LINE_SIZE:
case PCI_CACHE_LINE_SIZE:
case PCI_CACHE_LINE_SIZE:
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
case (PCI_CACHE_LINE_SIZE >> 2):
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
SAVED_BYTE(PCI_CACHE_LINE_SIZE));
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
SAVED_BYTE(PCI_CACHE_LINE_SIZE));
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
offset == PCI_CACHE_LINE_SIZE) {
grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff);
0, PCI_CACHE_LINE_SIZE);
0, PCI_CACHE_LINE_SIZE);
pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
(reg != PCI_CACHE_LINE_SIZE) && (reg != 0x44))
pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
if (pci_read_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, &cache_size)) {
if (pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, cache_size))
[PCI_CACHE_LINE_SIZE] = 0xff,
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
PCI_CACHE_LINE_SIZE,
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
dw_pcie_ep_writeb_dbi(ep, func_no, PCI_CACHE_LINE_SIZE,
PCI_CACHE_LINE_SIZE) {
PCI_CACHE_LINE_SIZE);
rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
PCI_CACHE_LINE_SIZE, temp_byte);
pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_CACHE_LINE_SIZE, CACHE);
pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_CACHE_LINE_SIZE, CACHE);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size);
bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
[PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
config_writeb(socket, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES / 4);
rc = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
.offset = PCI_CACHE_LINE_SIZE,
pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);