PCI_BASE_ADDRESS_MEM_MASK
PCI_BASE_ADDRESS_MEM_MASK;
PCI_BASE_ADDRESS_MEM_MASK) + IRONGATE_MEM);
base &= PCI_BASE_ADDRESS_MEM_MASK;
if (val & ~PCI_BASE_ADDRESS_MEM_MASK & ~PCI_BASE_ADDRESS_MEM_TYPE_64)
addr = (resource_size_t)(val & PCI_BASE_ADDRESS_MEM_MASK);
addr &= PCI_BASE_ADDRESS_MEM_MASK;
(unsigned long)early_ioremap(bar0 & PCI_BASE_ADDRESS_MEM_MASK, 0x10);
kexec_debug_8250_mmio32 = bar0 & PCI_BASE_ADDRESS_MEM_MASK;
bar_size &= PCI_BASE_ADDRESS_MEM_MASK;
aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
component_reg_phys = bar0 & PCI_BASE_ADDRESS_MEM_MASK;
& PCI_BASE_ADDRESS_MEM_MASK;
PCI_BASE_ADDRESS_MEM_MASK;
PCI_BASE_ADDRESS_MEM_MASK;
return addr & PCI_BASE_ADDRESS_MEM_MASK ? true : false;
size = (size & PCI_BASE_ADDRESS_MEM_MASK);
if ((size &= PCI_BASE_ADDRESS_MEM_MASK) == 0) {
start &= PCI_BASE_ADDRESS_MEM_MASK;
PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
addr = lo & PCI_BASE_ADDRESS_MEM_MASK;
return round_up((1 + ~(bar_val & PCI_BASE_ADDRESS_MEM_MASK)),
u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
(phys1 & PCI_BASE_ADDRESS_MEM_MASK);
(phys2 & PCI_BASE_ADDRESS_MEM_MASK);
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
phba->pcb->hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) +
if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
val64 = val & PCI_BASE_ADDRESS_MEM_MASK;
sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
mask64 = PCI_BASE_ADDRESS_MEM_MASK;
ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;
mask = ~PCI_BASE_ADDRESS_MEM_MASK;
cfg_addr &= PCI_BASE_ADDRESS_MEM_MASK;
~PCI_BASE_ADDRESS_MEM_MASK);
cfg_addr &= PCI_BASE_ADDRESS_MEM_MASK;
~PCI_BASE_ADDRESS_MEM_MASK);
PCI_BASE_ADDRESS_MEM_MASK;