MSR_IA32_MISC_ENABLE
rdmsr(MSR_IA32_MISC_ENABLE, low, high);
!wrmsr_safe(MSR_IA32_MISC_ENABLE,
if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
err = rdmsrq_safe(MSR_IA32_MISC_ENABLE, &misc_en);
if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0)
rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
if (msr_set_bit(MSR_IA32_MISC_ENABLE,
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
u64 misc_enable = mce_rdmsrq(MSR_IA32_MISC_ENABLE);
mce_wrmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
case MSR_IA32_MISC_ENABLE:
case MSR_IA32_MISC_ENABLE: {
MSR_IA32_MISC_ENABLE,
case MSR_IA32_MISC_ENABLE:
ctxt->misc_enable_saved = !rdmsrq_safe(MSR_IA32_MISC_ENABLE,
wrmsrq(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
msr_addr = MSR_IA32_MISC_ENABLE;
rdmsrq_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr);
rdmsrq(MSR_IA32_MISC_ENABLE, val);
wrmsrq(MSR_IA32_MISC_ENABLE, val);
rdmsrq(MSR_IA32_MISC_ENABLE, val);
rdmsrq(MSR_IA32_MISC_ENABLE, misc_en);
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
wrmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
if (!get_msr(master_cpu, MSR_IA32_MISC_ENABLE, &msr))
get_msr(cpu, MSR_IA32_MISC_ENABLE, &msr);
put_msr(cpu, MSR_IA32_MISC_ENABLE, msr);
put_msr(cpu, MSR_IA32_MISC_ENABLE, msr);
u64 val = rdmsr(MSR_IA32_MISC_ENABLE) & ~MSR_IA32_MISC_ENABLE_MWAIT;
wrmsr(MSR_IA32_MISC_ENABLE, val);
MSR_TEST_NON_ZERO(MSR_IA32_MISC_ENABLE,