MDIO_CTRL1
#define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1)
dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
MDIO_MMD_PMAPMD, MDIO_CTRL1,
MDIO_MMD_PMAPMD, MDIO_CTRL1,
MDIO_MMD_AN, MDIO_CTRL1,
MDIO_MMD_AN, MDIO_CTRL1,
MDIO_MMD_PMAPMD, MDIO_CTRL1,
err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1,
err = t3_mdio_change_bits(phy, mmd, MDIO_CTRL1, MDIO_CTRL1_LPOWER,
err = t3_mdio_read(phy, mmd, MDIO_CTRL1, &ctl);
hw->phy.ops.read_reg(hw, MDIO_CTRL1,
hw->phy.ops.write_reg(hw, MDIO_CTRL1,
hw->phy.ops.read_reg(hw, MDIO_CTRL1,
hw->phy.ops.write_reg(hw, MDIO_CTRL1,
hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
hw->phy.ops.write_reg(hw, MDIO_CTRL1,
status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK,
MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK,
MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK,
ef4_mdio_set_flag(efx, mmd, MDIO_CTRL1,
reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
ef4_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET);
ctrl = ef4_mdio_read(port, mmd, MDIO_CTRL1);
stat = ef4_mdio_read(efx, mmd, MDIO_CTRL1);
ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1,
MDIO_CTRL1);
MDIO_CTRL1);
xpcs_modify(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1,
xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0);
xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0);
ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN);
ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST,
return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1,
pcs_ctrl1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL1);
{ MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
case MDIO_CTRL1:
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
{ MDIO_MMD_PMAPMD, MDIO_CTRL1,
{ MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0 },
{ MDIO_MMD_PCS, MDIO_CTRL1, 0x0 },
{ MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
{ MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
unit + MDIO_CTRL1, val,
ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
u16 reg = MDIO_CTRL1;
u16 reg = MDIO_CTRL1;
u16 reg = MDIO_CTRL1;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
MDIO_CTRL1, val,
pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1);
xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1, pcs_value);
MDIO_CTRL1);
value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1);
xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value);