drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11232

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13139

struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3374

struct dc_stream_state *del_streams[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1301

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1582

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1684

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1768

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1868

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1952

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2052

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2132

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2229

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2307

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2361

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2430

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2499

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1425

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1101

bool tried[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1102

int kbps_increase[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1265

struct dsc_mst_fairness_params params[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1436

struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1452

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1567

bool computed_streams[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1637

bool computed_streams[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

998

bool bpp_increased[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

999

int initial_slack[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3012

const struct pipe_ctx *active_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

173

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

128

for (k = 0; k < MAX_PIPES; k++)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

526

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

529

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

576

uint32_t pix_clk_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

577

int p_state_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

578

int disp_src_width_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

579

int disp_src_height_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

580

uint64_t disp_src_refresh_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

581

bool is_scaled_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

298

bool dppclk_active[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

344

for (i = 0; i < MAX_PIPES * 2; ++i) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

419

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

422

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

467

uint32_t pix_clk_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

468

int p_state_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

469

int disp_src_width_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

470

int disp_src_height_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

471

uint64_t disp_src_refresh_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

472

bool is_scaled_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

171

bool dppclk_active[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

1251

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1312

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1619

struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1645

struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1659

struct pipe_ctx *pipe_set[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

2107

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2363

for (k = 0; k < MAX_PIPES; k++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2614

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2754

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3592

char force_odm[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

4150

if (dsc_cfg_index < MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc.c

433

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

470

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

536

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

543

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc.c

602

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

609

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc.c

6372

enum mall_stream_type subvp_pipe_type[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

6748

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7032

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7039

if (i == MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7082

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7089

if (i == MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7260

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

727

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7286

const unsigned int max_pipes = MAX_PIPES;

drivers/gpu/drm/amd/display/dc/core/dc.c

733

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc.c

753

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7539

for (unsigned int pipe_idx = 0; pipe_idx < MAX_PIPES && pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

775

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

816

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

835

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

858

struct pipe_ctx *pipes_affected[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

866

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1982

struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1987

memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2482

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2499

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2519

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

846

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

948

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

104

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

240

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

256

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

306

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

402

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

408

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

421

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

472

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

511

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

535

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

585

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

607

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

634

int eng_ids_per_ep_id[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

635

int ep_ids_per_eng_id[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

639

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

652

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

662

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

670

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

695

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

739

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

111

if (current_snapshot->line_count >= MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1488

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1781

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2037

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2047

struct pipe_ctx *opp_heads[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2063

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2072

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2082

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2091

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2096

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2105

if (j < MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2304

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2459

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2460

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3279

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3685

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4412

struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4413

struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4414

struct dc_stream_state *add_streams[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5990

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5991

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

771

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

151

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

317

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

464

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

768

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

798

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

836

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

863

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

869

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

893

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

899

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

935

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dc.h

1258

uint32_t dml21_force_pstate_method_values[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1275

uint32_t acpi_transition_bitmasks[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1925

bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */

drivers/gpu/drm/amd/display/dc/dc.h

2003

struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2004

struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2005

struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2006

struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2007

struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2008

struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2009

struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3134

} hubp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3174

} dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3183

uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */

drivers/gpu/drm/amd/display/dc/dc.h

3184

uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */

drivers/gpu/drm/amd/display/dc/dc.h

3185

uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */

drivers/gpu/drm/amd/display/dc/dc.h

3186

uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */

drivers/gpu/drm/amd/display/dc/dc.h

3187

uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */

drivers/gpu/drm/amd/display/dc/dc.h

3190

uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */

drivers/gpu/drm/amd/display/dc/dc.h

3191

uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */

drivers/gpu/drm/amd/display/dc/dc.h

3192

uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */

drivers/gpu/drm/amd/display/dc/dc.h

3193

uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */

drivers/gpu/drm/amd/display/dc/dc.h

3196

uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */

drivers/gpu/drm/amd/display/dc/dc.h

3197

uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */

drivers/gpu/drm/amd/display/dc/dc.h

3198

uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */

drivers/gpu/drm/amd/display/dc/dc.h

3199

uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */

drivers/gpu/drm/amd/display/dc/dc.h

3200

uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */

drivers/gpu/drm/amd/display/dc/dc.h

3201

uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */

drivers/gpu/drm/amd/display/dc/dc.h

3202

uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */

drivers/gpu/drm/amd/display/dc/dc.h

3210

uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */

drivers/gpu/drm/amd/display/dc/dc.h

3274

} dsc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3279

uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */

drivers/gpu/drm/amd/display/dc/dc.h

3280

uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */

drivers/gpu/drm/amd/display/dc/dc.h

3281

uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */

drivers/gpu/drm/amd/display/dc/dc.h

3282

uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */

drivers/gpu/drm/amd/display/dc/dc.h

3283

uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */

drivers/gpu/drm/amd/display/dc/dc.h

3284

uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */

drivers/gpu/drm/amd/display/dc/dc.h

3285

uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */

drivers/gpu/drm/amd/display/dc/dc.h

3286

uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */

drivers/gpu/drm/amd/display/dc/dc.h

3289

uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */

drivers/gpu/drm/amd/display/dc/dc.h

3290

uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */

drivers/gpu/drm/amd/display/dc/dc.h

3293

uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */

drivers/gpu/drm/amd/display/dc/dc.h

3294

uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */

drivers/gpu/drm/amd/display/dc/dc.h

3295

uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */

drivers/gpu/drm/amd/display/dc/dc.h

3298

uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */

drivers/gpu/drm/amd/display/dc/dc.h

3299

uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */

drivers/gpu/drm/amd/display/dc/dc.h

3300

uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */

drivers/gpu/drm/amd/display/dc/dc.h

3352

} opp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3501

} optc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

929

bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

420

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

138

type OTG_ADD_PIXEL[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

139

type OTG_DROP_PIXEL[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

175

type DTBCLK_DTO_ENABLE[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

176

type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

177

type PIPE_DTO_SRC_SEL[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

178

type DTBCLK_DTO_DIV[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

367

type DP_DTO_ENABLE[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

407

uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

414

uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

415

uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

447

uint32_t DP_DTO_MODULO[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

448

uint32_t DP_DTO_PHASE[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

252

uint32_t PHASE[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

253

uint32_t MODULO[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

254

uint32_t PIXEL_RATE_CNTL[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

305

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

128

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

711

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2047

int pipe_split_from[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2339

int pipe_split_from[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1176

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1206

int split[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1207

bool merge[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1290

struct vba_vars_st *vba, int split[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1291

bool merge[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1408

unsigned int cur_policy[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1418

memset(split, 0, MAX_PIPES * sizeof(int));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1419

memset(merge, 0, MAX_PIPES * sizeof(bool));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1481

memset(split, 0, MAX_PIPES * sizeof(int));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1482

memset(merge, 0, MAX_PIPES * sizeof(bool));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1916

bool newly_split[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2118

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2119

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

498

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

514

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

28

for (int i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1004

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

354

unsigned int preferred_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

355

unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

423

unsigned int preferred_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

424

unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

47

unsigned int odm_slice_end_x[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

48

struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

626

unsigned int pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

664

unsigned int pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

926

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

942

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

958

struct dml2_pipe_combine_factor odm_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

975

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

131

struct dml2_pipe_combine_factor odm_factors[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

132

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1010

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1291

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1330

for (k = 0; k < MAX_PIPES; k++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

997

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

523

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

100

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

103

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

237

enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1146

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2190

for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2231

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2432

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3510

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1474

TRACE_DC_PIPE_STATE(pipe_ctx, MAX_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1621

bool tg_enabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1755

if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2434

uint64_t phase[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2435

uint64_t modulo[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2446

hw_crtc_timing = kzalloc_objs(*hw_crtc_timing, MAX_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3623

for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1190

int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3209

for (j = 0; j < MAX_PIPES; j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

829

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

839

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

303

for (j = 0; j < MAX_PIPES; j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1301

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

178

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

405

bool otg_disabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

437

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

490

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1150

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1263

bool otg_disabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1295

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1404

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1792

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

436

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

646

bool tg_enabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

780

if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1079

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1618

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1654

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1655

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1701

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1791

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1792

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1898

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1899

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1996

struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3987

for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

766

struct pipe_ctx *opp_heads[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

813

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

814

struct pipe_ctx *opp_heads[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

190

if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

52

bool tg_enabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1226

#define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES)

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1977

struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

226

int opp_inst[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

249

struct mem_input *mis[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

250

struct hubp *hubps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

251

struct input_pixel_processor *ipps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

252

struct transform *transforms[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

253

struct dpp *dpps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

254

struct output_pixel_processor *opps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

255

struct timing_generator *timing_generators[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

256

struct stream_encoder *stream_enc[MAX_PIPES * 2];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

261

struct dce_aux *engines[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

262

struct dce_i2c_hw *hw_i2cs[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

263

struct dce_i2c_sw *sw_i2cs[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

274

struct display_stream_compressor *dscs[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

299

struct dc_3dlut *mpc_lut[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

300

struct dc_transfer_func *mpc_shaper[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

333

struct abm *multiple_abms[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

528

struct link_enc_assignment link_enc_assignments[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

530

struct link_enc_assignment transient_assignments[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

534

struct pipe_ctx pipe_ctx[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

535

bool is_stream_enc_acquired[MAX_PIPES * 2];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

536

bool is_audio_acquired[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

539

bool is_dsc_acquired[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

549

bool is_mpc_3dlut_acquired[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

560

struct dce_watermarks urgent_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

561

struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

562

struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

563

struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

619

struct dc_stream_state *streams[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

624

struct dc_stream_status stream_status[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

196

int pipe_dppclk_khz[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

198

bool dpp_clock_gated[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

46

#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

97

struct pipe_topology_line pipe_log_lines[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

231

int dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

232

int mpcc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

240

bool mpcc_disconnect_pending[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

35

bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/resource.h

399

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

409

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

418

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

217

if (pipe_offset >= MAX_PIPES)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

147

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

641

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

70

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

79

struct audio_output audio_output[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

80

struct dc_stream_state *streams_on_link[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

948

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

959

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

937

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

157

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

158

struct dc_stream_state *streams[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

216

struct pipe_ctx *pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

222

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

42

struct pipe_ctx *pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/link/link_resource.c

40

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

676

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

700

for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

328

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

126

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

217

for (unsigned int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

285

for (unsigned int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

59

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1031

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1194

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

533

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

798

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

903

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

915

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

59

bool first_preferred_memory_for_opp[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

60

bool second_preferred_memory_for_opp[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

83

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

94

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

141

if (dsc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

232

if (hubp_dpp_inst < MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

353

if (mpcc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

363

if (opp_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

373

if (optc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

561

memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool));

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

131

if (dsc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

237

if (hubp_dpp_inst < MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

373

if (mpcc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

383

if (opp_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

394

if (optc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

642

memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1454

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2067

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2068

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2095

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

805

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

806

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

876

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1794

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1795

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1796

bool newly_split[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

317

uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

318

uint8_t pipe_counted[MAX_PIPES] = {0};

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

133

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

161

[MAX_PIPES] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

177

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

154

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

155

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

160

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

13

[MAX_PIPES] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

13

[MAX_PIPES] = GENMASK(7, 0),