Symbol: M
arch/arm/include/asm/hw_breakpoint.h
110
#define ARM_DBG_READ(N, M, OP2, VAL) do {\
arch/arm/include/asm/hw_breakpoint.h
111
asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
arch/arm/include/asm/hw_breakpoint.h
114
#define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
arch/arm/include/asm/hw_breakpoint.h
115
asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
arch/arm/kernel/hw_breakpoint.c
49
#define READ_WB_REG_CASE(OP2, M, VAL) \
arch/arm/kernel/hw_breakpoint.c
50
case ((OP2 << 4) + M): \
arch/arm/kernel/hw_breakpoint.c
51
ARM_DBG_READ(c0, c ## M, OP2, VAL); \
arch/arm/kernel/hw_breakpoint.c
54
#define WRITE_WB_REG_CASE(OP2, M, VAL) \
arch/arm/kernel/hw_breakpoint.c
55
case ((OP2 << 4) + M): \
arch/arm/kernel/hw_breakpoint.c
56
ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
arch/mips/include/asm/fpu_emulator.h
157
#define MIPS_FPU_EMU_INC_STATS(M) \
arch/mips/include/asm/fpu_emulator.h
160
__this_cpu_inc(fpuemustats.M); \
arch/mips/include/asm/fpu_emulator.h
165
#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
arch/mips/include/asm/mips-r2-to-r6-emul.h
46
#define MIPS_R2_STATS(M) \
arch/mips/include/asm/mips-r2-to-r6-emul.h
52
__this_cpu_inc(mipsr2emustats.M); \
arch/mips/include/asm/mips-r2-to-r6-emul.h
56
__this_cpu_inc(mipsr2bdemustats.M); \
arch/mips/include/asm/mips-r2-to-r6-emul.h
61
#define MIPS_R2BR_STATS(M) \
arch/mips/include/asm/mips-r2-to-r6-emul.h
64
__this_cpu_inc(mipsr2bremustats.M); \
arch/mips/include/asm/mips-r2-to-r6-emul.h
70
#define MIPS_R2_STATS(M) do { } while (0)
arch/mips/include/asm/mips-r2-to-r6-emul.h
71
#define MIPS_R2BR_STATS(M) do { } while (0)
arch/mips/mm/uasm-micromips.c
101
[insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
102
[insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
103
[insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
104
[insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
105
[insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
106
[insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
107
[insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
108
[insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
109
[insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
110
[insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
111
[insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
112
[insn_sw] = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
113
[insn_sync] = {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS},
arch/mips/mm/uasm-micromips.c
114
[insn_tlbp] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0},
arch/mips/mm/uasm-micromips.c
115
[insn_tlbr] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0},
arch/mips/mm/uasm-micromips.c
116
[insn_tlbwi] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0},
arch/mips/mm/uasm-micromips.c
117
[insn_tlbwr] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0},
arch/mips/mm/uasm-micromips.c
118
[insn_wait] = {M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM},
arch/mips/mm/uasm-micromips.c
119
[insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS},
arch/mips/mm/uasm-micromips.c
120
[insn_xor] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
121
[insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
arch/mips/mm/uasm-micromips.c
124
[insn_syscall] = {M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
arch/mips/mm/uasm-micromips.c
43
[insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
44
[insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
45
[insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
46
[insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
arch/mips/mm/uasm-micromips.c
47
[insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-micromips.c
49
[insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-micromips.c
51
[insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-micromips.c
53
[insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
arch/mips/mm/uasm-micromips.c
54
[insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
55
[insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
arch/mips/mm/uasm-micromips.c
56
[insn_cfcmsa] = {M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE},
arch/mips/mm/uasm-micromips.c
57
[insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
arch/mips/mm/uasm-micromips.c
58
[insn_ctcmsa] = {M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE},
arch/mips/mm/uasm-micromips.c
61
[insn_di] = {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS},
arch/mips/mm/uasm-micromips.c
62
[insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},
arch/mips/mm/uasm-micromips.c
73
[insn_eret] = {M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0},
arch/mips/mm/uasm-micromips.c
74
[insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},
arch/mips/mm/uasm-micromips.c
75
[insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},
arch/mips/mm/uasm-micromips.c
76
[insn_j] = {M(mm_j32_op, 0, 0, 0, 0, 0), JIMM},
arch/mips/mm/uasm-micromips.c
77
[insn_jal] = {M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM},
arch/mips/mm/uasm-micromips.c
78
[insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS},
arch/mips/mm/uasm-micromips.c
79
[insn_jr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
arch/mips/mm/uasm-micromips.c
80
[insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
82
[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
83
[insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-micromips.c
85
[insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},
arch/mips/mm/uasm-micromips.c
86
[insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
87
[insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
88
[insn_mfhi] = {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS},
arch/mips/mm/uasm-micromips.c
89
[insn_mflo] = {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS},
arch/mips/mm/uasm-micromips.c
90
[insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
91
[insn_mthi] = {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS},
arch/mips/mm/uasm-micromips.c
92
[insn_mtlo] = {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS},
arch/mips/mm/uasm-micromips.c
93
[insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
94
[insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
95
[insn_ori] = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
arch/mips/mm/uasm-micromips.c
96
[insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
98
[insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-mips.c
100
[insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
101
[insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
102
[insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
103
[insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
104
[insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
105
[insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
106
[insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
107
[insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
108
[insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
109
[insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op), 0},
arch/mips/mm/uasm-mips.c
110
[insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
111
[insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
112
[insn_j] = {M(j_op, 0, 0, 0, 0, 0), JIMM},
arch/mips/mm/uasm-mips.c
113
[insn_jal] = {M(jal_op, 0, 0, 0, 0, 0), JIMM},
arch/mips/mm/uasm-mips.c
114
[insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD},
arch/mips/mm/uasm-mips.c
116
[insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS},
arch/mips/mm/uasm-mips.c
118
[insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS},
arch/mips/mm/uasm-mips.c
120
[insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
121
[insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
122
[insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
123
[insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
124
[insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},
arch/mips/mm/uasm-mips.c
125
[insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
126
[insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
127
[insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
129
[insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
130
[insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
135
[insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM},
arch/mips/mm/uasm-mips.c
136
[insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
137
[insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
138
[insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
139
[insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
140
[insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
141
[insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
arch/mips/mm/uasm-mips.c
142
[insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
arch/mips/mm/uasm-mips.c
143
[insn_modu] = {M(spec_op, 0, 0, 0, divu_modu_op, divu_op),
arch/mips/mm/uasm-mips.c
145
[insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
146
[insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
147
[insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
148
[insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
149
[insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
arch/mips/mm/uasm-mips.c
150
[insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
arch/mips/mm/uasm-mips.c
151
[insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
arch/mips/mm/uasm-mips.c
153
[insn_muhu] = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),
arch/mips/mm/uasm-mips.c
156
[insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
158
[insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
160
[insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
arch/mips/mm/uasm-mips.c
161
[insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
162
[insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
163
[insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
arch/mips/mm/uasm-mips.c
165
[insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
169
[insn_rfe] = {M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0},
arch/mips/mm/uasm-mips.c
170
[insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
171
[insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
173
[insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
174
[insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
179
[insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
180
[insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
181
[insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
182
[insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
183
[insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
184
[insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
185
[insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
186
[insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
187
[insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
188
[insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
189
[insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
190
[insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
191
[insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
192
[insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
193
[insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
194
[insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
195
[insn_sync] = {M(spec_op, 0, 0, 0, 0, sync_op), RE},
arch/mips/mm/uasm-mips.c
196
[insn_syscall] = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
arch/mips/mm/uasm-mips.c
197
[insn_tlbp] = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0},
arch/mips/mm/uasm-mips.c
198
[insn_tlbr] = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0},
arch/mips/mm/uasm-mips.c
199
[insn_tlbwi] = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0},
arch/mips/mm/uasm-mips.c
200
[insn_tlbwr] = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0},
arch/mips/mm/uasm-mips.c
201
[insn_wait] = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM},
arch/mips/mm/uasm-mips.c
202
[insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD},
arch/mips/mm/uasm-mips.c
203
[insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
204
[insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
arch/mips/mm/uasm-mips.c
205
[insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},
arch/mips/mm/uasm-mips.c
51
[insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
52
[insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
53
[insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
54
[insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
arch/mips/mm/uasm-mips.c
55
[insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
56
[insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
57
[insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
58
[insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
59
[insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-mips.c
60
[insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-mips.c
61
[insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-mips.c
62
[insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-mips.c
63
[insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-mips.c
64
[insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},
arch/mips/mm/uasm-mips.c
65
[insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
66
[insn_break] = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM},
arch/mips/mm/uasm-mips.c
68
[insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
72
[insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
arch/mips/mm/uasm-mips.c
73
[insn_cfcmsa] = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
arch/mips/mm/uasm-mips.c
74
[insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
arch/mips/mm/uasm-mips.c
75
[insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
arch/mips/mm/uasm-mips.c
76
[insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
77
[insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
78
[insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
arch/mips/mm/uasm-mips.c
79
[insn_ddivu_r6] = {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op),
arch/mips/mm/uasm-mips.c
81
[insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
arch/mips/mm/uasm-mips.c
82
[insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
83
[insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
84
[insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
85
[insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
arch/mips/mm/uasm-mips.c
86
[insn_divu_r6] = {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op),
arch/mips/mm/uasm-mips.c
88
[insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
89
[insn_dmodu] = {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op),
arch/mips/mm/uasm-mips.c
91
[insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
92
[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
arch/mips/mm/uasm-mips.c
93
[insn_dmulu] = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),
arch/mips/mm/uasm-mips.c
95
[insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
96
[insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
97
[insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
arch/mips/mm/uasm-mips.c
98
[insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
arch/mips/mm/uasm-mips.c
99
[insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
arch/powerpc/xmon/ppc-opc.c
2460
#define M_MASK M (0x3f, 1)
arch/powerpc/xmon/ppc-opc.c
2467
#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
arch/powerpc/xmon/ppc-opc.c
4586
{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4587
{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4589
{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4590
{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4594
{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4595
{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4598
{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4599
{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4601
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4602
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4605
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4606
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4608
{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4609
{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
7104
{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
arch/powerpc/xmon/ppc-opc.c
7105
{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
arch/sh/math-emu/math.c
101
#define ARITH_X(SZ,OP,M,N) do{ \
arch/sh/math-emu/math.c
103
UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
arch/sh/math-emu/math.c
70
#define CMP_X(SZ,R,M,N) do{ \
arch/sh/math-emu/math.c
72
UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
arch/sh/math-emu/math.c
74
#define EQ_X(SZ,R,M,N) do{ \
arch/sh/math-emu/math.c
76
UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
arch/sparc/kernel/traps_64.c
1101
/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
arch/sparc/kernel/traps_64.c
1102
/*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
arch/sparc/kernel/traps_64.c
1103
/*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
arch/sparc/kernel/traps_64.c
1104
/*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
arch/sparc/kernel/traps_64.c
1105
/*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
arch/sparc/kernel/traps_64.c
1106
/*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
arch/sparc/kernel/traps_64.c
1107
/*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
arch/sparc/kernel/traps_64.c
1108
/*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
arch/sparc/kernel/traps_64.c
1109
/*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
arch/sparc/kernel/traps_64.c
1110
/*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
arch/sparc/kernel/traps_64.c
1111
/*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
arch/sparc/kernel/traps_64.c
1112
/*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
arch/sparc/kernel/traps_64.c
1113
/*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
arch/sparc/kernel/traps_64.c
1114
/*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
arch/sparc/kernel/traps_64.c
1115
/*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
arch/sparc/kernel/traps_64.c
1116
/*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
arch/sparc/kernel/traps_64.c
1117
/*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
arch/sparc/kernel/traps_64.c
1118
/*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
arch/sparc/kernel/traps_64.c
1119
/*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
arch/sparc/kernel/traps_64.c
1120
/*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
arch/sparc/kernel/traps_64.c
1121
/*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
arch/sparc/kernel/traps_64.c
1122
/*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
arch/sparc/kernel/traps_64.c
1123
/*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
arch/sparc/kernel/traps_64.c
1124
/*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
arch/sparc/kernel/traps_64.c
1125
/*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
arch/sparc/kernel/traps_64.c
1126
/*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
arch/sparc/kernel/traps_64.c
1127
/*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
arch/sparc/kernel/traps_64.c
1128
/*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
arch/sparc/kernel/traps_64.c
1129
/*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
arch/sparc/kernel/traps_64.c
1130
/*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
arch/sparc/kernel/traps_64.c
1131
/*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
arch/sparc/kernel/traps_64.c
1132
/*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
drivers/clk/pxa/clk-pxa25x.c
36
#define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c
58
const char *M;
drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c
63
M = "V";
drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c
65
M = "I";
drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c
67
M = "U";
drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c
76
src, M, UNMARK(r));
drivers/cpufreq/pxa3xx-cpufreq.c
77
.hss = HSS_##_hss##M, \
drivers/cpufreq/pxa3xx-cpufreq.c
78
.dmcfs = DMCFS_##_dmc##M, \
drivers/cpufreq/pxa3xx-cpufreq.c
79
.smcfs = SMCFS_##_smc##M, \
drivers/cpufreq/pxa3xx-cpufreq.c
80
.sflfs = SFLFS_##_sfl##M, \
drivers/edac/sb_edac.c
434
#define PCI_ID_TABLE_ENTRY(A, N, M, T) { \
drivers/edac/sb_edac.c
438
.n_imcs_per_sock = M, \
drivers/gpio/gpio-tegra186.c
1061
TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
drivers/gpio/gpio-tegra186.c
1122
TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
drivers/gpio/gpio-tegra186.c
1194
TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
drivers/gpio/gpio-tegra186.c
1293
TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6),
drivers/gpio/gpio-tegra186.c
1409
TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7),
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
404
val = M(cfg.m) | N(cfg.n) | INT_CTRL(0) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
249
pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
26
u64 M;
drivers/gpu/drm/kmb/kmb_regs.h
400
#define HS_OFFSET(M) (((M) + 1) * 0x400)
drivers/gpu/drm/kmb/kmb_regs.h
403
#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M))
drivers/gpu/drm/kmb/kmb_regs.h
417
#define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \
drivers/gpu/drm/kmb/kmb_regs.h
418
+ HS_OFFSET(M))
drivers/gpu/drm/kmb/kmb_regs.h
435
#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \
drivers/gpu/drm/kmb/kmb_regs.h
436
HS_OFFSET(M) + (0x2C * (N)) \
drivers/gpu/drm/kmb/kmb_regs.h
448
#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
450
+ HS_OFFSET(M) + (0x2C * (N)))
drivers/gpu/drm/kmb/kmb_regs.h
452
#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \
drivers/gpu/drm/kmb/kmb_regs.h
453
(MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
457
#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
458
(MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
461
#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
462
(MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
465
#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
466
(MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
469
#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
470
(MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
473
#define MIPI_TXm_HS_V_ACTIVEn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
474
(MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
477
#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
478
(MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
481
#define MIPI_TXm_HS_H_BACKPORCHn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
482
(MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
485
#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
486
(MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
489
#define MIPI_TXm_HS_H_ACTIVEn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
490
(MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
493
#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
494
(MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
497
#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
498
(MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
501
#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
502
(MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
506
#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \
drivers/gpu/drm/kmb/kmb_regs.h
507
(MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M))
drivers/gpu/drm/kmb/kmb_regs.h
511
#define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
512
(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
520
#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
521
(MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \
drivers/gpu/drm/kmb/kmb_regs.h
545
#define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) kmb_set_bit_mipi(dev, \
drivers/gpu/drm/kmb/kmb_regs.h
547
(M) + (N))
drivers/gpu/drm/kmb/kmb_regs.h
554
#define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
555
kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR0, (M) + (N))
drivers/gpu/drm/kmb/kmb_regs.h
557
#define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
558
kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, (M) + (N))
drivers/gpu/drm/kmb/kmb_regs.h
561
#define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \
drivers/gpu/drm/kmb/kmb_regs.h
562
HS_OFFSET(M))
drivers/gpu/drm/kmb/kmb_regs.h
563
#define GET_MIPI_TX_HS_IRQ_STATUS(dev, M) kmb_read_mipi(dev, \
drivers/gpu/drm/kmb/kmb_regs.h
564
MIPI_TX_HS_IRQ_STATUSm(M))
drivers/gpu/drm/kmb/kmb_regs.h
618
#define GET_HS_IRQ_ENABLE(dev, M) kmb_read_mipi(dev, \
drivers/gpu/drm/kmb/kmb_regs.h
620
+ HS_OFFSET(M))
drivers/gpu/drm/kmb/kmb_regs.h
625
#define MIPI_TXm_HS_TEST_PAT_CTRL(M) \
drivers/gpu/drm/kmb/kmb_regs.h
626
(MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M))
drivers/gpu/drm/kmb/kmb_regs.h
627
#define TP_EN_VCm(M) (1 << ((M) * 0x04))
drivers/gpu/drm/kmb/kmb_regs.h
628
#define TP_SEL_VCm(M, N) \
drivers/gpu/drm/kmb/kmb_regs.h
629
((N) << (((M) * 0x04) + 1))
drivers/gpu/drm/kmb/kmb_regs.h
630
#define TP_STRIPE_WIDTH(M) ((M) << 16)
drivers/gpu/drm/kmb/kmb_regs.h
632
#define MIPI_TXm_HS_TEST_PAT_COLOR0(M) \
drivers/gpu/drm/kmb/kmb_regs.h
633
(MIPI_TX_HS_TEST_PAT_COLOR0 + HS_OFFSET(M))
drivers/gpu/drm/kmb/kmb_regs.h
635
#define MIPI_TXm_HS_TEST_PAT_COLOR1(M) \
drivers/gpu/drm/kmb/kmb_regs.h
636
(MIPI_TX_HS_TEST_PAT_COLOR1 + HS_OFFSET(M))
drivers/gpu/drm/nouveau/include/nvif/push.h
262
#define PUSH_(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X,IMPL,...) IMPL
drivers/gpu/drm/nouveau/include/nvif/push.h
353
#define PUSH_NV_(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X,IMPL,...) IMPL
drivers/gpu/drm/nouveau/nouveau_bios.c
1033
parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
255
int N, M, P, ret;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
265
ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
269
*coef = (P << 16) | (N << 8) | M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
66
u32 M = (coef & 0x000000ff) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
94
return sclk * N / M / P;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
102
return sclk / (M * P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
268
int N, M, P, ret;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
278
ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
282
*coef = (P << 16) | (N << 8) | M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
67
u32 M = (coef & 0x000000ff) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
112
u32 sclk = 0, P = 1, N = 1, M = 1;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
118
M = (coef & 0x000000ff) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
134
MP = M * P;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
241
int P, N, M, diff;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
263
ret = gt215_pll_calc(subdev, &limits, khz, &N, NULL, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
265
info->pll = (P << 16) | (N << 8) | M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
163
u32 clock, int *N, int *M, int *P)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
178
return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
208
int N, M, P1, P2 = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
216
clock = calc_pll(clk, 0x4028, (core << 1), &N, &M, &P1);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
231
clk->ccoef = (N << 8) | M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
242
clock = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
253
clk->scoef = (N << 8) | M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
46
int M = (ctrl & 0x000000ff) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
50
khz = ref * N / M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
112
M = (coef & 0x000000ff) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
118
if (M)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
119
return (ref * N / M) >> P;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
326
calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
341
return nv04_pll_calc(subdev, &pll, idx, N, M, NULL, NULL, P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
381
int N, M, P1, P2;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
460
freq = calc_pll(clk, 0x4028, core, &N, &M, &P1);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
466
clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
478
freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
484
clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
58
int P, N, M, id;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
77
M = ((coef & 0x000000ff) >> 0) + 1;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
85
M = (coef & 0x000000ff) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
11
int *N, int *fN, int *M, int *P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
34
int M, lM, hM, N, fN;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
48
for (M = lM; M <= hM; M++) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
49
u32 tmp = freq * *P * M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
67
err = abs(freq - (info->refclk * N / M / *P));
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
71
*pM = M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
107
calcclk = ((N * crystal + P/2) / P + M/2) / M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
116
*pM = M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
49
int M, N, thisP, P;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
92
for (M = minM; M <= maxM; M++) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
93
if (crystal/M < minU)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
95
if (crystal/M > maxU)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
99
N = (clkP * M + crystal/2) / crystal;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
36
int N, fN, M, P;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
43
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
54
nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | M);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
37
int N, fN, M, P;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
44
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
54
nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
37
int N, fN, M, P;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
44
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
53
(P << 16) | (M << 8) | N);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c
35
int N, fN, M, P;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c
42
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c
54
(M << 0));
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
36
int N, fN, M, P;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
43
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
55
(M << 0));
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
982
gk104_calc_pll_output(int fN, int M, int N, int P, int clk)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
984
return ((clk * N) + (((u16)(fN + 4096) * clk) >> 13)) / (M * P);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
155
if (!bit_entry(bios, 'M', &M))
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
156
nvbios_init(subdev, nvbios_rd16(bios, M.offset + 0x00));
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
73
struct bit_entry M;
drivers/iio/adc/at91-sama5d2_adc.c
151
#define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M))
drivers/iommu/msm_iommu_hw-8xxx.h
567
#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
drivers/iommu/msm_iommu_hw-8xxx.h
755
#define GET_M(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, M)
drivers/media/dvb-frontends/mb86a16.c
457
int M;
drivers/media/dvb-frontends/mb86a16.c
500
M = f * (1 << R) / 2;
drivers/media/dvb-frontends/mb86a16.c
503
rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
drivers/media/dvb-frontends/mb86a16.c
504
rf_val[2] = (M & 0x00ff0) >> 4;
drivers/media/dvb-frontends/mb86a16.c
505
rf_val[3] = ((M & 0x0000f) << 4) | B;
drivers/media/dvb-frontends/mb86a16.c
640
int R, M, fOSC, fOSC_OFS;
drivers/media/dvb-frontends/mb86a16.c
692
M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
drivers/media/dvb-frontends/mb86a16.c
694
fOSC = 2 * M;
drivers/media/dvb-frontends/mb86a16.c
696
fOSC = M;
drivers/media/dvb-frontends/stv0367.c
1752
u32 M, N, P;
drivers/media/dvb-frontends/stv0367.c
1760
M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
drivers/media/dvb-frontends/stv0367.c
1761
if (M == 0)
drivers/media/dvb-frontends/stv0367.c
1762
M = M + 1;
drivers/media/dvb-frontends/stv0367.c
1769
mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
330
#define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N))
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
303
#define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N))
drivers/media/platform/qcom/camss/camss-vfe-gen1.c
707
#define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N))
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
143
M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
144
M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
145
M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
146
M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
147
M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
148
M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
149
M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
150
M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
151
M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
152
M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
154
M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
155
M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
156
M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
157
M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
158
M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
160
M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
161
M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
162
M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
163
M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
165
M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
167
M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
168
M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
169
M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
170
M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
171
M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
172
M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
173
M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
174
M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
175
M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
176
M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
178
M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
179
M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
180
M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
182
M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
184
M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
186
M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
187
M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
189
M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
190
M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
191
M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
193
M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
194
M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
196
M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
198
M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
201
M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
203
M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
204
M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
205
M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
206
M(NPA_CN20K_AQ_ENQ, 0x404, npa_cn20k_aq_enq, npa_cn20k_aq_enq_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
211
M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
213
M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
214
M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
216
M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
218
M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
219
M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
221
M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
222
M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
223
M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
226
M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
227
M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
229
M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
231
M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
233
M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
235
M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
237
M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
239
M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
241
M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
244
M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
246
M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
248
M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
250
M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
253
M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
260
M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
272
M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
275
M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
282
M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
283
M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
285
M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
287
M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
288
M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
290
M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
291
M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
293
M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
296
M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
297
M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
298
M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
299
M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
300
M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
304
M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
308
M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
309
M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
312
M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
313
M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
314
M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
316
M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
320
M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
321
M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
323
M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
331
M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
333
M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
335
M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
337
M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
340
M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
341
M(NIX_CN20K_AQ_ENQ, 0x802f, nix_cn20k_aq_enq, nix_cn20k_aq_enq_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
344
M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
346
M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
347
M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
349
M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
351
M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
353
M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
355
M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
357
M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
359
M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
361
M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
363
M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
365
M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
366
M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
368
M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
370
M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
371
M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
372
M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
374
M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
375
M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
376
M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
377
M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
379
M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
382
M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
384
M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
386
M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
387
M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
388
M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
390
M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
396
M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
399
M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
402
M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
405
M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
430
int G_fxp, Y_intercept, order_x_by_y, M, I, L, sum_y_sqr, sum_y_quad;
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
545
M = 10;
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
547
M = 9;
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
549
M = 8;
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
572
(x_est_fxp1_nonlin * (1 << M) + y_est[i + I]) / y_est[i +
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
575
(x_tilde[i] * (1 << M) + y_est[i + I]) / y_est[i + I];
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
577
(x_tilde[i] * (1 << M) + y_est[i + I]) / y_est[i + I];
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
638
order_1 = 3 * M - Q_x - Q_B1 - Q_beta + 10 + Q_scale_B;
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
639
order_2 = 3 * M - Q_x - Q_B2 - Q_alpha + 10 + Q_scale_B;
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
675
((theta[i + I] << M) + y_est[i + I]) / y_est[i + I];
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
677
((theta_tilde << M) + y_est[i + I]) / y_est[i + I];
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
679
((theta_tilde << M) + y_est[i + I]) / y_est[i + I];
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
691
order_1 = 3 * M - Q_x - Q_B1 - Q_beta + 10 + Q_scale_B + 5;
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
692
order_2 = 3 * M - Q_x - Q_B2 - Q_alpha + 10 + Q_scale_B + 5;
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
102
val |= M(0x2);
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
104
val |= M(0x1);
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
106
val |= M(0x0);
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
111
val |= M(0x2);
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
113
val |= M(0x1);
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
115
val |= M(0x0);
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
36
#define CTRL_RESET_VAL (M(0x0) | CCM(0x4) | CA(0x4) | TST(0x25))
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
40
#define CTRL_INIT_VAL (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB)
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1071
M_MASK, M(samsung->pll.fbdiv));
drivers/pinctrl/pinctrl-rockchip.c
307
#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
drivers/pinctrl/pinctrl-rockchip.c
308
PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
80
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
84
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
88
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
93
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
97
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
66
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
70
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
74
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
79
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
83
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
87
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
91
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
95
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
100
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
105
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
110
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
115
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
120
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
125
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
130
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
72
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
76
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
80
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
84
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
88
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
95
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
drivers/rtc/rtc-atcrtc100.c
61
#define ATCRTC_TIME_TO_SEC(D, H, M, S) \
drivers/rtc/rtc-atcrtc100.c
62
((time64_t)(D) * 86400 + (H) * 3600 + (M) * 60 + (S))
drivers/scsi/ncr53c8xx.h
1230
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
drivers/scsi/sym53c8xx_2/sym_defs.h
713
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
drivers/staging/rtl8723bs/core/rtw_security.c
138
pmicdata->M = 0;
drivers/staging/rtl8723bs/core/rtw_security.c
153
pmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM);
drivers/staging/rtl8723bs/core/rtw_security.c
157
pmicdata->L ^= pmicdata->M;
drivers/staging/rtl8723bs/core/rtw_security.c
167
pmicdata->M = 0;
drivers/staging/rtl8723bs/include/rtw_security.h
236
u32 M; /* Message accumulator (single word) */
drivers/staging/sm750fb/ddk750_chip.c
319
int N, M, X, d;
drivers/staging/sm750fb/ddk750_chip.c
360
M = quo * X;
drivers/staging/sm750fb/ddk750_chip.c
361
M += fl_quo * X / 10000;
drivers/staging/sm750fb/ddk750_chip.c
363
M += (fl_quo * X % 10000) > 5000 ? 1 : 0;
drivers/staging/sm750fb/ddk750_chip.c
364
if (M < 256 && M > 0) {
drivers/staging/sm750fb/ddk750_chip.c
367
tmp_clock = pll->input_freq * M / N / X;
drivers/staging/sm750fb/ddk750_chip.c
37
unsigned int M, N, OD, POD;
drivers/staging/sm750fb/ddk750_chip.c
370
pll->M = M;
drivers/staging/sm750fb/ddk750_chip.c
391
unsigned int M = p_PLL->M;
drivers/staging/sm750fb/ddk750_chip.c
406
((M << PLL_CTRL_M_SHIFT) & PLL_CTRL_M_MASK);
drivers/staging/sm750fb/ddk750_chip.c
43
M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
drivers/staging/sm750fb/ddk750_chip.c
48
return DEFAULT_INPUT_CLOCK * M / N / BIT(OD) / BIT(POD);
drivers/staging/sm750fb/ddk750_chip.h
47
unsigned long M;
drivers/video/fbdev/aty/aty128fb.c
952
u32 Nx, M;
drivers/video/fbdev/aty/aty128fb.c
963
M = x_mpll_ref_fb_div & 0x0000ff;
drivers/video/fbdev/aty/aty128fb.c
966
(M * PostDivSet[xclk_cntl]));
drivers/video/fbdev/aty/atyfb_base.c
3076
unsigned int N, P, Q, M, T, R;
drivers/video/fbdev/aty/atyfb_base.c
3103
M = pll_regs[PLL_REF_DIV];
drivers/video/fbdev/aty/atyfb_base.c
3135
T = 2 * Q * R / M;
drivers/video/fbdev/aty/radeon_base.c
578
unsigned Ns, Nm, M;
drivers/video/fbdev/aty/radeon_base.c
693
M = (tmp & 0xff);
drivers/video/fbdev/aty/radeon_base.c
694
sclk = round_div((2 * Ns * xtal), (2 * M));
drivers/video/fbdev/aty/radeon_base.c
695
mclk = round_div((2 * Nm * xtal), (2 * M));
drivers/video/fbdev/gbefb.c
538
SET_GBE_FIELD(DOTCLK, M, val, timing->pll_m - 1);
drivers/video/fbdev/i810/i810.h
212
u32 pixclock, M, N, P;
drivers/video/fbdev/i810/i810_main.c
1179
i810_calc_dclk(var->pixclock, &par->regs.M,
drivers/video/fbdev/i810/i810_main.c
236
tmp1 = par->regs.M | par->regs.N << 16;
drivers/video/fbdev/nvidia/nv_hw.c
144
unsigned int pll, N, M, MB, NB, P;
drivers/video/fbdev/nvidia/nv_hw.c
150
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
160
*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
165
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
170
*NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
173
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
184
*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
187
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
198
*NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
203
M = pll & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
213
*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
216
M = pll & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
226
*NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
229
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
232
*MClk = (N * par->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
235
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
238
*NVClk = (N * par->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
684
unsigned int M, N, P, pll, MClk, NVClk, memctrl;
drivers/video/fbdev/nvidia/nv_hw.c
704
M = (pll >> 0) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
707
NVClk = (N * par->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
772
unsigned M, N, P;
drivers/video/fbdev/nvidia/nv_hw.c
789
for (M = lowM; M <= highM; M++) {
drivers/video/fbdev/nvidia/nv_hw.c
790
N = ((VClk << P) * M) / par->CrystalFreqKHz;
drivers/video/fbdev/nvidia/nv_hw.c
794
M) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
801
(P << 16) | (N << 8) | M;
drivers/video/fbdev/nvidia/nv_hw.c
818
unsigned M, N, P;
drivers/video/fbdev/nvidia/nv_hw.c
829
for (M = 1; M <= 13; M++) {
drivers/video/fbdev/nvidia/nv_hw.c
830
N = ((VClk << P) * M) /
drivers/video/fbdev/nvidia/nv_hw.c
835
M) >> P;
drivers/video/fbdev/nvidia/nv_hw.c
842
(P << 16) | (N << 8) | M;
drivers/video/fbdev/riva/riva_hw.c
1054
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
drivers/video/fbdev/riva/riva_hw.c
1057
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
1058
MClk = (N * chip->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/riva/riva_hw.c
1060
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
1061
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/riva/riva_hw.c
1100
unsigned int M, N, P, pll, MClk, NVClk;
drivers/video/fbdev/riva/riva_hw.c
1114
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
1115
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/riva/riva_hw.c
1166
unsigned M, N, P;
drivers/video/fbdev/riva/riva_hw.c
1189
for (M = lowM; M <= highM; M++)
drivers/video/fbdev/riva/riva_hw.c
1191
N = (VClk << P) * M / chip->CrystalFreqKHz;
drivers/video/fbdev/riva/riva_hw.c
1193
Freq = (chip->CrystalFreqKHz * N / M) >> P;
drivers/video/fbdev/riva/riva_hw.c
1200
*mOut = M;
drivers/video/fbdev/riva/riva_hw.c
621
unsigned int M, N, P, pll, MClk;
drivers/video/fbdev/riva/riva_hw.c
624
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
625
MClk = (N * chip->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/riva/riva_hw.c
805
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
drivers/video/fbdev/riva/riva_hw.c
808
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
809
MClk = (N * chip->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/riva/riva_hw.c
811
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
812
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
drivers/video/fbdev/stifb.c
388
#define IBOvals(R,M,X,S,D,L,B,F) \
drivers/video/fbdev/stifb.c
389
(((R)<<8)|((M)<<16)|((X)<<24)|((S)<<29)|((D)<<28)|((L)<<31)|((B)<<1)|(F))
include/linux/poll.h
124
return M(IN) | M(OUT) | M(PRI) | M(ERR) | M(NVAL) |
include/linux/poll.h
125
M(RDNORM) | M(RDBAND) | M(WRNORM) | M(WRBAND) |
include/linux/poll.h
126
M(HUP) | M(RDHUP) | M(MSG);
include/linux/poll.h
133
return M(IN) | M(OUT) | M(PRI) | M(ERR) | M(NVAL) |
include/linux/poll.h
134
M(RDNORM) | M(RDBAND) | M(WRNORM) | M(WRBAND) |
include/linux/poll.h
135
M(HUP) | M(RDHUP) | M(MSG);
kernel/sched/debug.c
1221
#define PM(F, M) __PS(#F, p->F & (M))
security/security.c
101
UNROLL(MAX_LSM_COUNT, M, __VA_ARGS__) \
security/security.c
104
#define LSM_DEFINE_UNROLL(M, ...) UNROLL(MAX_LSM_COUNT, M, __VA_ARGS__)
security/security.c
99
#define LSM_LOOP_UNROLL(M, ...) \
sound/pci/riptide/riptide.c
1027
u32 D, M, N;
sound/pci/riptide/riptide.c
1034
M = ((rate == 48000) ? 47999 : rate) * 65536;
sound/pci/riptide/riptide.c
1035
N = M % D;
sound/pci/riptide/riptide.c
1036
M /= D;
sound/pci/riptide/riptide.c
1040
SEND_SSRC(cif, *intdec, D, M, N);
sound/pci/riptide/riptide.c
1043
rptr.retwords[2] != M &&
tools/bpf/bpf_dbg.c
125
uint32_t M[BPF_MEMWORDS];
tools/bpf/bpf_dbg.c
461
if (r->M[i]) {
tools/bpf/bpf_dbg.c
463
rl_printf("M[%d]: [%#08x][%u]\n", i, r->M[i], r->M[i]);
tools/bpf/bpf_dbg.c
659
r->M[K] = r->A;
tools/bpf/bpf_dbg.c
662
r->M[K] = r->X;
tools/bpf/bpf_dbg.c
725
r->A = r->M[K];
tools/bpf/bpf_dbg.c
728
r->X = r->M[K];
tools/perf/tests/kmod-path.c
104
M("[test_module]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
tools/perf/tests/kmod-path.c
105
M("[test_module]", PERF_RECORD_MISC_KERNEL, true);
tools/perf/tests/kmod-path.c
106
M("[test_module]", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
113
M("[test.module]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
tools/perf/tests/kmod-path.c
114
M("[test.module]", PERF_RECORD_MISC_KERNEL, true);
tools/perf/tests/kmod-path.c
115
M("[test.module]", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
122
M("[vdso]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
tools/perf/tests/kmod-path.c
123
M("[vdso]", PERF_RECORD_MISC_KERNEL, false);
tools/perf/tests/kmod-path.c
124
M("[vdso]", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
130
M("[vdso32]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
tools/perf/tests/kmod-path.c
131
M("[vdso32]", PERF_RECORD_MISC_KERNEL, false);
tools/perf/tests/kmod-path.c
132
M("[vdso32]", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
138
M("[vdsox32]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
tools/perf/tests/kmod-path.c
139
M("[vdsox32]", PERF_RECORD_MISC_KERNEL, false);
tools/perf/tests/kmod-path.c
140
M("[vdsox32]", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
147
M("[vsyscall]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
tools/perf/tests/kmod-path.c
148
M("[vsyscall]", PERF_RECORD_MISC_KERNEL, false);
tools/perf/tests/kmod-path.c
149
M("[vsyscall]", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
156
M("[kernel.kallsyms]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
tools/perf/tests/kmod-path.c
157
M("[kernel.kallsyms]", PERF_RECORD_MISC_KERNEL, false);
tools/perf/tests/kmod-path.c
158
M("[kernel.kallsyms]", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
57
M("/xxxx/xxxx/x-x.ko", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
tools/perf/tests/kmod-path.c
58
M("/xxxx/xxxx/x-x.ko", PERF_RECORD_MISC_KERNEL, true);
tools/perf/tests/kmod-path.c
59
M("/xxxx/xxxx/x-x.ko", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
67
M("/xxxx/xxxx/x.ko.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
tools/perf/tests/kmod-path.c
68
M("/xxxx/xxxx/x.ko.gz", PERF_RECORD_MISC_KERNEL, true);
tools/perf/tests/kmod-path.c
69
M("/xxxx/xxxx/x.ko.gz", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
76
M("/xxxx/xxxx/x.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
tools/perf/tests/kmod-path.c
77
M("/xxxx/xxxx/x.gz", PERF_RECORD_MISC_KERNEL, false);
tools/perf/tests/kmod-path.c
78
M("/xxxx/xxxx/x.gz", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
85
M("x.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
tools/perf/tests/kmod-path.c
86
M("x.gz", PERF_RECORD_MISC_KERNEL, false);
tools/perf/tests/kmod-path.c
87
M("x.gz", PERF_RECORD_MISC_USER, false);
tools/perf/tests/kmod-path.c
94
M("x.ko.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
tools/perf/tests/kmod-path.c
95
M("x.ko.gz", PERF_RECORD_MISC_KERNEL, true);
tools/perf/tests/kmod-path.c
96
M("x.ko.gz", PERF_RECORD_MISC_USER, false);
tools/testing/selftests/bpf/io_helpers.c
8
const long M = 1000 * 1000;
tools/testing/selftests/bpf/io_helpers.c
9
struct timeval tv = { usec / M, usec % M };
tools/testing/selftests/kvm/riscv/get-reg-list.c
514
KVM_ISA_EXT_ARR(M),