Symbol: IRQ_MSK
arch/arm/mach-imx/avic.c
133
gc->wake_enabled = IRQ_MSK(32);
arch/arm/mach-imx/avic.c
145
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
arch/arm/mach-imx/tzic.c
108
gc->wake_enabled = IRQ_MSK(32);
arch/arm/mach-imx/tzic.c
119
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
arch/arm/mach-omap1/irq.c
179
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
arch/arm/plat-orion/gpio.c
601
irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
arch/arm/plat-orion/irq.c
37
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
arch/sh/boards/mach-se/7343/irq.c
87
irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
arch/sh/boards/mach-se/7722/irq.c
85
irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
drivers/gpio/gpio-ml-ioh.c
396
rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
drivers/gpio/gpio-mxc.c
367
rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
drivers/gpio/gpio-mxs.c
225
rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
drivers/gpio/gpio-pch.c
345
rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
drivers/gpio/gpio-rockchip.c
559
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
drivers/gpio/gpio-sodaville.c
169
irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
drivers/irqchip/irq-goldfish-pic.c
101
irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
drivers/irqchip/irq-goldfish-pic.c
120
irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
drivers/irqchip/irq-ingenic-tcu.c
132
gc->wake_enabled = IRQ_MSK(32);
drivers/irqchip/irq-ingenic-tcu.c
144
regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32));
drivers/irqchip/irq-ingenic.c
111
gc->wake_enabled = IRQ_MSK(32);
drivers/irqchip/irq-ingenic.c
124
irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
drivers/irqchip/irq-omap-intc.c
239
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
drivers/irqchip/irq-stm32-exti.c
372
gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);