IRQ_MSK
gc->wake_enabled = IRQ_MSK(32);
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
gc->wake_enabled = IRQ_MSK(32);
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
gc->wake_enabled = IRQ_MSK(32);
regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32));
gc->wake_enabled = IRQ_MSK(32);
irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);