I915_MAX_PIPES
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
int min_cdclk[I915_MAX_PIPES];
u8 min_voltage_level[I915_MAX_PIPES];
struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
entries, I915_MAX_PIPES, pipe))
entries, I915_MAX_PIPES, pipe));
struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
(i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
for (int (i) = (I915_MAX_PIPES * 2 - 1); \
(i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
u32 de_pipe_imr_mask[I915_MAX_PIPES];
u32 pipestat_irq_mask[I915_MAX_PIPES];
u16 linetime[I915_MAX_PIPES];
bool disable[I915_MAX_PIPES];
u32 chv_dpll_md[I915_MAX_PIPES];
BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
u8 num_sprites[I915_MAX_PIPES];
u8 num_scalers[I915_MAX_PIPES];
u32 cursor_offsets[I915_MAX_PIPES];
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
const u32 pipe_stats[I915_MAX_PIPES])
u32 pipe_stats[I915_MAX_PIPES];
__array(u32, frame, I915_MAX_PIPES)
__array(u32, scanline, I915_MAX_PIPES)
sizeof(__entry->frame[0]) * I915_MAX_PIPES);
sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
__array(u32, frame, I915_MAX_PIPES)
__array(u32, scanline, I915_MAX_PIPES)
sizeof(__entry->frame[0]) * I915_MAX_PIPES);
sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
static_assert(I915_MAX_PIPES - 1 == _TRACE_PIPE_D);
__array(u32, frame, I915_MAX_PIPES)
__array(u32, scanline, I915_MAX_PIPES)
sizeof(__entry->frame[0]) * I915_MAX_PIPES);
sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
struct intel_dp_mst_encoder *stream_encoders[I915_MAX_PIPES];
for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
struct drm_dp_tunnel_ref ref[I915_MAX_PIPES];
drm_WARN_ON(display->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1));
u32 dpll[I915_MAX_PIPES];
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32);
if (pipe < PIPE_A || pipe >= I915_MAX_PIPES)
struct intel_initial_plane_config config[I915_MAX_PIPES];
int max_bpp_x16[I915_MAX_PIPES];
int ddi_clocks[I915_MAX_PIPES];
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
I915_MAX_PIPES, crtc->pipe))
struct skl_ddb_entry ddb[I915_MAX_PIPES];
unsigned int weight[I915_MAX_PIPES];
u8 slices[I915_MAX_PIPES];
u8 dbuf_mask[I915_MAX_PIPES];
pipe < PIPE_A || pipe >= I915_MAX_PIPES))
for ((__p) = PIPE_A; (__p) < I915_MAX_PIPES; (__p)++) \
for (i = 0; i < I915_MAX_PIPES; i++)
if (pipe >= I915_MAX_PIPES)
if (pipe >= I915_MAX_PIPES)
DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],