FIELD_PREP_CONST

drivers/accel/amdxdna/amdxdna_error.h

47

FIELD_PREP_CONST(AMDXDNA_ERR_DRV_MASK, AMDXDNA_ERR_DRV_AIE) | \

drivers/accel/amdxdna/amdxdna_error.h

48

FIELD_PREP_CONST(AMDXDNA_ERR_SEV_MASK, AMDXDNA_ERR_SEV_CRITICAL) | \

drivers/accel/amdxdna/amdxdna_error.h

50

FIELD_PREP_CONST(AMDXDNA_ERR_CLASS_MASK, AMDXDNA_ERR_CLASS_AIE))

drivers/clk/renesas/r9a09g077-cpg.c

38

(FIELD_PREP_CONST(OFFSET_MASK, (offset)) | \

drivers/clk/renesas/r9a09g077-cpg.c

39

FIELD_PREP_CONST(SHIFT_MASK, (shift)) | \

drivers/clk/renesas/r9a09g077-cpg.c

40

FIELD_PREP_CONST(WIDTH_MASK, (width)))

drivers/clk/renesas/rzv2h-cpg.h

161

#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \

drivers/clk/renesas/rzv2h-cpg.h

162

FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))

drivers/cpufreq/intel_pstate.c

3704

(FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\

drivers/cpufreq/intel_pstate.c

3705

FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\

drivers/cpufreq/intel_pstate.c

3706

FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\

drivers/cpufreq/intel_pstate.c

3707

FIELD_PREP_CONST(PERFORMANCE_MASK, performance))

drivers/dpll/zl3073x/core.h

119

.value = FIELD_PREP_CONST(_mask, _value), \

drivers/dpll/zl3073x/regs.h

50

FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page) | \

drivers/dpll/zl3073x/regs.h

51

FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size) | \

drivers/dpll/zl3073x/regs.h

52

FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK, \

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

58

val = FIELD_PREP_CONST(P_SEL,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

60

val |= FIELD_PREP_CONST(C_SEL,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

62

val |= FIELD_PREP_CONST(U_SEL,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

64

val |= FIELD_PREP_CONST(V_SEL,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

66

val |= FIELD_PREP_CONST(D_SEL,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

68

val |= FIELD_PREP_CONST(PRE_SEL,

drivers/gpu/drm/imx/dc/dc-fu.h

24

#define R_BITS(x) FIELD_PREP_CONST(GENMASK(27, 24), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

25

#define G_BITS(x) FIELD_PREP_CONST(GENMASK(19, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

26

#define B_BITS(x) FIELD_PREP_CONST(GENMASK(11, 8), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

27

#define A_BITS(x) FIELD_PREP_CONST(GENMASK(3, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

30

#define R_SHIFT(x) FIELD_PREP_CONST(GENMASK(28, 24), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

31

#define G_SHIFT(x) FIELD_PREP_CONST(GENMASK(20, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

32

#define B_SHIFT(x) FIELD_PREP_CONST(GENMASK(12, 8), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

33

#define A_SHIFT(x) FIELD_PREP_CONST(GENMASK(4, 0), (x))

drivers/gpu/drm/panel/panel-himax-hx8279.c

1215

.volt_adj = FIELD_PREP_CONST(HX8279_P6_VOLT_ADJ_VCCIFS, 3) |

drivers/gpu/drm/panel/panel-himax-hx8279.c

1216

FIELD_PREP_CONST(HX8279_P6_VOLT_ADJ_VCCS, 3),

drivers/gpu/drm/panel/panel-himax-hx8279.c

1272

.gamma_ctl = FIELD_PREP_CONST(HX8279_P6_GAMMA_POCGM_CTL, 1) |

drivers/gpu/drm/panel/panel-himax-hx8279.c

1273

FIELD_PREP_CONST(HX8279_P6_GAMMA_POGCMD_CTL, 1),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

100

FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_EVENT) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

101

FIELD_PREP_CONST(GUC_HXG_EVENT_MSG_0_ACTION, XE_GUC_ACTION_GUC2PF_RELAY_FROM_VF),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

102

FIELD_PREP_CONST(GUC2PF_RELAY_FROM_VF_EVENT_MSG_1_VFID, TEST_VFID),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

103

FIELD_PREP_CONST(GUC2PF_RELAY_FROM_VF_EVENT_MSG_2_RELAY_ID, TEST_RID),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

105

FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

106

FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_SUCCESS),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

111

FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

112

FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_EVENT) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

113

FIELD_PREP_CONST(GUC_HXG_EVENT_MSG_0_ACTION, XE_GUC_ACTION_GUC2VF_RELAY_FROM_PF),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

114

FIELD_PREP_CONST(GUC2VF_RELAY_FROM_PF_EVENT_MSG_1_RELAY_ID, TEST_RID),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

116

FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

117

FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_SUCCESS),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

159

FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

160

FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_SUCCESS),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

54

FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

55

FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_EVENT) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

56

FIELD_PREP_CONST(GUC_HXG_EVENT_MSG_0_ACTION, TEST_ACTION) |

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

57

FIELD_PREP_CONST(GUC_HXG_EVENT_MSG_0_DATA0, TEST_DATA(0)),

drivers/gpu/drm/xe/tests/xe_guc_relay_test.c

99

FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC) |

drivers/gpu/drm/xe/xe_guc_klv_helpers.h

38

(FIELD_PREP_CONST(GUC_KLV_0_KEY, (key)) | \

drivers/gpu/drm/xe/xe_guc_klv_helpers.h

39

FIELD_PREP_CONST(GUC_KLV_0_LEN, (len)))

drivers/gpu/drm/xe/xe_guc_log.c

270

lfd->header = FIELD_PREP_CONST(GUC_LFD_DATA_HEADER_MASK_MAGIC, GUC_LFD_DATA_HEADER_MAGIC);

drivers/gpu/drm/xe/xe_guc_log.c

556

header.version = FIELD_PREP_CONST(GUC_LFD_FILE_HEADER_VERSION_MASK_MINOR,

drivers/gpu/drm/xe/xe_guc_log.c

558

FIELD_PREP_CONST(GUC_LFD_FILE_HEADER_VERSION_MASK_MAJOR,

drivers/gpu/drm/xe/xe_guc_log.c

79

(FIELD_PREP_CONST(GUC_LIC_VERSION_MASK_MAJOR, GUC_LIC_VERSION_MAJOR) |

drivers/gpu/drm/xe/xe_guc_log.c

80

FIELD_PREP_CONST(GUC_LIC_VERSION_MASK_MINOR, GUC_LIC_VERSION_MINOR))

drivers/leds/leds-lp55xx-common.c

43

#define LP55xx_MODE_DISABLE_ENG FIELD_PREP_CONST(LP55xx_MODE_ENG_MASK, 0x0)

drivers/leds/leds-lp55xx-common.c

44

#define LP55xx_MODE_LOAD_ENG FIELD_PREP_CONST(LP55xx_MODE_ENG_MASK, 0x1)

drivers/leds/leds-lp55xx-common.c

45

#define LP55xx_MODE_RUN_ENG FIELD_PREP_CONST(LP55xx_MODE_ENG_MASK, 0x2)

drivers/leds/leds-lp55xx-common.c

46

#define LP55xx_MODE_HALT_ENG FIELD_PREP_CONST(LP55xx_MODE_ENG_MASK, 0x3)

drivers/leds/leds-lp55xx-common.c

54

#define LP55xx_EXEC_HOLD_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x0)

drivers/leds/leds-lp55xx-common.c

55

#define LP55xx_EXEC_STEP_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x1)

drivers/leds/leds-lp55xx-common.c

56

#define LP55xx_EXEC_RUN_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x2)

drivers/leds/leds-lp55xx-common.c

57

#define LP55xx_EXEC_ONCE_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x3)

drivers/leds/leds-sun50i-a100.c

162

FIELD_PREP_CONST(LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL, LEDC_FIFO_DEPTH / 2);