DMA_IN_PROGRESS
desc->status = DMA_IN_PROGRESS;
chan->status = DMA_IN_PROGRESS;
if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS)
desc->status = DMA_IN_PROGRESS;
ret = DMA_IN_PROGRESS;
ret = DMA_IN_PROGRESS;
if (dch->status == DMA_IN_PROGRESS) {
dch->status = DMA_IN_PROGRESS;
if (status == DMA_IN_PROGRESS || status == DMA_PAUSED)
} else if (status == DMA_IN_PROGRESS) {
dch->status = DMA_IN_PROGRESS;
if (status != DMA_IN_PROGRESS)
if (ret == DMA_IN_PROGRESS && chan->status == EDMA_ST_PAUSE)
return DMA_IN_PROGRESS;
return DMA_IN_PROGRESS;
fsl_chan->status = DMA_IN_PROGRESS;
fsl_chan->status = DMA_IN_PROGRESS;
if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) {
fsl_chan->status = DMA_IN_PROGRESS;
desc->status = DMA_IN_PROGRESS;
if (hsuc->desc && hsuc->desc->status == DMA_IN_PROGRESS) {
hsuc->desc->status = DMA_IN_PROGRESS;
desc->status = DMA_IN_PROGRESS;
if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
idma64c->desc->status = DMA_IN_PROGRESS;
sdmac->status = DMA_IN_PROGRESS;
if (c->status == DMA_IN_PROGRESS) {
c->status = DMA_IN_PROGRESS;
c->status = DMA_IN_PROGRESS;
desc->status = DMA_IN_PROGRESS;
desc->status = DMA_IN_PROGRESS;
if (lchan->desc && lchan->desc->status == DMA_IN_PROGRESS) {
lchan->desc->status = DMA_IN_PROGRESS;
tdmac->status = DMA_IN_PROGRESS;
tdmac->status = DMA_IN_PROGRESS;
tdmac->status = DMA_IN_PROGRESS;
mxs_chan->status = DMA_IN_PROGRESS;
mxs_chan->status = DMA_IN_PROGRESS;
if (mxs_chan->status == DMA_IN_PROGRESS)
mxs_chan->status = DMA_IN_PROGRESS;
if (mxs_chan->status == DMA_IN_PROGRESS)
mxs_chan->status = DMA_IN_PROGRESS;
if (mxs_chan->status == DMA_IN_PROGRESS &&
} else if (status == DMA_IN_PROGRESS) {
ret = DMA_IN_PROGRESS;
if (ret == DMA_IN_PROGRESS && bchan->paused)
if (mchan->paused && (ret == DMA_IN_PROGRESS)) {
ret = DMA_IN_PROGRESS;
if (c->status == DMA_IN_PROGRESS) {
c->status = DMA_IN_PROGRESS;
c->status = DMA_IN_PROGRESS;
chan->status = DMA_IN_PROGRESS;
status = DMA_IN_PROGRESS;
fchan->status = DMA_IN_PROGRESS;
chan->status = DMA_IN_PROGRESS;
if (chan->status != DMA_IN_PROGRESS)
chan->status = DMA_IN_PROGRESS;
chan->dma_status = DMA_IN_PROGRESS;
chan->dma_status = DMA_IN_PROGRESS;
tdc->status = DMA_IN_PROGRESS;
dma_desc->dma_status = DMA_IN_PROGRESS;
dma_desc->dma_status = DMA_IN_PROGRESS;
if (ret == DMA_IN_PROGRESS && udma_is_chan_paused(uc))
if (ret == DMA_IN_PROGRESS && c->paused) {
if (status != DMA_IN_PROGRESS)
if (status == DMA_IN_PROGRESS) {
if (status == DMA_IN_PROGRESS) {
case DMA_IN_PROGRESS:
if (req->status != DMA_IN_PROGRESS && req->status != DMA_PAUSED)
req->status = DMA_IN_PROGRESS;
desc->status = DMA_IN_PROGRESS;
if (dma_status == DMA_IN_PROGRESS)
if (ret == DMA_IN_PROGRESS) {
if (dma_status == DMA_IN_PROGRESS ||
if (status == DMA_IN_PROGRESS) {
if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
DMA_IN_PROGRESS, dmaengine_pause,
if (rx_dma_status == DMA_IN_PROGRESS ||
if (rx_dma_status == DMA_IN_PROGRESS)
DMA_IN_PROGRESS, dmaengine_pause,
return DMA_IN_PROGRESS;
if (status == DMA_IN_PROGRESS || status == DMA_PAUSED) {