writew_relaxed
#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
#define imx_writew writew_relaxed
writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
#define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); })
#define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); mb(); })
#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
writew_relaxed(val, vaddr);
writew_relaxed(cmd, &generic_comm_base->command);
writew_relaxed(0, &generic_comm_base->status);
writew_relaxed(val, ctx->regs + reg);
writew_relaxed(value & 0xffff, ddata->module_va + offset);
writew_relaxed(hi, ddata->module_va + offset + 4);
writew_relaxed(val, iomem + (xbar * 2));
writew_relaxed(val, addr);
writew_relaxed(val, addr);
writew_relaxed(val >> 16, addr + 2);
writew_relaxed(csdp, gdd + SSI_GDD_CSDP_REG(lch));
writew_relaxed(SSI_BLOCK_IE | SSI_TOUT_IE, gdd + SSI_GDD_CICR_REG(lch));
writew_relaxed(SSI_BYTES_TO_FRAMES(msg->sgt.sgl->length),
writew_relaxed(0, omap_ssi->gdd + SSI_GDD_CCR_REG(i));
writew_relaxed(0, omap_ssi->gdd + SSI_GDD_CCR_REG(i));
writew_relaxed(0, omap_ssi->gdd + SSI_GDD_CCR_REG(i));
writew_relaxed(*(u16 *)data, addr);
writew_relaxed(*(u16 *)payload, dest);
writew_relaxed(val, i2c_dev->base + reg);
writew_relaxed(val, omap->base +
writew_relaxed(cd->saved_polarity_conf[i], addr + i * 4);
writew_relaxed(val, cd->base + offset);
writew_relaxed(val, cd->base + offset);
writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,
writew_relaxed(tmp, priv->base + ICR1);
writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
writew_relaxed(chip_data->cpu_mask,
writew_relaxed((value), (dev)->regs + SDMMC_##reg)
writew_relaxed(val, host->ioaddr + reg);
writew_relaxed(val, host->ioaddr + reg);
writew_relaxed(*(u16 *)buf, io_addr_w);
writew_relaxed(*(u16 *)buf, io_addr_w);
writew_relaxed((u16)val, REG_ADDR(bp, offset))
#define writew_o writew_relaxed
#define writew_u writew_relaxed
writew_relaxed(value, pcie->cra_base + reg);
writew_relaxed(value, addr);
writew_relaxed(port->vendor_id, host->pcie + PCI_VENDOR_ID);
writew_relaxed(port->device_id, host->pcie + PCI_DEVICE_ID);
writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
writew_relaxed((value), (port)->regs + SPI_##reg)
writew_relaxed(val, dws->regs + offset);
writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
writew_relaxed(*((u16 *)val), addr);
writew_relaxed(*((u16 *)val), addr);
writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR);
writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR);
writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
writew_relaxed(val, addr);
writew_relaxed(status, ep->fifo);
#ifndef writew_relaxed
#define writew_relaxed writew_relaxed
writew_relaxed(value, addr);
writew_relaxed((u16)val, addr);
#ifndef writew_relaxed
#define writew_relaxed writew_relaxed