drivers/accel/ivpu/ivpu_trace.h

17

#define TRACE_SYSTEM vpu

drivers/media/platform/amphion/vpu.h

166

struct vpu_dev *vpu;

drivers/media/platform/amphion/vpu.h

232

struct vpu_dev *vpu;

drivers/media/platform/amphion/vpu.h

314

void vpu_writel(struct vpu_dev *vpu, u32 reg, u32 val);

drivers/media/platform/amphion/vpu.h

315

u32 vpu_readl(struct vpu_dev *vpu, u32 reg);

drivers/media/platform/amphion/vpu.h

342

int vpu_add_func(struct vpu_dev *vpu, struct vpu_func *func);

drivers/media/platform/amphion/vpu.h

347

struct vpu_core *vpu_request_core(struct vpu_dev *vpu, enum vpu_core_type type);

drivers/media/platform/amphion/vpu.h

38

int (*setup)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

39

int (*setup_encoder)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

40

int (*setup_decoder)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

41

int (*reset)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

73

void (*get_vpu)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

74

void (*put_vpu)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

75

void (*get_enc)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

76

void (*put_enc)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

77

void (*get_dec)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu.h

78

void (*put_dec)(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu_core.c

198

static struct vpu_core *vpu_core_find_proper_by_type(struct vpu_dev *vpu, u32 type)

drivers/media/platform/amphion/vpu_core.c

204

list_for_each_entry(c, &vpu->cores, list) {

drivers/media/platform/amphion/vpu_core.c

228

static bool vpu_core_is_exist(struct vpu_dev *vpu, struct vpu_core *core)

drivers/media/platform/amphion/vpu_core.c

232

list_for_each_entry(c, &vpu->cores, list) {

drivers/media/platform/amphion/vpu_core.c

242

core->vpu->get_vpu(core->vpu);

drivers/media/platform/amphion/vpu_core.c

244

core->vpu->get_enc(core->vpu);

drivers/media/platform/amphion/vpu_core.c

246

core->vpu->get_dec(core->vpu);

drivers/media/platform/amphion/vpu_core.c

251

struct vpu_dev *vpu = dev_get_drvdata(dev);

drivers/media/platform/amphion/vpu_core.c

256

if (vpu_core_is_exist(vpu, core))

drivers/media/platform/amphion/vpu_core.c

279

list_add_tail(&core->list, &vpu->cores);

drivers/media/platform/amphion/vpu_core.c

296

core->vpu->put_enc(core->vpu);

drivers/media/platform/amphion/vpu_core.c

298

core->vpu->put_dec(core->vpu);

drivers/media/platform/amphion/vpu_core.c

299

core->vpu->put_vpu(core->vpu);

drivers/media/platform/amphion/vpu_core.c

307

core->vpu = NULL;

drivers/media/platform/amphion/vpu_core.c

362

struct vpu_core *vpu_request_core(struct vpu_dev *vpu, enum vpu_core_type type)

drivers/media/platform/amphion/vpu_core.c

367

mutex_lock(&vpu->lock);

drivers/media/platform/amphion/vpu_core.c

369

core = vpu_core_find_proper_by_type(vpu, type);

drivers/media/platform/amphion/vpu_core.c

393

mutex_unlock(&vpu->lock);

drivers/media/platform/amphion/vpu_core.c

412

struct vpu_dev *vpu;

drivers/media/platform/amphion/vpu_core.c

416

vpu = inst->vpu;

drivers/media/platform/amphion/vpu_core.c

419

core = vpu_request_core(vpu, inst->type);

drivers/media/platform/amphion/vpu_core.c

421

dev_err(vpu->dev, "there is no vpu core for %s\n",

drivers/media/platform/amphion/vpu_core.c

517

struct vpu_dev *vpu;

drivers/media/platform/amphion/vpu_core.c

521

if (!inst || !inst->vpu)

drivers/media/platform/amphion/vpu_core.c

527

vpu = inst->vpu;

drivers/media/platform/amphion/vpu_core.c

528

mutex_lock(&vpu->lock);

drivers/media/platform/amphion/vpu_core.c

529

list_for_each_entry(core, &vpu->cores, list) {

drivers/media/platform/amphion/vpu_core.c

535

mutex_unlock(&vpu->lock);

drivers/media/platform/amphion/vpu_core.c

595

struct vpu_dev *vpu = dev_get_drvdata(dev->parent);

drivers/media/platform/amphion/vpu_core.c

601

if (!vpu)

drivers/media/platform/amphion/vpu_core.c

610

core->vpu = vpu;

drivers/media/platform/amphion/vpu_core.c

663

vpu_iface_config_system(core, vpu->res->mreg_base, vpu->base);

drivers/media/platform/amphion/vpu_dbg.c

436

struct vpu_dev *vpu;

drivers/media/platform/amphion/vpu_dbg.c

439

if (!inst || !inst->core || !inst->core->vpu)

drivers/media/platform/amphion/vpu_dbg.c

442

vpu = inst->core->vpu;

drivers/media/platform/amphion/vpu_dbg.c

443

if (!vpu->debugfs)

drivers/media/platform/amphion/vpu_dbg.c

452

vpu->debugfs,

drivers/media/platform/amphion/vpu_dbg.c

472

struct vpu_dev *vpu;

drivers/media/platform/amphion/vpu_dbg.c

475

if (!core || !core->vpu)

drivers/media/platform/amphion/vpu_dbg.c

478

vpu = core->vpu;

drivers/media/platform/amphion/vpu_dbg.c

479

if (!vpu->debugfs)

drivers/media/platform/amphion/vpu_dbg.c

486

vpu->debugfs,

drivers/media/platform/amphion/vpu_dbg.c

494

vpu->debugfs,

drivers/media/platform/amphion/vpu_drv.c

100

INIT_LIST_HEAD(&vpu->cores);

drivers/media/platform/amphion/vpu_drv.c

101

platform_set_drvdata(pdev, vpu);

drivers/media/platform/amphion/vpu_drv.c

102

atomic_set(&vpu->ref_vpu, 0);

drivers/media/platform/amphion/vpu_drv.c

103

atomic_set(&vpu->ref_enc, 0);

drivers/media/platform/amphion/vpu_drv.c

104

atomic_set(&vpu->ref_dec, 0);

drivers/media/platform/amphion/vpu_drv.c

105

vpu->get_vpu = vpu_dev_get;

drivers/media/platform/amphion/vpu_drv.c

106

vpu->put_vpu = vpu_dev_put;

drivers/media/platform/amphion/vpu_drv.c

107

vpu->get_enc = vpu_enc_get;

drivers/media/platform/amphion/vpu_drv.c

108

vpu->put_enc = vpu_enc_put;

drivers/media/platform/amphion/vpu_drv.c

109

vpu->get_dec = vpu_dec_get;

drivers/media/platform/amphion/vpu_drv.c

110

vpu->put_dec = vpu_dec_put;

drivers/media/platform/amphion/vpu_drv.c

112

vpu->base = devm_platform_ioremap_resource(pdev, 0);

drivers/media/platform/amphion/vpu_drv.c

113

if (IS_ERR(vpu->base))

drivers/media/platform/amphion/vpu_drv.c

114

return PTR_ERR(vpu->base);

drivers/media/platform/amphion/vpu_drv.c

116

vpu->res = of_device_get_match_data(dev);

drivers/media/platform/amphion/vpu_drv.c

117

if (!vpu->res)

drivers/media/platform/amphion/vpu_drv.c

122

ret = v4l2_device_register(dev, &vpu->v4l2_dev);

drivers/media/platform/amphion/vpu_drv.c

126

vpu_init_media_device(vpu);

drivers/media/platform/amphion/vpu_drv.c

127

vpu->encoder.type = VPU_CORE_TYPE_ENC;

drivers/media/platform/amphion/vpu_drv.c

128

vpu->encoder.function = MEDIA_ENT_F_PROC_VIDEO_ENCODER;

drivers/media/platform/amphion/vpu_drv.c

129

vpu->decoder.type = VPU_CORE_TYPE_DEC;

drivers/media/platform/amphion/vpu_drv.c

130

vpu->decoder.function = MEDIA_ENT_F_PROC_VIDEO_DECODER;

drivers/media/platform/amphion/vpu_drv.c

131

ret = vpu_add_func(vpu, &vpu->decoder);

drivers/media/platform/amphion/vpu_drv.c

134

ret = vpu_add_func(vpu, &vpu->encoder);

drivers/media/platform/amphion/vpu_drv.c

137

ret = media_device_register(&vpu->mdev);

drivers/media/platform/amphion/vpu_drv.c

140

vpu->debugfs = debugfs_create_dir("amphion_vpu", NULL);

drivers/media/platform/amphion/vpu_drv.c

147

vpu_remove_func(&vpu->encoder);

drivers/media/platform/amphion/vpu_drv.c

149

vpu_remove_func(&vpu->decoder);

drivers/media/platform/amphion/vpu_drv.c

151

media_device_cleanup(&vpu->mdev);

drivers/media/platform/amphion/vpu_drv.c

152

v4l2_device_unregister(&vpu->v4l2_dev);

drivers/media/platform/amphion/vpu_drv.c

162

struct vpu_dev *vpu = platform_get_drvdata(pdev);

drivers/media/platform/amphion/vpu_drv.c

165

debugfs_remove_recursive(vpu->debugfs);

drivers/media/platform/amphion/vpu_drv.c

166

vpu->debugfs = NULL;

drivers/media/platform/amphion/vpu_drv.c

170

media_device_unregister(&vpu->mdev);

drivers/media/platform/amphion/vpu_drv.c

171

vpu_remove_func(&vpu->decoder);

drivers/media/platform/amphion/vpu_drv.c

172

vpu_remove_func(&vpu->encoder);

drivers/media/platform/amphion/vpu_drv.c

173

media_device_cleanup(&vpu->mdev);

drivers/media/platform/amphion/vpu_drv.c

174

v4l2_device_unregister(&vpu->v4l2_dev);

drivers/media/platform/amphion/vpu_drv.c

175

mutex_destroy(&vpu->lock);

drivers/media/platform/amphion/vpu_drv.c

32

void vpu_writel(struct vpu_dev *vpu, u32 reg, u32 val)

drivers/media/platform/amphion/vpu_drv.c

34

writel(val, vpu->base + reg);

drivers/media/platform/amphion/vpu_drv.c

37

u32 vpu_readl(struct vpu_dev *vpu, u32 reg)

drivers/media/platform/amphion/vpu_drv.c

39

return readl(vpu->base + reg);

drivers/media/platform/amphion/vpu_drv.c

42

static void vpu_dev_get(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_drv.c

44

if (atomic_inc_return(&vpu->ref_vpu) == 1 && vpu->res->setup)

drivers/media/platform/amphion/vpu_drv.c

45

vpu->res->setup(vpu);

drivers/media/platform/amphion/vpu_drv.c

48

static void vpu_dev_put(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_drv.c

50

atomic_dec(&vpu->ref_vpu);

drivers/media/platform/amphion/vpu_drv.c

53

static void vpu_enc_get(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_drv.c

55

if (atomic_inc_return(&vpu->ref_enc) == 1 && vpu->res->setup_encoder)

drivers/media/platform/amphion/vpu_drv.c

56

vpu->res->setup_encoder(vpu);

drivers/media/platform/amphion/vpu_drv.c

59

static void vpu_enc_put(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_drv.c

61

atomic_dec(&vpu->ref_enc);

drivers/media/platform/amphion/vpu_drv.c

64

static void vpu_dec_get(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_drv.c

66

if (atomic_inc_return(&vpu->ref_dec) == 1 && vpu->res->setup_decoder)

drivers/media/platform/amphion/vpu_drv.c

67

vpu->res->setup_decoder(vpu);

drivers/media/platform/amphion/vpu_drv.c

70

static void vpu_dec_put(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_drv.c

72

atomic_dec(&vpu->ref_dec);

drivers/media/platform/amphion/vpu_drv.c

75

static int vpu_init_media_device(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_drv.c

77

vpu->mdev.dev = vpu->dev;

drivers/media/platform/amphion/vpu_drv.c

78

strscpy(vpu->mdev.model, "amphion-vpu", sizeof(vpu->mdev.model));

drivers/media/platform/amphion/vpu_drv.c

79

strscpy(vpu->mdev.bus_info, "platform: amphion-vpu", sizeof(vpu->mdev.bus_info));

drivers/media/platform/amphion/vpu_drv.c

80

media_device_init(&vpu->mdev);

drivers/media/platform/amphion/vpu_drv.c

81

vpu->v4l2_dev.mdev = &vpu->mdev;

drivers/media/platform/amphion/vpu_drv.c

89

struct vpu_dev *vpu;

drivers/media/platform/amphion/vpu_drv.c

93

vpu = devm_kzalloc(dev, sizeof(*vpu), GFP_KERNEL);

drivers/media/platform/amphion/vpu_drv.c

94

if (!vpu)

drivers/media/platform/amphion/vpu_drv.c

97

vpu->pdev = pdev;

drivers/media/platform/amphion/vpu_drv.c

98

vpu->dev = dev;

drivers/media/platform/amphion/vpu_drv.c

99

mutex_init(&vpu->lock);

drivers/media/platform/amphion/vpu_imx8q.c

161

p[16] = core->vpu->res->plat_type;

drivers/media/platform/amphion/vpu_imx8q.c

42

int vpu_imx8q_setup_dec(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_imx8q.c

46

vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f);

drivers/media/platform/amphion/vpu_imx8q.c

47

vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff);

drivers/media/platform/amphion/vpu_imx8q.c

52

int vpu_imx8q_setup_enc(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_imx8q.c

57

int vpu_imx8q_setup(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_imx8q.c

61

vpu_readl(vpu, offset + 0x108);

drivers/media/platform/amphion/vpu_imx8q.c

63

vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1);

drivers/media/platform/amphion/vpu_imx8q.c

64

vpu_writel(vpu, offset + 0x190, 0xffffffff);

drivers/media/platform/amphion/vpu_imx8q.c

65

vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff);

drivers/media/platform/amphion/vpu_imx8q.c

66

vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE);

drivers/media/platform/amphion/vpu_imx8q.c

67

vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_SET, 0x7);

drivers/media/platform/amphion/vpu_imx8q.c

68

vpu_writel(vpu, XMEM_CONTROL, 0x102);

drivers/media/platform/amphion/vpu_imx8q.c

70

vpu_readl(vpu, offset + 0x108);

drivers/media/platform/amphion/vpu_imx8q.c

75

static int vpu_imx8q_reset_enc(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_imx8q.c

80

static int vpu_imx8q_reset_dec(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_imx8q.c

84

vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_CLR, 0xffffffff);

drivers/media/platform/amphion/vpu_imx8q.c

89

int vpu_imx8q_reset(struct vpu_dev *vpu)

drivers/media/platform/amphion/vpu_imx8q.c

93

vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_CLR, 0x7);

drivers/media/platform/amphion/vpu_imx8q.c

94

vpu_imx8q_reset_enc(vpu);

drivers/media/platform/amphion/vpu_imx8q.c

95

vpu_imx8q_reset_dec(vpu);

drivers/media/platform/amphion/vpu_imx8q.h

103

int vpu_imx8q_setup_dec(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu_imx8q.h

104

int vpu_imx8q_setup_enc(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu_imx8q.h

105

int vpu_imx8q_setup(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu_imx8q.h

106

int vpu_imx8q_reset(struct vpu_dev *vpu);

drivers/media/platform/amphion/vpu_rpc.c

225

static struct vpu_iface_ops *vpu_get_iface(struct vpu_dev *vpu, enum vpu_core_type type)

drivers/media/platform/amphion/vpu_rpc.c

230

switch (vpu->res->plat_type) {

drivers/media/platform/amphion/vpu_rpc.c

248

return vpu_get_iface(core->vpu, core->type);

drivers/media/platform/amphion/vpu_rpc.c

256

return vpu_get_iface(inst->vpu, inst->type);

drivers/media/platform/amphion/vpu_v4l2.c

672

src_vq->dev = inst->vpu->dev;

drivers/media/platform/amphion/vpu_v4l2.c

688

dst_vq->dev = inst->vpu->dev;

drivers/media/platform/amphion/vpu_v4l2.c

701

vpu_trace(inst->vpu->dev, "%p\n", inst);

drivers/media/platform/amphion/vpu_v4l2.c

722

struct vpu_dev *vpu = video_drvdata(file);

drivers/media/platform/amphion/vpu_v4l2.c

730

func = &vpu->encoder;

drivers/media/platform/amphion/vpu_v4l2.c

732

func = &vpu->decoder;

drivers/media/platform/amphion/vpu_v4l2.c

737

inst->vpu = vpu;

drivers/media/platform/amphion/vpu_v4l2.c

738

inst->core = vpu_request_core(vpu, inst->type);

drivers/media/platform/amphion/vpu_v4l2.c

758

dev_err(vpu->dev, "v4l2_m2m_ctx_init fail\n");

drivers/media/platform/amphion/vpu_v4l2.c

776

vpu_trace(vpu->dev, "tgid = %d, pid = %d, type = %s, inst = %p\n",

drivers/media/platform/amphion/vpu_v4l2.c

789

struct vpu_dev *vpu = video_drvdata(file);

drivers/media/platform/amphion/vpu_v4l2.c

792

vpu_trace(vpu->dev, "tgid = %d, pid = %d, inst = %p\n", inst->tgid, inst->pid, inst);

drivers/media/platform/amphion/vpu_v4l2.c

811

int vpu_add_func(struct vpu_dev *vpu, struct vpu_func *func)

drivers/media/platform/amphion/vpu_v4l2.c

816

if (!vpu || !func)

drivers/media/platform/amphion/vpu_v4l2.c

824

dev_err(vpu->dev, "v4l2_m2m_init fail\n");

drivers/media/platform/amphion/vpu_v4l2.c

832

dev_err(vpu->dev, "alloc vpu decoder video device fail\n");

drivers/media/platform/amphion/vpu_v4l2.c

837

vfd->v4l2_dev = &vpu->v4l2_dev;

drivers/media/platform/amphion/vpu_v4l2.c

848

video_set_drvdata(vfd, vpu);

drivers/media/platform/chips-media/wave5/wave5-vpu.c

224

struct vpu_device *vpu = dev_get_drvdata(dev);

drivers/media/platform/chips-media/wave5/wave5-vpu.c

229

if (vpu->irq < 0)

drivers/media/platform/chips-media/wave5/wave5-vpu.c

230

hrtimer_cancel(&vpu->hrtimer);

drivers/media/platform/chips-media/wave5/wave5-vpu.c

233

clk_bulk_disable_unprepare(vpu->num_clks, vpu->clks);

drivers/media/platform/chips-media/wave5/wave5-vpu.c

240

struct vpu_device *vpu = dev_get_drvdata(dev);

drivers/media/platform/chips-media/wave5/wave5-vpu.c

244

ret = clk_bulk_prepare_enable(vpu->num_clks, vpu->clks);

drivers/media/platform/chips-media/wave5/wave5-vpu.c

250

if (vpu->irq < 0 && !hrtimer_active(&vpu->hrtimer))

drivers/media/platform/chips-media/wave5/wave5-vpu.c

251

hrtimer_start(&vpu->hrtimer, ns_to_ktime(vpu->vpu_poll_interval * NSEC_PER_MSEC),

drivers/media/platform/mediatek/mdp/mtk_mdp_core.h

217

struct mtk_mdp_vpu vpu;

drivers/media/platform/mediatek/mdp/mtk_mdp_m2m.c

1148

mtk_mdp_vpu_deinit(&ctx->vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_m2m.c

521

ret = mtk_mdp_vpu_process(&ctx->vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_m2m.c

737

ret = mtk_mdp_vpu_init(&ctx->vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

107

struct mdp_config *config = &ctx->vpu.vsi->dst_config;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

123

struct mdp_config *config = &ctx->vpu.vsi->dst_config;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

124

struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

136

struct mdp_config_misc *misc = &ctx->vpu.vsi->misc;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

145

struct mdp_config_misc *misc = &ctx->vpu.vsi->misc;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

51

struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

61

struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

71

struct mdp_config *config = &ctx->vpu.vsi->src_config;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

92

struct mdp_config *config = &ctx->vpu.vsi->src_config;

drivers/media/platform/mediatek/mdp/mtk_mdp_regs.c

93

struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer;

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

103

msg.vpu_inst_addr = vpu->inst_addr;

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

104

msg.ap_inst = (unsigned long)vpu;

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

105

err = mtk_mdp_vpu_send_msg((void *)&msg, sizeof(msg), vpu, IPI_MDP);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

106

if (!err && vpu->failure)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

112

int mtk_mdp_vpu_init(struct mtk_mdp_vpu *vpu)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

116

struct mtk_mdp_ctx *ctx = vpu_to_ctx(vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

118

vpu->pdev = ctx->mdp_dev->vpu_dev;

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

122

msg.ap_inst = (unsigned long)vpu;

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

123

err = mtk_mdp_vpu_send_msg((void *)&msg, sizeof(msg), vpu, IPI_MDP);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

124

if (!err && vpu->failure)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

13

static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

130

int mtk_mdp_vpu_deinit(struct mtk_mdp_vpu *vpu)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

132

return mtk_mdp_vpu_send_ap_ipi(vpu, AP_MDP_DEINIT);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

135

int mtk_mdp_vpu_process(struct mtk_mdp_vpu *vpu)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

137

return mtk_mdp_vpu_send_ap_ipi(vpu, AP_MDP_PROCESS);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

15

return container_of(vpu, struct mtk_mdp_ctx, vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

20

struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

24

vpu->vsi = (struct mdp_process_vsi *)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

25

vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

26

vpu->inst_addr = msg->vpu_inst_addr;

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

34

struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

38

vpu->failure = msg->status;

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

39

if (!vpu->failure) {

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

48

ctx = vpu_to_ctx(vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

55

ctx = vpu_to_ctx(vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

57

msg_id, vpu->failure);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

75

static int mtk_mdp_vpu_send_msg(void *msg, int len, struct mtk_mdp_vpu *vpu,

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

78

struct mtk_mdp_ctx *ctx = vpu_to_ctx(vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

81

if (!vpu->pdev) {

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

87

err = vpu_ipi_send(vpu->pdev, (enum ipi_id)id, msg, len);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.c

96

static int mtk_mdp_vpu_send_ap_ipi(struct mtk_mdp_vpu *vpu, uint32_t msg_id)

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.h

29

int mtk_mdp_vpu_init(struct mtk_mdp_vpu *vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.h

30

int mtk_mdp_vpu_deinit(struct mtk_mdp_vpu *vpu);

drivers/media/platform/mediatek/mdp/mtk_mdp_vpu.h

31

int mtk_mdp_vpu_process(struct mtk_mdp_vpu *vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c

112

long bound = mdp->vpu.config_size;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c

127

if ((long)cfg_n - (long)mdp->vpu.config > bound) {

drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c

119

mdp_vpu_dev_deinit(&mdp->vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c

155

mdp_vpu_shared_mem_free(&mdp->vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c

99

ret = mdp_vpu_dev_init(&mdp->vpu, mdp->scp, &mdp->vpu_lock);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h

120

struct mdp_vpu_dev vpu;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c

100

task.config = ctx->mdp_dev->vpu.config;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c

93

ret = mdp_vpu_process(&ctx->mdp_dev->vpu, &param);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

101

vpu->status = msg->status;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

102

complete(&vpu->ipi_acked);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

111

struct mdp_vpu_dev *vpu =

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

115

struct mdp_dev *mdp = vpu_to_mdp(vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

119

vpu->status = param->state;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

120

complete(&vpu->ipi_acked);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

14

static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

16

return container_of(vpu, struct mdp_dev, vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

165

static int mdp_vpu_sendmsg(struct mdp_vpu_dev *vpu, enum scp_ipi_id id,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

168

struct mdp_dev *mdp = vpu_to_mdp(vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

172

if (!vpu->scp) {

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

176

ret = scp_ipi_send(vpu->scp, id, buf, len, 2000);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

182

ret = wait_for_completion_timeout(&vpu->ipi_acked,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

186

else if (vpu->status)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

19

static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

193

int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

197

.drv_data = (unsigned long)vpu,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

199

struct mdp_dev *mdp = vpu_to_mdp(vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

203

init_completion(&vpu->ipi_acked);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

204

vpu->scp = scp;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

205

vpu->lock = lock;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

206

vpu->work_size = 0;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

207

err = mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_INIT, &msg, sizeof(msg));

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

212

mutex_lock(vpu->lock);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

213

vpu->work_size = ALIGN(vpu->work_size, 64);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

214

vpu->param_size = ALIGN(sizeof(struct img_ipi_frameparam), 64);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

215

vpu->config_size = ALIGN(sizeof(struct img_config) * pp_num, 64);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

216

err = mdp_vpu_shared_mem_alloc(vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

217

mutex_unlock(vpu->lock);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

225

vpu->param, &vpu->param_addr, vpu->param_size,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

226

vpu->work, &vpu->work_addr, vpu->work_size,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

227

vpu->config, &vpu->config_addr, vpu->config_size);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

229

msg.work_addr = vpu->work_addr;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

23

if (IS_ERR_OR_NULL(vpu))

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

230

msg.work_size = vpu->work_size;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

231

err = mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_INIT, &msg, sizeof(msg));

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

238

switch (vpu->status) {

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

251

int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

254

.drv_data = (unsigned long)vpu,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

255

.work_addr = vpu->work_addr,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

258

return mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_DEINIT, &msg, sizeof(msg));

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

26

dev = scp_get_device(vpu->scp);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

261

int mdp_vpu_process(struct mdp_vpu_dev *vpu, struct img_ipi_frameparam *param)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

263

struct mdp_dev *mdp = vpu_to_mdp(vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

266

mutex_lock(vpu->lock);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

267

if (mdp_vpu_shared_mem_alloc(vpu)) {

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

269

mutex_unlock(vpu->lock);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

273

memset(vpu->param, 0, vpu->param_size);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

274

memset(vpu->work, 0, vpu->work_size);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

275

memset(vpu->config, 0, vpu->config_size);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

277

param->self_data.va = (unsigned long)vpu->work;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

278

param->self_data.pa = vpu->work_addr;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

279

param->config_data.va = (unsigned long)vpu->config;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

28

if (!vpu->param) {

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

280

param->config_data.pa = vpu->config_addr;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

281

param->drv_data = (unsigned long)vpu;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

282

memcpy(vpu->param, param, sizeof(*param));

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

284

addr.pa = vpu->param_addr;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

285

addr.va = (unsigned long)vpu->param;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

286

mutex_unlock(vpu->lock);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

287

return mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_FRAME, &addr, sizeof(addr));

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

29

vpu->param = dma_alloc_wc(dev, vpu->param_size,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

30

&vpu->param_addr, GFP_KERNEL);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

31

if (!vpu->param)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

35

if (!vpu->work) {

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

36

vpu->work = dma_alloc_wc(dev, vpu->work_size,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

37

&vpu->work_addr, GFP_KERNEL);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

38

if (!vpu->work)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

42

if (!vpu->config) {

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

43

vpu->config = dma_alloc_wc(dev, vpu->config_size,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

44

&vpu->config_addr, GFP_KERNEL);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

45

if (!vpu->config)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

52

dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

53

vpu->work = NULL;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

55

dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

56

vpu->param = NULL;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

61

void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

65

if (IS_ERR_OR_NULL(vpu))

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

68

dev = scp_get_device(vpu->scp);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

70

if (vpu->param && vpu->param_addr)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

71

dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

73

if (vpu->work && vpu->work_addr)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

74

dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

76

if (vpu->config && vpu->config_addr)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

77

dma_free_wc(dev, vpu->config_size, vpu->config, vpu->config_addr);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

84

struct mdp_vpu_dev *vpu =

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

87

if (!vpu->work_size)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

88

vpu->work_size = msg->work_size;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

90

vpu->status = msg->status;

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

91

complete(&vpu->ipi_acked);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c

98

struct mdp_vpu_dev *vpu =

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h

57

void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h

58

int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h

60

int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu);

drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h

61

int mdp_vpu_process(struct mdp_vpu_dev *vpu, struct img_ipi_frameparam *param);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1887

instance->vpu.id = SCP_IPI_VDEC_LAT;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1888

instance->vpu.core_id = SCP_IPI_VDEC_CORE;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1889

instance->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1890

instance->vpu.codec_type = ctx->current_codec;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1892

ret = vpu_dec_init(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1899

vsi = instance->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1936

vpu_dec_deinit(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1950

vpu_dec_deinit(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1969

return vpu_dec_reset(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1982

vpu_dec_get_param(&instance->vpu, data, 3, GET_PARAM_PIC_INFO);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1986

ctx->picinfo.fb_sz[0] = instance->vpu.fb_sz[0];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1987

ctx->picinfo.fb_sz[1] = instance->vpu.fb_sz[1];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

2077

ret = vpu_dec_start(&instance->vpu, NULL, 0);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

2094

vpu_dec_end(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

2168

ret = vpu_dec_core(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

2183

vpu_dec_core_end(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

709

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

776

vsi = instance->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

807

vsi = instance->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

130

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

279

inst->vpu.id = IPI_VDEC_H264;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

280

inst->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

282

err = vpu_dec_init(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

288

inst->vsi = (struct vdec_h264_vsi *)inst->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

299

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

310

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

333

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

350

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

382

err = vpu_dec_start(vpu, data, 2);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c

413

vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

282

inst->vpu.id = SCP_IPI_VDEC_H264;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

283

inst->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

285

err = vpu_dec_init(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

291

memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx));

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

311

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

322

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

335

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

347

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

397

memcpy(inst->vpu.vsi, &inst->vsi_ctx, sizeof(inst->vsi_ctx));

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

398

err = vpu_dec_start(vpu, data, 2);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

408

vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

410

memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx));

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c

89

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1010

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1020

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1069

memcpy(inst->vpu.vsi, &inst->vsi_ctx_ext, sizeof(inst->vsi_ctx_ext));

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1070

err = vpu_dec_start(vpu, data, 2);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1081

err = vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1085

memcpy(&inst->vsi_ctx_ext, inst->vpu.vsi, sizeof(inst->vsi_ctx_ext));

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1105

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1116

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1173

memcpy(inst->vpu.vsi, &inst->vsi_ctx, sizeof(inst->vsi_ctx));

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1174

err = vpu_dec_start(vpu, data, 2);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1185

err = vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1189

memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx));

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1217

inst->vpu.id = SCP_IPI_VDEC_LAT;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1218

inst->vpu.core_id = SCP_IPI_VDEC_CORE;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1219

inst->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1220

inst->vpu.codec_type = ctx->current_codec;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1221

inst->vpu.capture_type = ctx->capture_fourcc;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1223

err = vpu_dec_init(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1233

inst->vsi_ext = inst->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1245

inst->vsi = inst->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1264

inst, inst->vpu.codec_type);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

1278

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

242

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

444

vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

448

ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

449

ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

584

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

595

err = vpu_dec_core(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

608

vpu_dec_core_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

636

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

682

err = vpu_dec_core(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

695

vpu_dec_core_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

741

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

756

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

804

err = vpu_dec_start(vpu, data, 2);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

829

err = vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

864

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

881

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

953

err = vpu_dec_start(vpu, data, 2);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c

977

err = vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

1007

err = vpu_dec_start(vpu, data, 2);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

1026

err = vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

363

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

687

vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

691

ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

692

ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

867

inst->vpu.id = SCP_IPI_VDEC_LAT;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

868

inst->vpu.core_id = SCP_IPI_VDEC_CORE;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

869

inst->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

870

inst->vpu.codec_type = ctx->current_codec;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

871

inst->vpu.capture_type = ctx->capture_fourcc;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

873

err = vpu_dec_init(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

880

inst->vsi = inst->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

882

(struct vdec_hevc_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

899

inst, inst->vpu.codec_type);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

913

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

930

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

942

err = vpu_dec_core(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

955

vpu_dec_core_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

975

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

989

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

161

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

399

inst->vpu.id = IPI_VDEC_VP8;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

400

inst->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

402

err = vpu_dec_init(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

408

inst->vsi = (struct vdec_vp8_vsi *)inst->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

421

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

432

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

442

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

468

err = vpu_dec_start(vpu, &data, 1);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

496

err = vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c

598

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

103

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

125

vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

129

ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

130

ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

284

inst->vpu.id = SCP_IPI_VDEC_LAT;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

285

inst->vpu.core_id = SCP_IPI_VDEC_CORE;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

286

inst->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

287

inst->vpu.codec_type = ctx->current_codec;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

288

inst->vpu.capture_type = ctx->capture_fourcc;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

290

err = vpu_dec_init(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

296

inst->vsi = inst->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

305

inst, inst->vpu.codec_type, inst->vpu.vsi);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

311

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

321

struct vdec_vpu_inst *vpu = &inst->vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

332

return vpu_dec_reset(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

367

err = vpu_dec_start(vpu, &data, 1);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

383

err = vpu_dec_end(vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

426

vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

201

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

587

if (vpu_dec_end(&inst->vpu)) {

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

662

if (vpu_dec_reset(&inst->vpu))

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

759

ret = vpu_dec_deinit(&inst->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

786

inst->vpu.id = IPI_VDEC_VP9;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

787

inst->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

789

if (vpu_dec_init(&inst->vpu)) {

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

794

inst->vsi = (struct vdec_vp9_vsi *)inst->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

872

ret = vpu_dec_start(&inst->vpu, data, 3);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c

882

ret = vpu_dec_start(&inst->vpu, NULL, 0);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1856

instance->vpu.id = SCP_IPI_VDEC_LAT;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1857

instance->vpu.core_id = SCP_IPI_VDEC_CORE;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1858

instance->vpu.ctx = ctx;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1859

instance->vpu.codec_type = ctx->current_codec;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1861

ret = vpu_dec_init(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1869

vsi = instance->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1896

vpu_dec_deinit(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1909

vpu_dec_deinit(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1923

return vpu_dec_reset(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1936

vpu_dec_get_param(&instance->vpu, data, 3, GET_PARAM_PIC_INFO);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1940

ctx->picinfo.fb_sz[0] = instance->vpu.fb_sz[0];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1941

ctx->picinfo.fb_sz[1] = instance->vpu.fb_sz[1];

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

2003

ret = vpu_dec_start(&instance->vpu, NULL, 0);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

2017

vpu_dec_end(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

2073

ret = vpu_dec_start(&instance->vpu, NULL, 0);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

2087

vpu_dec_end(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

2161

ret = vpu_dec_core(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

2175

vpu_dec_core_end(&instance->vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

447

struct vdec_vpu_inst vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

512

vsi = instance->vpu.vsi;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

107

struct vdec_vpu_inst *vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

110

vpu = (struct vdec_vpu_inst *)(unsigned long)msg->ap_inst_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

111

if (!priv || !vpu) {

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

116

if (!vpu_dec_check_ap_inst(dec_dev, vpu) || msg->msg_id < VPU_IPIMSG_DEC_INIT_ACK ||

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

118

mtk_v4l2_vdec_err(vpu->ctx, "vdec msg id not correctly => 0x%x", msg->msg_id);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

119

vpu->failure = -EINVAL;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

123

vpu->failure = msg->status;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

14

struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

144

mtk_vdec_err(vpu->ctx, "invalid msg=%X", msg->msg_id);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

149

vpu->signaled = 1;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

152

static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

157

mtk_vdec_debug(vpu->ctx, "id=%X", msgid);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

159

vpu->failure = 0;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

160

vpu->signaled = 0;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

162

if (vpu->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_LAT_SINGLE_CORE) {

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

165

id = vpu->core_id;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

167

id = vpu->id;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

169

id = vpu->id;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

17

mtk_vdec_debug(vpu->ctx, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

172

err = mtk_vcodec_fw_ipi_send(vpu->ctx->dev->fw_handler, id, msg,

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

175

mtk_vdec_err(vpu->ctx, "send fail vpu_id=%d msg_id=%X status=%d",

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

180

return vpu->failure;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

183

static int vcodec_send_ap_ipi(struct vdec_vpu_inst *vpu, unsigned int msg_id)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

188

mtk_vdec_debug(vpu->ctx, "+ id=%X", msg_id);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

191

if (vpu->fw_abi_version < 2)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

192

msg.vpu_inst_addr = vpu->inst_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

194

msg.inst_id = vpu->inst_id;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

195

msg.codec_type = vpu->codec_type;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

197

err = vcodec_vpu_send_msg(vpu, &msg, sizeof(msg));

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

198

mtk_vdec_debug(vpu->ctx, "- id=%X ret=%d", msg_id, err);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

202

int vpu_dec_init(struct vdec_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

207

init_waitqueue_head(&vpu->wq);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

208

vpu->handler = vpu_dec_ipi_handler;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

209

vpu->ctx->vpu_inst = vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

21

vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler,

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

211

err = mtk_vcodec_fw_ipi_register(vpu->ctx->dev->fw_handler, vpu->id,

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

212

vpu->handler, "vdec", vpu->ctx->dev);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

214

mtk_vdec_err(vpu->ctx, "vpu_ipi_register fail status=%d", err);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

218

if (vpu->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_LAT_SINGLE_CORE) {

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

219

err = mtk_vcodec_fw_ipi_register(vpu->ctx->dev->fw_handler,

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

220

vpu->core_id, vpu->handler,

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

221

"vdec", vpu->ctx->dev);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

223

mtk_vdec_err(vpu->ctx, "vpu_ipi_register core fail status=%d", err);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

229

msg.ap_inst_addr = (unsigned long)vpu;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

23

vpu->inst_addr = msg->vpu_inst_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

230

msg.codec_type = vpu->codec_type;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

232

mtk_vdec_debug(vpu->ctx, "vdec_inst=%p", vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

234

err = vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg));

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

236

if (IS_ERR_OR_NULL(vpu->vsi)) {

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

237

mtk_vdec_err(vpu->ctx, "invalid vdec vsi, status=%d", err);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

241

mtk_vdec_debug(vpu->ctx, "- ret=%d", err);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

245

int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

25

mtk_vdec_debug(vpu->ctx, "- vpu_inst_addr = 0x%x", vpu->inst_addr);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

252

mtk_vdec_err(vpu->ctx, "invalid len = %d\n", len);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

257

if (vpu->fw_abi_version < 2)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

258

msg.vpu_inst_addr = vpu->inst_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

260

msg.inst_id = vpu->inst_id;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

264

msg.codec_type = vpu->codec_type;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

266

err = vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg));

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

267

mtk_vdec_debug(vpu->ctx, "- ret=%d", err);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

271

int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data,

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

278

mtk_vdec_err(vpu->ctx, "invalid len = %d\n", len);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

28

vpu->fw_abi_version = 0;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

283

msg.inst_id = vpu->inst_id;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

286

msg.codec_type = vpu->codec_type;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

288

err = vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg));

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

289

mtk_vdec_debug(vpu->ctx, "- ret=%d", err);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

293

int vpu_dec_core(struct vdec_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

295

return vcodec_send_ap_ipi(vpu, AP_IPIMSG_DEC_CORE);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

298

int vpu_dec_end(struct vdec_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

300

return vcodec_send_ap_ipi(vpu, AP_IPIMSG_DEC_END);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

303

int vpu_dec_core_end(struct vdec_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

305

return vcodec_send_ap_ipi(vpu, AP_IPIMSG_DEC_CORE_END);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

308

int vpu_dec_deinit(struct vdec_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

310

return vcodec_send_ap_ipi(vpu, AP_IPIMSG_DEC_DEINIT);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

313

int vpu_dec_reset(struct vdec_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

315

return vcodec_send_ap_ipi(vpu, AP_IPIMSG_DEC_RESET);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

33

vpu->inst_id = 0xdeadbeef;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

36

if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VPU)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

40

vpu->fw_abi_version = msg->vdec_abi_version;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

41

mtk_vdec_debug(vpu->ctx, "firmware version 0x%x\n", vpu->fw_abi_version);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

42

switch (vpu->fw_abi_version) {

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

46

vpu->inst_id = msg->inst_id;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

49

mtk_vdec_err(vpu->ctx, "unhandled firmware version 0x%x\n", vpu->fw_abi_version);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

50

vpu->failure = 1;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

57

struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

60

mtk_vdec_debug(vpu->ctx, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

65

vpu->fb_sz[0] = msg->data[0];

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

66

vpu->fb_sz[1] = msg->data[1];

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

69

mtk_vdec_err(vpu->ctx, "invalid get param type=%d", msg->param_type);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

70

vpu->failure = 1;

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

75

static bool vpu_dec_check_ap_inst(struct mtk_vcodec_dec_dev *dec_dev, struct vdec_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c

83

if (!IS_ERR_OR_NULL(ctx) && ctx->vpu_inst == vpu) {

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

106

int vpu_dec_core_end(struct vdec_vpu_inst *vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

116

int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data,

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

53

int vpu_dec_init(struct vdec_vpu_inst *vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

63

int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

73

int vpu_dec_end(struct vdec_vpu_inst *vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

80

int vpu_dec_deinit(struct vdec_vpu_inst *vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

88

int vpu_dec_reset(struct vdec_vpu_inst *vpu);

drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.h

96

int vpu_dec_core(struct vdec_vpu_inst *vpu);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

102

mtk_venc_err(vpu->ctx, "unknown msg id %x", msg->msg_id);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

107

vpu->signaled = 1;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

11

static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data)

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

110

static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, void *msg,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

115

if (!vpu->ctx->dev->fw_handler) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

116

mtk_venc_err(vpu->ctx, "inst dev is NULL");

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

120

status = mtk_vcodec_fw_ipi_send(vpu->ctx->dev->fw_handler, vpu->id, msg,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

123

mtk_venc_err(vpu->ctx, "vpu_ipi_send msg_id %x len %d fail %d",

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

127

if (vpu->failure)

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

133

int vpu_enc_init(struct venc_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

138

init_waitqueue_head(&vpu->wq_hd);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

139

vpu->signaled = 0;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

140

vpu->failure = 0;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

141

vpu->ctx->vpu_inst = vpu;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

143

status = mtk_vcodec_fw_ipi_register(vpu->ctx->dev->fw_handler, vpu->id,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

145

vpu->ctx->dev);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

148

mtk_venc_err(vpu->ctx, "vpu_ipi_register fail %d", status);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

15

vpu->inst_addr = msg->vpu_inst_addr;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

153

out.venc_inst = (unsigned long)vpu;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

154

if (vpu_enc_send_msg(vpu, &out, sizeof(out))) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

155

mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_INIT fail");

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

159

if (IS_ERR_OR_NULL(vpu->vsi)) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

16

vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

160

mtk_venc_err(vpu->ctx, "invalid venc vsi");

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

167

static unsigned int venc_enc_param_crop_right(struct venc_vpu_inst *vpu,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

186

int vpu_enc_set_param(struct venc_vpu_inst *vpu,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

190

const bool is_ext = MTK_ENC_CTX_IS_EXT(vpu->ctx);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

196

mtk_venc_debug(vpu->ctx, "id %d ->", id);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

199

out.base.vpu_inst_addr = vpu->inst_addr;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

20

if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VPU)

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

206

venc_enc_param_crop_right(vpu, enc_param);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

237

mtk_venc_err(vpu->ctx, "id %d not supported", id);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

24

mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n", msg->venc_abi_version);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

240

if (vpu_enc_send_msg(vpu, &out, msg_size)) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

241

mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_SET_PARAM %d fail", id);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

245

mtk_venc_debug(vpu->ctx, "id %d <-", id);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

250

static int vpu_enc_encode_32bits(struct venc_vpu_inst *vpu,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

256

const bool is_ext = MTK_ENC_CTX_IS_EXT(vpu->ctx);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

262

mtk_venc_debug(vpu->ctx, "bs_mode %d ->", bs_mode);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

265

out.base.vpu_inst_addr = vpu->inst_addr;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

275

mtk_venc_err(vpu->ctx, "dma_addr not align to 16");

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

289

if (vpu_enc_send_msg(vpu, &out, msg_size)) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

29

mtk_venc_err(vpu->ctx, "unhandled firmware version 0x%x\n",

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

290

mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_ENCODE %d fail", bs_mode);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

297

static int vpu_enc_encode_34bits(struct venc_vpu_inst *vpu,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

306

mtk_venc_debug(vpu->ctx, "bs_mode %d ->", bs_mode);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

309

out.vpu_inst_addr = vpu->inst_addr;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

31

vpu->failure = 1;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

320

mtk_venc_err(vpu->ctx, "dma_addr not align to 16");

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

334

if (vpu_enc_send_msg(vpu, &out, msg_size)) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

335

mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_ENCODE %d fail", bs_mode);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

342

int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

349

if (MTK_ENC_IOVA_IS_34BIT(vpu->ctx))

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

350

ret = vpu_enc_encode_34bits(vpu, bs_mode,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

353

ret = vpu_enc_encode_32bits(vpu, bs_mode,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

359

mtk_venc_debug(vpu->ctx, "bs_mode %d state %d size %d key_frm %d <-",

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

36

static void handle_enc_encode_msg(struct venc_vpu_inst *vpu, const void *data)

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

360

bs_mode, vpu->state, vpu->bs_size, vpu->is_key_frm);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

365

int vpu_enc_deinit(struct venc_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

370

out.vpu_inst_addr = vpu->inst_addr;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

371

if (vpu_enc_send_msg(vpu, &out, sizeof(out))) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

372

mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_DEINIT fail");

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

40

vpu->state = msg->state;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

41

vpu->bs_size = msg->bs_size;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

42

vpu->is_key_frm = msg->is_key_frm;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

45

static bool vpu_enc_check_ap_inst(struct mtk_vcodec_enc_dev *enc_dev, struct venc_vpu_inst *vpu)

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

53

if (!IS_ERR_OR_NULL(ctx) && ctx->vpu_inst == vpu) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

67

struct venc_vpu_inst *vpu;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

70

vpu = (struct venc_vpu_inst *)(unsigned long)msg->venc_inst;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

71

if (!priv || !vpu) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

76

mtk_venc_debug(vpu->ctx, "msg_id %x inst %p status %d", msg->msg_id, vpu, msg->status);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

77

if (!vpu_enc_check_ap_inst(enc_dev, vpu) || msg->msg_id < VPU_IPIMSG_ENC_INIT_DONE ||

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

79

mtk_v4l2_venc_err(vpu->ctx, "venc msg id not correctly => 0x%x", msg->msg_id);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

80

vpu->failure = -EINVAL;

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

84

vpu->failure = (msg->status != VENC_IPI_MSG_STATUS_OK);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

85

if (vpu->failure) {

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

86

mtk_venc_err(vpu->ctx, "vpu enc status failure %d", vpu->failure);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

92

handle_enc_init_msg(vpu, data);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c

97

handle_enc_encode_msg(vpu, data);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.h

40

int vpu_enc_init(struct venc_vpu_inst *vpu);

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.h

41

int vpu_enc_set_param(struct venc_vpu_inst *vpu,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.h

44

int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,

drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.h

48

int vpu_enc_deinit(struct venc_vpu_inst *vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1000

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1001

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1004

} while (!vpu_cfg_readl(vpu, VPU_IDLE_REG));

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1006

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1007

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1008

clk_unprepare(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1015

struct mtk_vpu *vpu = dev_get_drvdata(dev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1018

clk_prepare(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1019

ret = vpu_clock_enable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1021

clk_unprepare(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1026

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1028

vpu_cfg_writel(vpu,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1029

vpu_cfg_readl(vpu, VPU_INT_STATUS) & ~(VPU_IDLE_STATE),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1031

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

1032

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

227

static inline void vpu_cfg_writel(struct mtk_vpu *vpu, u32 val, u32 offset)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

229

writel(val, vpu->reg.cfg + offset);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

232

static inline u32 vpu_cfg_readl(struct mtk_vpu *vpu, u32 offset)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

234

return readl(vpu->reg.cfg + offset);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

237

static inline bool vpu_running(struct mtk_vpu *vpu)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

239

return vpu_cfg_readl(vpu, VPU_RESET) & BIT(0);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

242

static void vpu_clock_disable(struct mtk_vpu *vpu)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

245

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

246

if (!--vpu->wdt_refcnt)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

247

vpu_cfg_writel(vpu,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

248

vpu_cfg_readl(vpu, VPU_WDT_REG) & ~(1L << 31),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

250

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

252

clk_disable(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

255

static int vpu_clock_enable(struct mtk_vpu *vpu)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

259

ret = clk_enable(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

263

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

264

if (!vpu->wdt_refcnt++)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

265

vpu_cfg_writel(vpu,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

266

vpu_cfg_readl(vpu, VPU_WDT_REG) | (1L << 31),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

268

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

273

static void vpu_dump_status(struct mtk_vpu *vpu)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

275

dev_info(vpu->dev,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

278

vpu_running(vpu), vpu_cfg_readl(vpu, VPU_PC_REG),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

279

vpu_cfg_readl(vpu, VPU_RA_REG), vpu_cfg_readl(vpu, VPU_SP_REG),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

280

vpu_cfg_readl(vpu, VPU_IDLE_REG),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

281

vpu_cfg_readl(vpu, VPU_INT_STATUS),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

282

vpu_cfg_readl(vpu, HOST_TO_VPU),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

283

vpu_cfg_readl(vpu, VPU_TO_HOST),

drivers/media/platform/mediatek/vpu/mtk_vpu.c

284

vpu_cfg_readl(vpu, VPU_WDT_REG));

drivers/media/platform/mediatek/vpu/mtk_vpu.c

291

struct mtk_vpu *vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

294

if (!vpu) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

300

ipi_desc = vpu->ipi_desc;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

317

struct mtk_vpu *vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

318

struct share_obj __iomem *send_obj = vpu->send_buf;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

324

dev_err(vpu->dev, "failed to send ipi message\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

328

ret = vpu_clock_enable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

330

dev_err(vpu->dev, "failed to enable vpu clock\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

333

if (!vpu_running(vpu)) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

334

dev_err(vpu->dev, "vpu_ipi_send: VPU is not running\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

339

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

345

dev_err(vpu->dev, "vpu_ipi_send: IPI timeout!\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

347

vpu_dump_status(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

350

} while (vpu_cfg_readl(vpu, HOST_TO_VPU));

drivers/media/platform/mediatek/vpu/mtk_vpu.c

356

vpu->ipi_id_ack[id] = false;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

358

vpu_cfg_writel(vpu, 0x1, HOST_TO_VPU);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

360

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

364

ret = wait_event_timeout(vpu->ack_wq, vpu->ipi_id_ack[id], timeout);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

365

vpu->ipi_id_ack[id] = false;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

367

dev_err(vpu->dev, "vpu ipi %d ack time out !\n", id);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

369

vpu_dump_status(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

372

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

377

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

379

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

388

struct mtk_vpu *vpu = container_of(wdt, struct mtk_vpu, wdt);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

392

dev_info(vpu->dev, "vpu reset\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

393

ret = vpu_clock_enable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

395

dev_err(vpu->dev, "[VPU] wdt enables clock failed %d\n", ret);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

398

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

399

vpu_cfg_writel(vpu, 0x0, VPU_RESET);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

400

vpu->fw_loaded = false;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

401

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

402

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

407

dev_dbg(vpu->dev, "wdt handler func %d\n", index);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

416

struct mtk_vpu *vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

419

if (!vpu) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

424

handler = vpu->wdt.handler;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

427

dev_dbg(vpu->dev, "wdt register id %d\n", id);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

428

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

431

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

435

dev_err(vpu->dev, "register vpu wdt handler failed\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

442

struct mtk_vpu *vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

444

return vpu->run.dec_capability;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

450

struct mtk_vpu *vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

452

return vpu->run.enc_capability;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

459

struct mtk_vpu *vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

463

dev_err(vpu->dev, "invalid virtual data memory address\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

468

return (__force void *)(dtcm_dmem_addr + vpu->reg.tcm +

drivers/media/platform/mediatek/vpu/mtk_vpu.c

471

return vpu->extmem[D_FW].va + (dtcm_dmem_addr - VPU_DTCM_SIZE);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

499

static int load_requested_vpu(struct mtk_vpu *vpu,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

512

ret = request_firmware(&vpu_fw, fw_new_name, vpu->dev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

514

dev_info(vpu->dev, "Failed to load %s, %d, retry\n",

drivers/media/platform/mediatek/vpu/mtk_vpu.c

517

ret = request_firmware(&vpu_fw, fw_name, vpu->dev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

519

dev_err(vpu->dev, "Failed to load %s, %d\n", fw_name,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

526

dev_err(vpu->dev, "fw %s size %zu is abnormal\n", fw_name,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

531

dev_dbg(vpu->dev, "Downloaded fw %s size: %zu.\n",

drivers/media/platform/mediatek/vpu/mtk_vpu.c

535

vpu_cfg_writel(vpu, 0x0, VPU_RESET);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

539

dev_dbg(vpu->dev, "fw size %zu > limited fw size %zu\n",

drivers/media/platform/mediatek/vpu/mtk_vpu.c

542

dev_dbg(vpu->dev, "extra_fw_size %zu\n", extra_fw_size);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

545

dest = (__force void *)vpu->reg.tcm;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

551

dest = vpu->extmem[fw_type].va;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

552

dev_dbg(vpu->dev, "download extended memory type %x\n",

drivers/media/platform/mediatek/vpu/mtk_vpu.c

564

struct mtk_vpu *vpu;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

576

vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

577

run = &vpu->run;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

579

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

580

if (vpu->fw_loaded) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

581

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

584

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

586

ret = vpu_clock_enable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

592

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

595

dev_dbg(vpu->dev, "firmware request\n");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

597

ret = load_requested_vpu(vpu, P_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

604

ret = load_requested_vpu(vpu, D_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

610

vpu->fw_loaded = true;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

612

vpu_cfg_writel(vpu, 0x1, VPU_RESET);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

631

mutex_unlock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

632

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

640

struct mtk_vpu *vpu = priv;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

643

vpu->run.signaled = run->signaled;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

644

strscpy(vpu->run.fw_ver, run->fw_ver, sizeof(vpu->run.fw_ver));

drivers/media/platform/mediatek/vpu/mtk_vpu.c

645

vpu->run.dec_capability = run->dec_capability;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

646

vpu->run.enc_capability = run->enc_capability;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

647

wake_up_interruptible(&vpu->run.wq);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

659

struct mtk_vpu *vpu = dev_get_drvdata(dev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

661

ret = vpu_clock_enable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

663

dev_err(vpu->dev, "[VPU] enable clock failed %d\n", ret);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

668

running = vpu_running(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

669

pc = vpu_cfg_readl(vpu, VPU_PC_REG);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

670

wdt = vpu_cfg_readl(vpu, VPU_WDT_REG);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

671

host_to_vpu = vpu_cfg_readl(vpu, HOST_TO_VPU);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

672

vpu_to_host = vpu_cfg_readl(vpu, VPU_TO_HOST);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

673

ra = vpu_cfg_readl(vpu, VPU_RA_REG);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

674

sp = vpu_cfg_readl(vpu, VPU_SP_REG);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

675

idle = vpu_cfg_readl(vpu, VPU_IDLE_REG);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

677

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

689

vpu->run.fw_ver, pc, wdt,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

704

static void vpu_free_ext_mem(struct mtk_vpu *vpu, u8 fw_type)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

706

struct device *dev = vpu->dev;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

709

dma_free_coherent(dev, fw_ext_size, vpu->extmem[fw_type].va,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

710

vpu->extmem[fw_type].pa);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

713

static int vpu_alloc_ext_mem(struct mtk_vpu *vpu, u32 fw_type)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

715

struct device *dev = vpu->dev;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

719

u32 offset_4gb = vpu->enable_4GB ? 0x40000000 : 0;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

721

vpu->extmem[fw_type].va = dma_alloc_coherent(dev,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

723

&vpu->extmem[fw_type].pa,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

725

if (!vpu->extmem[fw_type].va) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

731

vpu_cfg_writel(vpu, 0x1, vpu_ext_mem0);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

732

vpu_cfg_writel(vpu, (vpu->extmem[fw_type].pa & 0xFFFFF000) + offset_4gb,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

737

(unsigned long long)vpu->extmem[fw_type].pa,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

738

vpu->extmem[fw_type].va);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

743

static void vpu_ipi_handler(struct mtk_vpu *vpu)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

745

struct share_obj __iomem *rcv_obj = vpu->recv_buf;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

746

struct vpu_ipi_desc *ipi_desc = vpu->ipi_desc;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

755

vpu->ipi_id_ack[id] = true;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

756

wake_up(&vpu->ack_wq);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

759

dev_err(vpu->dev, "No such ipi id = %d\n", id);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

763

static int vpu_ipi_init(struct mtk_vpu *vpu)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

766

vpu_cfg_writel(vpu, 0x0, VPU_TO_HOST);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

769

vpu->recv_buf = vpu->reg.tcm + VPU_DTCM_OFFSET;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

770

vpu->send_buf = vpu->recv_buf + 1;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

771

memset_io(vpu->recv_buf, 0, sizeof(struct share_obj));

drivers/media/platform/mediatek/vpu/mtk_vpu.c

772

memset_io(vpu->send_buf, 0, sizeof(struct share_obj));

drivers/media/platform/mediatek/vpu/mtk_vpu.c

779

struct mtk_vpu *vpu = priv;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

788

ret = clk_enable(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

790

dev_err(vpu->dev, "[VPU] enable clock failed %d\n", ret);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

793

vpu_to_host = vpu_cfg_readl(vpu, VPU_TO_HOST);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

795

vpu_ipi_handler(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

797

dev_err(vpu->dev, "vpu watchdog timeout! 0x%x", vpu_to_host);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

798

queue_work(vpu->wdt.wq, &vpu->wdt.ws);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

802

vpu_cfg_writel(vpu, 0x0, VPU_TO_HOST);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

803

clk_disable(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

813

struct mtk_vpu *vpu;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

820

vpu = devm_kzalloc(dev, sizeof(*vpu), GFP_KERNEL);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

821

if (!vpu)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

824

vpu->dev = &pdev->dev;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

825

vpu->reg.tcm = devm_platform_ioremap_resource_byname(pdev, "tcm");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

826

if (IS_ERR((__force void *)vpu->reg.tcm))

drivers/media/platform/mediatek/vpu/mtk_vpu.c

827

return PTR_ERR((__force void *)vpu->reg.tcm);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

829

vpu->reg.cfg = devm_platform_ioremap_resource_byname(pdev, "cfg_reg");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

830

if (IS_ERR((__force void *)vpu->reg.cfg))

drivers/media/platform/mediatek/vpu/mtk_vpu.c

831

return PTR_ERR((__force void *)vpu->reg.cfg);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

834

vpu->clk = devm_clk_get(dev, "main");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

835

if (IS_ERR(vpu->clk)) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

837

return PTR_ERR(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

840

platform_set_drvdata(pdev, vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

842

ret = clk_prepare(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

849

vpu->wdt.wq = create_singlethread_workqueue("vpu_wdt");

drivers/media/platform/mediatek/vpu/mtk_vpu.c

850

if (!vpu->wdt.wq) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

855

INIT_WORK(&vpu->wdt.ws, vpu_wdt_reset_func);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

856

mutex_init(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

858

ret = vpu_clock_enable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

865

ret = vpu_ipi_init(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

873

"vpu_init", vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

885

vpu_cfg_writel(vpu, 0x2, VPU_TCM_CFG);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

887

vpu->enable_4GB = !!(totalram_pages() > (SZ_2G >> PAGE_SHIFT));

drivers/media/platform/mediatek/vpu/mtk_vpu.c

888

dev_info(dev, "4GB mode %u\n", vpu->enable_4GB);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

890

if (vpu->enable_4GB) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

897

ret = vpu_alloc_ext_mem(vpu, D_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

903

ret = vpu_alloc_ext_mem(vpu, P_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

909

init_waitqueue_head(&vpu->run.wq);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

910

init_waitqueue_head(&vpu->ack_wq);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

915

vpu->reg.irq = ret;

drivers/media/platform/mediatek/vpu/mtk_vpu.c

916

ret = devm_request_irq(dev, vpu->reg.irq, vpu_irq_handler, 0,

drivers/media/platform/mediatek/vpu/mtk_vpu.c

917

pdev->name, vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

923

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

929

vpu_free_ext_mem(vpu, P_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

931

vpu_free_ext_mem(vpu, D_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

937

memset(vpu->ipi_desc, 0, sizeof(struct vpu_ipi_desc) * IPI_MAX);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

939

mutex_destroy(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

941

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

943

destroy_workqueue(vpu->wdt.wq);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

945

clk_unprepare(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

960

struct mtk_vpu *vpu = platform_get_drvdata(pdev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

965

if (vpu->wdt.wq)

drivers/media/platform/mediatek/vpu/mtk_vpu.c

966

destroy_workqueue(vpu->wdt.wq);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

967

vpu_free_ext_mem(vpu, P_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

968

vpu_free_ext_mem(vpu, D_FW);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

969

mutex_destroy(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

970

clk_unprepare(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

975

struct mtk_vpu *vpu = dev_get_drvdata(dev);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

979

ret = vpu_clock_enable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

985

if (!vpu_running(vpu)) {

drivers/media/platform/mediatek/vpu/mtk_vpu.c

986

vpu_clock_disable(vpu);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

987

clk_unprepare(vpu->clk);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

991

mutex_lock(&vpu->vpu_mutex);

drivers/media/platform/mediatek/vpu/mtk_vpu.c

993

vpu_cfg_writel(vpu, vpu_cfg_readl(vpu, VPU_INT_STATUS) | VPU_IDLE_STATE,

drivers/media/platform/verisilicon/hantro.h

393

static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro.h

397

writel_relaxed(val, vpu->enc_base + reg);

drivers/media/platform/verisilicon/hantro.h

400

static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)

drivers/media/platform/verisilicon/hantro.h

403

writel(val, vpu->enc_base + reg);

drivers/media/platform/verisilicon/hantro.h

406

static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)

drivers/media/platform/verisilicon/hantro.h

408

u32 val = readl(vpu->enc_base + reg);

drivers/media/platform/verisilicon/hantro.h

414

static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro.h

418

writel_relaxed(val, vpu->dec_base + reg);

drivers/media/platform/verisilicon/hantro.h

421

static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)

drivers/media/platform/verisilicon/hantro.h

424

writel(val, vpu->dec_base + reg);

drivers/media/platform/verisilicon/hantro.h

427

static __always_inline void hantro_write_addr(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro.h

431

vdpu_write(vpu, addr & 0xffffffff, offset);

drivers/media/platform/verisilicon/hantro.h

434

static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)

drivers/media/platform/verisilicon/hantro.h

436

u32 val = readl(vpu->dec_base + reg);

drivers/media/platform/verisilicon/hantro.h

442

static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro.h

448

v = vdpu_read(vpu, reg->base);

drivers/media/platform/verisilicon/hantro.h

454

static __always_inline void hantro_reg_write(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro.h

458

vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);

drivers/media/platform/verisilicon/hantro.h

461

static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro.h

465

vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);

drivers/media/platform/verisilicon/hantro.h

94

int (*init)(struct hantro_dev *vpu);

drivers/media/platform/verisilicon/hantro.h

95

int (*runtime_resume)(struct hantro_dev *vpu);

drivers/media/platform/verisilicon/hantro_drv.c

100

void hantro_irq_done(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_drv.c

1005

static int hantro_disable_multicore(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/hantro_drv.c

1013

ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible);

drivers/media/platform/verisilicon/hantro_drv.c

1027

is_main_core = (vpu->dev->of_node == node);

drivers/media/platform/verisilicon/hantro_drv.c

1032

dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n");

drivers/media/platform/verisilicon/hantro_drv.c

1039

static struct v4l2_m2m_dev *hantro_get_v4l2_m2m_dev(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/hantro_drv.c

104

v4l2_m2m_get_curr_priv(vpu->m2m_dev);

drivers/media/platform/verisilicon/hantro_drv.c

1044

if (!vpu->variant || !vpu->variant->shared_devices)

drivers/media/platform/verisilicon/hantro_drv.c

1047

for_each_matching_node(node, vpu->variant->shared_devices) {

drivers/media/platform/verisilicon/hantro_drv.c

1056

if (IS_ERR_OR_NULL(shared_vpu) || shared_vpu == vpu) {

drivers/media/platform/verisilicon/hantro_drv.c

1077

struct hantro_dev *vpu;

drivers/media/platform/verisilicon/hantro_drv.c

1081

vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL);

drivers/media/platform/verisilicon/hantro_drv.c

1082

if (!vpu)

drivers/media/platform/verisilicon/hantro_drv.c

1085

vpu->dev = &pdev->dev;

drivers/media/platform/verisilicon/hantro_drv.c

1086

vpu->pdev = pdev;

drivers/media/platform/verisilicon/hantro_drv.c

1087

mutex_init(&vpu->vpu_mutex);

drivers/media/platform/verisilicon/hantro_drv.c

1088

spin_lock_init(&vpu->irqlock);

drivers/media/platform/verisilicon/hantro_drv.c

1091

vpu->variant = match->data;

drivers/media/platform/verisilicon/hantro_drv.c

1093

ret = hantro_disable_multicore(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1106

INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);

drivers/media/platform/verisilicon/hantro_drv.c

1108

vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,

drivers/media/platform/verisilicon/hantro_drv.c

1109

sizeof(*vpu->clocks), GFP_KERNEL);

drivers/media/platform/verisilicon/hantro_drv.c

111

if (cancel_delayed_work(&vpu->watchdog_work)) {

drivers/media/platform/verisilicon/hantro_drv.c

1110

if (!vpu->clocks)

drivers/media/platform/verisilicon/hantro_drv.c

1113

if (vpu->variant->num_clocks > 1) {

drivers/media/platform/verisilicon/hantro_drv.c

1114

for (i = 0; i < vpu->variant->num_clocks; i++)

drivers/media/platform/verisilicon/hantro_drv.c

1115

vpu->clocks[i].id = vpu->variant->clk_names[i];

drivers/media/platform/verisilicon/hantro_drv.c

1117

ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks,

drivers/media/platform/verisilicon/hantro_drv.c

1118

vpu->clocks);

drivers/media/platform/verisilicon/hantro_drv.c

1126

vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL);

drivers/media/platform/verisilicon/hantro_drv.c

1127

if (IS_ERR(vpu->clocks[0].clk))

drivers/media/platform/verisilicon/hantro_drv.c

1128

return PTR_ERR(vpu->clocks[0].clk);

drivers/media/platform/verisilicon/hantro_drv.c

1131

vpu->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);

drivers/media/platform/verisilicon/hantro_drv.c

1132

if (IS_ERR(vpu->resets))

drivers/media/platform/verisilicon/hantro_drv.c

1133

return PTR_ERR(vpu->resets);

drivers/media/platform/verisilicon/hantro_drv.c

1135

num_bases = vpu->variant->num_regs ?: 1;

drivers/media/platform/verisilicon/hantro_drv.c

1136

vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,

drivers/media/platform/verisilicon/hantro_drv.c

1137

sizeof(*vpu->reg_bases), GFP_KERNEL);

drivers/media/platform/verisilicon/hantro_drv.c

1138

if (!vpu->reg_bases)

drivers/media/platform/verisilicon/hantro_drv.c

114

hantro_job_finish(vpu, ctx, result);

drivers/media/platform/verisilicon/hantro_drv.c

1142

vpu->reg_bases[i] = vpu->variant->reg_names ?

drivers/media/platform/verisilicon/hantro_drv.c

1143

devm_platform_ioremap_resource_byname(pdev, vpu->variant->reg_names[i]) :

drivers/media/platform/verisilicon/hantro_drv.c

1145

if (IS_ERR(vpu->reg_bases[i]))

drivers/media/platform/verisilicon/hantro_drv.c

1146

return PTR_ERR(vpu->reg_bases[i]);

drivers/media/platform/verisilicon/hantro_drv.c

1148

vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;

drivers/media/platform/verisilicon/hantro_drv.c

1149

vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;

drivers/media/platform/verisilicon/hantro_drv.c

1156

ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));

drivers/media/platform/verisilicon/hantro_drv.c

1158

dev_err(vpu->dev, "Could not set DMA coherent mask.\n");

drivers/media/platform/verisilicon/hantro_drv.c

1163

for (i = 0; i < vpu->variant->num_irqs; i++) {

drivers/media/platform/verisilicon/hantro_drv.c

1167

if (!vpu->variant->irqs[i].handler)

drivers/media/platform/verisilicon/hantro_drv.c

1170

if (vpu->variant->num_irqs > 1) {

drivers/media/platform/verisilicon/hantro_drv.c

1171

irq_name = vpu->variant->irqs[i].name;

drivers/media/platform/verisilicon/hantro_drv.c

1172

irq = platform_get_irq_byname(vpu->pdev, irq_name);

drivers/media/platform/verisilicon/hantro_drv.c

1179

irq = platform_get_irq(vpu->pdev, 0);

drivers/media/platform/verisilicon/hantro_drv.c

1184

ret = devm_request_irq(vpu->dev, irq,

drivers/media/platform/verisilicon/hantro_drv.c

1185

vpu->variant->irqs[i].handler, 0,

drivers/media/platform/verisilicon/hantro_drv.c

1186

dev_name(vpu->dev), vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1188

dev_err(vpu->dev, "Could not request %s IRQ.\n",

drivers/media/platform/verisilicon/hantro_drv.c

1194

if (vpu->variant->init) {

drivers/media/platform/verisilicon/hantro_drv.c

1195

ret = vpu->variant->init(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

120

struct hantro_dev *vpu;

drivers/media/platform/verisilicon/hantro_drv.c

1202

pm_runtime_set_autosuspend_delay(vpu->dev, 100);

drivers/media/platform/verisilicon/hantro_drv.c

1203

pm_runtime_use_autosuspend(vpu->dev);

drivers/media/platform/verisilicon/hantro_drv.c

1204

pm_runtime_enable(vpu->dev);

drivers/media/platform/verisilicon/hantro_drv.c

1206

ret = reset_control_deassert(vpu->resets);

drivers/media/platform/verisilicon/hantro_drv.c

1212

ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);

drivers/media/platform/verisilicon/hantro_drv.c

1218

ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);

drivers/media/platform/verisilicon/hantro_drv.c

1223

platform_set_drvdata(pdev, vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1225

vpu->m2m_dev = hantro_get_v4l2_m2m_dev(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1226

if (IS_ERR(vpu->m2m_dev)) {

drivers/media/platform/verisilicon/hantro_drv.c

1227

v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n");

drivers/media/platform/verisilicon/hantro_drv.c

1228

ret = PTR_ERR(vpu->m2m_dev);

drivers/media/platform/verisilicon/hantro_drv.c

123

vpu = container_of(to_delayed_work(work),

drivers/media/platform/verisilicon/hantro_drv.c

1232

vpu->mdev.dev = vpu->dev;

drivers/media/platform/verisilicon/hantro_drv.c

1233

strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model));

drivers/media/platform/verisilicon/hantro_drv.c

1234

media_device_init(&vpu->mdev);

drivers/media/platform/verisilicon/hantro_drv.c

1235

vpu->mdev.ops = &hantro_m2m_media_ops;

drivers/media/platform/verisilicon/hantro_drv.c

1236

vpu->v4l2_dev.mdev = &vpu->mdev;

drivers/media/platform/verisilicon/hantro_drv.c

1238

ret = hantro_add_enc_func(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1244

ret = hantro_add_dec_func(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

125

ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev);

drivers/media/platform/verisilicon/hantro_drv.c

1250

ret = media_device_register(&vpu->mdev);

drivers/media/platform/verisilicon/hantro_drv.c

1252

v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n");

drivers/media/platform/verisilicon/hantro_drv.c

1259

hantro_remove_dec_func(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1261

hantro_remove_enc_func(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1263

media_device_cleanup(&vpu->mdev);

drivers/media/platform/verisilicon/hantro_drv.c

1264

v4l2_m2m_put(vpu->m2m_dev);

drivers/media/platform/verisilicon/hantro_drv.c

1266

v4l2_device_unregister(&vpu->v4l2_dev);

drivers/media/platform/verisilicon/hantro_drv.c

1268

clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);

drivers/media/platform/verisilicon/hantro_drv.c

1270

reset_control_assert(vpu->resets);

drivers/media/platform/verisilicon/hantro_drv.c

1272

pm_runtime_dont_use_autosuspend(vpu->dev);

drivers/media/platform/verisilicon/hantro_drv.c

1273

pm_runtime_disable(vpu->dev);

drivers/media/platform/verisilicon/hantro_drv.c

1279

struct hantro_dev *vpu = platform_get_drvdata(pdev);

drivers/media/platform/verisilicon/hantro_drv.c

1281

v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name);

drivers/media/platform/verisilicon/hantro_drv.c

1283

media_device_unregister(&vpu->mdev);

drivers/media/platform/verisilicon/hantro_drv.c

1284

hantro_remove_dec_func(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1285

hantro_remove_enc_func(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

1286

media_device_cleanup(&vpu->mdev);

drivers/media/platform/verisilicon/hantro_drv.c

1287

v4l2_m2m_put(vpu->m2m_dev);

drivers/media/platform/verisilicon/hantro_drv.c

1288

v4l2_device_unregister(&vpu->v4l2_dev);

drivers/media/platform/verisilicon/hantro_drv.c

1289

clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);

drivers/media/platform/verisilicon/hantro_drv.c

1290

reset_control_assert(vpu->resets);

drivers/media/platform/verisilicon/hantro_drv.c

1291

pm_runtime_dont_use_autosuspend(vpu->dev);

drivers/media/platform/verisilicon/hantro_drv.c

1292

pm_runtime_disable(vpu->dev);

drivers/media/platform/verisilicon/hantro_drv.c

1298

struct hantro_dev *vpu = dev_get_drvdata(dev);

drivers/media/platform/verisilicon/hantro_drv.c

130

hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR);

drivers/media/platform/verisilicon/hantro_drv.c

1300

if (vpu->variant->runtime_resume)

drivers/media/platform/verisilicon/hantro_drv.c

1301

return vpu->variant->runtime_resume(vpu);

drivers/media/platform/verisilicon/hantro_drv.c

597

static int hantro_ctrls_setup(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_drv.c

62

static void hantro_job_finish_no_pm(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_drv.c

628

struct hantro_dev *vpu = video_drvdata(filp);

drivers/media/platform/verisilicon/hantro_drv.c

647

ctx->dev = vpu;

drivers/media/platform/verisilicon/hantro_drv.c

649

allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS;

drivers/media/platform/verisilicon/hantro_drv.c

652

allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;

drivers/media/platform/verisilicon/hantro_drv.c

659

ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init);

drivers/media/platform/verisilicon/hantro_drv.c

670

ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs);

drivers/media/platform/verisilicon/hantro_drv.c

780

static int hantro_attach_func(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_drv.c

783

struct media_device *mdev = &vpu->mdev;

drivers/media/platform/verisilicon/hantro_drv.c

883

static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)

drivers/media/platform/verisilicon/hantro_drv.c

89

static void hantro_job_finish(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_drv.c

890

match = of_match_node(of_hantro_match, vpu->dev->of_node);

drivers/media/platform/verisilicon/hantro_drv.c

891

func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL);

drivers/media/platform/verisilicon/hantro_drv.c

893

v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n");

drivers/media/platform/verisilicon/hantro_drv.c

902

vfd->lock = &vpu->vpu_mutex;

drivers/media/platform/verisilicon/hantro_drv.c

903

vfd->v4l2_dev = &vpu->v4l2_dev;

drivers/media/platform/verisilicon/hantro_drv.c

912

vpu->encoder = func;

drivers/media/platform/verisilicon/hantro_drv.c

916

vpu->decoder = func;

drivers/media/platform/verisilicon/hantro_drv.c

923

video_set_drvdata(vfd, vpu);

drivers/media/platform/verisilicon/hantro_drv.c

927

v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n");

drivers/media/platform/verisilicon/hantro_drv.c

93

pm_runtime_put_autosuspend(vpu->dev);

drivers/media/platform/verisilicon/hantro_drv.c

931

ret = hantro_attach_func(vpu, func);

drivers/media/platform/verisilicon/hantro_drv.c

933

v4l2_err(&vpu->v4l2_dev,

drivers/media/platform/verisilicon/hantro_drv.c

938

v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name,

drivers/media/platform/verisilicon/hantro_drv.c

948

static int hantro_add_enc_func(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/hantro_drv.c

95

clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);

drivers/media/platform/verisilicon/hantro_drv.c

950

if (!vpu->variant->enc_fmts)

drivers/media/platform/verisilicon/hantro_drv.c

953

return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);

drivers/media/platform/verisilicon/hantro_drv.c

956

static int hantro_add_dec_func(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/hantro_drv.c

958

if (!vpu->variant->dec_fmts)

drivers/media/platform/verisilicon/hantro_drv.c

961

return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);

drivers/media/platform/verisilicon/hantro_drv.c

964

static void hantro_remove_func(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_drv.c

97

hantro_job_finish_no_pm(vpu, ctx, result);

drivers/media/platform/verisilicon/hantro_drv.c

970

func = vpu->encoder;

drivers/media/platform/verisilicon/hantro_drv.c

972

func = vpu->decoder;

drivers/media/platform/verisilicon/hantro_drv.c

981

static void hantro_remove_enc_func(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/hantro_drv.c

983

hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);

drivers/media/platform/verisilicon/hantro_drv.c

986

static void hantro_remove_dec_func(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/hantro_drv.c

988

hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);

drivers/media/platform/verisilicon/hantro_g1.c

16

struct hantro_dev *vpu = dev_id;

drivers/media/platform/verisilicon/hantro_g1.c

20

status = vdpu_read(vpu, G1_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g1.c

24

vdpu_write(vpu, 0, G1_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g1.c

25

vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);

drivers/media/platform/verisilicon/hantro_g1.c

27

hantro_irq_done(vpu, state);

drivers/media/platform/verisilicon/hantro_g1.c

34

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1.c

36

vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g1.c

37

vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);

drivers/media/platform/verisilicon/hantro_g1.c

38

vdpu_write(vpu, 1, G1_REG_SOFT_RESET);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

100

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

107

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

110

vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

113

vdpu_write_relaxed(vpu,

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

120

vdpu_write_relaxed(vpu, 0, G1_REG_REF_BUF_CTRL);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

123

vdpu_write_relaxed(vpu, G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(8),

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

130

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

135

vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

136

vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

147

vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2));

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

166

vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++));

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

180

vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

194

vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++));

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

201

vdpu_write_relaxed(vpu, dma_addr, G1_REG_ADDR_REF(i));

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

209

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

215

vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

223

vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DST);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

243

vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DIR_MV);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

247

vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

252

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

270

vdpu_write_relaxed(vpu,

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

28

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

281

vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

49

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

55

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

65

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

71

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3);

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

85

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

111

vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

119

vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

133

vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

134

vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

136

vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

137

vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

139

vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

140

vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

144

vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER2_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

145

vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER3_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

150

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

181

vdpu_write_relaxed(vpu, reg, G1_SWREG(2));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

194

vdpu_write_relaxed(vpu, reg, G1_SWREG(3));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

200

vdpu_write_relaxed(vpu, reg, G1_SWREG(4));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

208

vdpu_write_relaxed(vpu, reg, G1_SWREG(5));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

212

vdpu_write_relaxed(vpu, reg, G1_SWREG(6));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

221

vdpu_write_relaxed(vpu, reg, G1_SWREG(18));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

225

vdpu_write_relaxed(vpu, reg, G1_SWREG(48));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

228

vdpu_write_relaxed(vpu, reg, G1_SWREG(55));

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

230

hantro_g1_mpeg2_dec_set_quantisation(vpu, ctx);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

231

hantro_g1_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

237

vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

81

hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

88

vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE);

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

92

hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx,

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

139

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

144

hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

150

hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

154

hantro_reg_write(vpu, &vp8_dec_lf_level[i],

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

161

vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0));

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

165

hantro_reg_write(vpu, &vp8_dec_mb_adj[i],

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

167

hantro_reg_write(vpu, &vp8_dec_ref_adj[i],

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

181

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

185

hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

191

hantro_reg_write(vpu, &vp8_dec_quant[i], quant);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

195

hantro_reg_write(vpu, &vp8_dec_quant[i],

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

199

hantro_reg_write(vpu, &vp8_dec_quant_delta[0], q->y_dc_delta);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

200

hantro_reg_write(vpu, &vp8_dec_quant_delta[1], q->y2_dc_delta);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

201

hantro_reg_write(vpu, &vp8_dec_quant_delta[2], q->y2_ac_delta);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

202

hantro_reg_write(vpu, &vp8_dec_quant_delta[3], q->uv_dc_delta);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

203

hantro_reg_write(vpu, &vp8_dec_quant_delta[4], q->uv_ac_delta);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

234

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

269

vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK))

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

276

hantro_reg_write(vpu, &reg, mb_start_bits);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

282

hantro_reg_write(vpu, &reg, mb_size + 1);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

303

hantro_reg_write(vpu, &reg, hdr->num_dct_parts - 1);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

306

vdpu_write_relaxed(vpu,

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

315

hantro_reg_write(vpu, &vp8_dec_dct_base[i],

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

318

hantro_reg_write(vpu, &vp8_dec_dct_start_bits[i],

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

332

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

348

hantro_reg_write(vpu, &vp8_dec_pred_bc_tap[i][j],

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

365

hantro_reg_write(vpu, &reg, val);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

373

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

383

vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0));

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

393

vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4));

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

403

vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(5));

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

411

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

416

vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma,

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

426

vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(0));

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

429

vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

435

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

464

vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

474

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

483

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

488

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

495

vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4);

drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c

508

vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g2.c

16

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2.c

19

status = vdpu_read(vpu, G2_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g2.c

35

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2.c

38

status = vdpu_read(vpu, G2_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g2.c

40

dev_warn_ratelimited(vpu->dev, "device still running, aborting");

drivers/media/platform/verisilicon/hantro_g2.c

42

vdpu_write(vpu, status, G2_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g2.c

52

struct hantro_dev *vpu = dev_id;

drivers/media/platform/verisilicon/hantro_g2.c

55

status = vdpu_read(vpu, G2_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g2.c

60

hantro_reg_write(vpu, &g2_dec_irq, 0);

drivers/media/platform/verisilicon/hantro_g2.c

61

hantro_reg_write(vpu, &g2_dec_int_stat, 0);

drivers/media/platform/verisilicon/hantro_g2.c

62

hantro_reg_write(vpu, &g2_clk_gate_e, 1);

drivers/media/platform/verisilicon/hantro_g2.c

65

hantro_irq_done(vpu, VB2_BUF_STATE_DONE);

drivers/media/platform/verisilicon/hantro_g2.c

71

dev_warn_ratelimited(vpu->dev, "decode operation aborted.");

drivers/media/platform/verisilicon/hantro_g2.c

76

dev_warn_ratelimited(vpu->dev, "not all macroblocks were decoded.");

drivers/media/platform/verisilicon/hantro_g2.c

79

dev_warn_ratelimited(vpu->dev, "bus error detected.");

drivers/media/platform/verisilicon/hantro_g2.c

82

dev_warn_ratelimited(vpu->dev, "decode error detected.");

drivers/media/platform/verisilicon/hantro_g2.c

85

dev_warn_ratelimited(vpu->dev, "frame decode timed out.");

drivers/media/platform/verisilicon/hantro_g2.c

94

hantro_irq_done(vpu, VB2_BUF_STATE_ERROR);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

13

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

147

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

153

hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

154

hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

156

hantro_reg_write(vpu, &g2_hdr_skip_length, compute_header_skip_length(ctx));

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

161

hantro_reg_write(vpu, &g2_min_cb_size, min_log2_cb_size);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

162

hantro_reg_write(vpu, &g2_max_cb_size, max_log2_ctb_size);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

175

hantro_reg_write(vpu, &g2_partial_ctb_x, partial_ctb_x);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

176

hantro_reg_write(vpu, &g2_partial_ctb_y, partial_ctb_y);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

178

hantro_reg_write(vpu, &g2_pic_width_in_cbs, pic_width_in_min_cbs);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

179

hantro_reg_write(vpu, &g2_pic_height_in_cbs, pic_height_in_min_cbs);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

181

hantro_reg_write(vpu, &g2_pic_width_4x4,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

183

hantro_reg_write(vpu, &g2_pic_height_4x4,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

186

hantro_reg_write(vpu, &hevc_max_inter_hierdepth,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

188

hantro_reg_write(vpu, &hevc_max_intra_hierdepth,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

190

hantro_reg_write(vpu, &hevc_min_trb_size,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

192

hantro_reg_write(vpu, &hevc_max_trb_size,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

196

hantro_reg_write(vpu, &g2_tempor_mvp_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

199

hantro_reg_write(vpu, &g2_strong_smooth_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

201

hantro_reg_write(vpu, &g2_asym_pred_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

203

hantro_reg_write(vpu, &g2_sao_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

205

hantro_reg_write(vpu, &g2_sign_data_hide,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

209

hantro_reg_write(vpu, &g2_cu_qpd_e, 1);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

210

hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

212

hantro_reg_write(vpu, &g2_cu_qpd_e, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

213

hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

216

hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

217

hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

219

hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

220

hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

221

hantro_reg_write(vpu, &g2_slice_hdr_ext_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

223

hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

224

hantro_reg_write(vpu, &g2_slice_chqp_present,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

226

hantro_reg_write(vpu, &g2_weight_bipr_idc,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

228

hantro_reg_write(vpu, &g2_transq_bypass,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

230

hantro_reg_write(vpu, &g2_list_mod_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

232

hantro_reg_write(vpu, &g2_entropy_sync_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

234

hantro_reg_write(vpu, &g2_cabac_init_present,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

236

hantro_reg_write(vpu, &g2_idr_pic_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

238

hantro_reg_write(vpu, &hevc_parallel_merge,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

240

hantro_reg_write(vpu, &g2_pcm_filt_d,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

242

hantro_reg_write(vpu, &g2_pcm_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

245

hantro_reg_write(vpu, &g2_max_pcm_size,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

248

hantro_reg_write(vpu, &g2_min_pcm_size,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

250

hantro_reg_write(vpu, &g2_bit_depth_pcm_y,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

252

hantro_reg_write(vpu, &g2_bit_depth_pcm_c,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

255

hantro_reg_write(vpu, &g2_max_pcm_size, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

256

hantro_reg_write(vpu, &g2_min_pcm_size, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

257

hantro_reg_write(vpu, &g2_bit_depth_pcm_y, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

258

hantro_reg_write(vpu, &g2_bit_depth_pcm_c, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

261

hantro_reg_write(vpu, &g2_start_code_e, 1);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

262

hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

263

hantro_reg_write(vpu, &g2_weight_pred_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

265

hantro_reg_write(vpu, &g2_cabac_init_present,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

267

hantro_reg_write(vpu, &g2_const_intra_e,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

269

hantro_reg_write(vpu, &g2_transform_skip,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

271

hantro_reg_write(vpu, &g2_out_filtering_dis,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

273

hantro_reg_write(vpu, &g2_filt_ctrl_pres,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

275

hantro_reg_write(vpu, &g2_dependent_slice,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

277

hantro_reg_write(vpu, &g2_filter_override,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

279

hantro_reg_write(vpu, &g2_refidx0_active,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

28

hantro_reg_write(vpu, &g2_tile_e, tiles_enabled);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

281

hantro_reg_write(vpu, &g2_refidx1_active,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

283

hantro_reg_write(vpu, &g2_apf_threshold, 8);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

298

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

367

hantro_reg_write(vpu, &ref_pic_regs0[i],

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

369

hantro_reg_write(vpu, &ref_pic_regs1[i],

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

382

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

419

hantro_reg_write(vpu, &g2_num_ref_frames, max_ref_frames);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

420

hantro_reg_write(vpu, &g2_filter_over_slices,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

422

hantro_reg_write(vpu, &g2_filter_over_tiles,

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

431

hantro_reg_write(vpu, &cur_poc[i], poc_diff);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

439

hantro_reg_write(vpu, &cur_poc[i], 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

445

hantro_reg_write(vpu, &cur_poc[i], decode_params->pic_order_cnt_val);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

46

hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

468

hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

469

hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

47

hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

470

hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

471

hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), compress_luma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

472

hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i), compress_chroma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

489

hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

490

hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

491

hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

492

hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), compress_luma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

493

hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i++), compress_chroma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

495

hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

496

hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

497

hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

498

hantro_write_addr(vpu, G2_OUT_COMP_LUMA_ADDR, compress_luma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

499

hantro_write_addr(vpu, G2_OUT_COMP_CHROMA_ADDR, compress_chroma_addr);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

502

hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

503

hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

504

hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

505

hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

506

hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i), 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

509

hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

517

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

528

hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

529

hantro_reg_write(vpu, &g2_stream_len, src_len);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

530

hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

531

hantro_reg_write(vpu, &g2_strm_start_offset, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

532

hantro_reg_write(vpu, &g2_start_bit, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

533

hantro_reg_write(vpu, &g2_write_mvs_e, 1);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

535

hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

536

hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

537

hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

538

hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

543

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

552

hantro_reg_write(vpu, &g2_scaling_list_e, scaling_list_enabled);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

588

hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

593

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

616

hantro_reg_write(vpu, &g2_mode, HEVC_DEC_MODE);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

617

hantro_reg_write(vpu, &g2_clk_gate_e, 1);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

620

hantro_reg_write(vpu, &g2_out_dis, 0);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

622

hantro_reg_write(vpu, &g2_ref_compress_bypass, !ctx->hevc_dec.use_compression);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

625

hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

626

hantro_reg_write(vpu, &g2_max_burst, 16);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

629

hantro_reg_write(vpu, &g2_strm_swap, 0xf);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

630

hantro_reg_write(vpu, &g2_dirmv_swap, 0xf);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

631

hantro_reg_write(vpu, &g2_compress_swap, 0xf);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

634

vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

94

hantro_reg_write(vpu, &g2_num_tile_rows, 1);

drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c

95

hantro_reg_write(vpu, &g2_num_tile_cols, 1);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

102

vepu_write_relaxed(vpu, reg, H1_REG_JPEG_CHROMA_QUAT(i));

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

108

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

126

vepu_write_relaxed(vpu, H1_REG_ENC_CTRL_ENC_MODE_JPEG,

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

129

hantro_h1_set_src_img_ctrl(vpu, ctx);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

130

hantro_h1_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf,

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

132

hantro_h1_jpeg_enc_set_qtable(vpu, jpeg_ctx.hw_luma_qtable,

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

143

vepu_write(vpu, reg, H1_REG_AXI_CTRL);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

153

vepu_write(vpu, reg, H1_REG_ENC_CTRL);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

160

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

161

u32 bytesused = vepu_read(vpu, H1_REG_STR_BUF_LIMIT) / 8;

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

18

static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

37

vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

40

static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

55

vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) +

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

58

vepu_write_relaxed(vpu, size_left, H1_REG_STR_BUF_LIMIT);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

63

vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

67

vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

68

vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

73

vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

74

vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

75

vepu_write_relaxed(vpu, src[2], H1_REG_ADDR_IN_PLANE_2);

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

80

hantro_h1_jpeg_enc_set_qtable(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_h1_jpeg_enc.c

97

vepu_write_relaxed(vpu, reg, H1_REG_JPEG_LUMA_QUAT(i));

drivers/media/platform/verisilicon/hantro_h264.c

497

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_h264.c

501

dma_free_coherent(vpu->dev, priv->size, priv->cpu, priv->dma);

drivers/media/platform/verisilicon/hantro_h264.c

506

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_h264.c

511

priv->cpu = dma_alloc_coherent(vpu->dev, sizeof(*tbl), &priv->dma,

drivers/media/platform/verisilicon/hantro_hevc.c

106

dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,

drivers/media/platform/verisilicon/hantro_hevc.c

113

hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/hantro_hevc.c

121

hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/hantro_hevc.c

129

hevc_dec->tile_bsd.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/hantro_hevc.c

142

dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,

drivers/media/platform/verisilicon/hantro_hevc.c

149

dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,

drivers/media/platform/verisilicon/hantro_hevc.c

217

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_hevc.c

221

dma_free_coherent(vpu->dev, hevc_dec->tile_sizes.size,

drivers/media/platform/verisilicon/hantro_hevc.c

227

dma_free_coherent(vpu->dev, hevc_dec->scaling_lists.size,

drivers/media/platform/verisilicon/hantro_hevc.c

233

dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,

drivers/media/platform/verisilicon/hantro_hevc.c

239

dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,

drivers/media/platform/verisilicon/hantro_hevc.c

245

dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,

drivers/media/platform/verisilicon/hantro_hevc.c

253

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_hevc.c

265

hevc_dec->tile_sizes.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/hantro_hevc.c

273

hevc_dec->scaling_lists.cpu = dma_alloc_coherent(vpu->dev, SCALING_LIST_SIZE,

drivers/media/platform/verisilicon/hantro_hevc.c

77

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_hevc.c

92

dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,

drivers/media/platform/verisilicon/hantro_hevc.c

99

dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,

drivers/media/platform/verisilicon/hantro_hw.h

431

void hantro_irq_done(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/hantro_hw.h

585

void hantro_g2_check_idle(struct hantro_dev *vpu);

drivers/media/platform/verisilicon/hantro_mpeg2.c

40

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_mpeg2.c

44

dma_alloc_coherent(vpu->dev,

drivers/media/platform/verisilicon/hantro_mpeg2.c

55

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_mpeg2.c

57

dma_free_coherent(vpu->dev,

drivers/media/platform/verisilicon/hantro_postproc.c

100

HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width));

drivers/media/platform/verisilicon/hantro_postproc.c

101

HANTRO_PP_REG_WRITE(vpu, input_height, MB_HEIGHT(ctx->dst_fmt.height));

drivers/media/platform/verisilicon/hantro_postproc.c

102

HANTRO_PP_REG_WRITE(vpu, input_fmt, src_pp_fmt);

drivers/media/platform/verisilicon/hantro_postproc.c

103

HANTRO_PP_REG_WRITE(vpu, output_fmt, dst_pp_fmt);

drivers/media/platform/verisilicon/hantro_postproc.c

104

HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width);

drivers/media/platform/verisilicon/hantro_postproc.c

105

HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height);

drivers/media/platform/verisilicon/hantro_postproc.c

106

HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));

drivers/media/platform/verisilicon/hantro_postproc.c

107

HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);

drivers/media/platform/verisilicon/hantro_postproc.c

108

HANTRO_PP_REG_WRITE(vpu, input_width_ext, MB_WIDTH(ctx->dst_fmt.width) >> 9);

drivers/media/platform/verisilicon/hantro_postproc.c

109

HANTRO_PP_REG_WRITE(vpu, input_height_ext, MB_HEIGHT(ctx->dst_fmt.height >> 8));

drivers/media/platform/verisilicon/hantro_postproc.c

122

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

135

hantro_reg_write(vpu, &g2_down_scale_e, 1);

drivers/media/platform/verisilicon/hantro_postproc.c

136

hantro_reg_write(vpu, &g2_down_scale_y, down_scale >> 2);

drivers/media/platform/verisilicon/hantro_postproc.c

137

hantro_reg_write(vpu, &g2_down_scale_x, down_scale >> 2);

drivers/media/platform/verisilicon/hantro_postproc.c

138

hantro_write_addr(vpu, G2_DS_DST, dst_dma);

drivers/media/platform/verisilicon/hantro_postproc.c

139

hantro_write_addr(vpu, G2_DS_DST_CHR, dst_dma + (chroma_offset >> down_scale));

drivers/media/platform/verisilicon/hantro_postproc.c

141

hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);

drivers/media/platform/verisilicon/hantro_postproc.c

142

hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset);

drivers/media/platform/verisilicon/hantro_postproc.c

155

hantro_reg_write(vpu, &g2_output_8_bits, out_depth > 8 ? 0 : 1);

drivers/media/platform/verisilicon/hantro_postproc.c

156

hantro_reg_write(vpu, &g2_output_format, out_depth > 8 ? 1 : 0);

drivers/media/platform/verisilicon/hantro_postproc.c

158

hantro_reg_write(vpu, &g2_out_rs_e, 1);

drivers/media/platform/verisilicon/hantro_postproc.c

17

#define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \

drivers/media/platform/verisilicon/hantro_postproc.c

183

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

19

hantro_reg_write(vpu, \

drivers/media/platform/verisilicon/hantro_postproc.c

192

dma_free_attrs(vpu->dev, priv->size, priv->cpu,

drivers/media/platform/verisilicon/hantro_postproc.c

226

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

238

priv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &priv->dma,

drivers/media/platform/verisilicon/hantro_postproc.c

24

#define HANTRO_PP_REG_WRITE_RELAXED(vpu, reg_name, val) \

drivers/media/platform/verisilicon/hantro_postproc.c

26

hantro_reg_write_relaxed(vpu, \

drivers/media/platform/verisilicon/hantro_postproc.c

271

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

276

dma_free_attrs(vpu->dev, priv->size, priv->cpu,

drivers/media/platform/verisilicon/hantro_postproc.c

296

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

298

HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x0);

drivers/media/platform/verisilicon/hantro_postproc.c

303

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

305

hantro_reg_write(vpu, &g2_out_rs_e, 0);

drivers/media/platform/verisilicon/hantro_postproc.c

310

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

312

if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable)

drivers/media/platform/verisilicon/hantro_postproc.c

313

vpu->variant->postproc_ops->disable(ctx);

drivers/media/platform/verisilicon/hantro_postproc.c

318

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

320

if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable)

drivers/media/platform/verisilicon/hantro_postproc.c

321

vpu->variant->postproc_ops->enable(ctx);

drivers/media/platform/verisilicon/hantro_postproc.c

327

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

329

if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enum_framesizes)

drivers/media/platform/verisilicon/hantro_postproc.c

330

return vpu->variant->postproc_ops->enum_framesizes(ctx, fsize);

drivers/media/platform/verisilicon/hantro_postproc.c

71

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_postproc.c

77

HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x1);

drivers/media/platform/verisilicon/hantro_postproc.c

95

HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);

drivers/media/platform/verisilicon/hantro_postproc.c

96

HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1);

drivers/media/platform/verisilicon/hantro_postproc.c

97

HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1);

drivers/media/platform/verisilicon/hantro_postproc.c

98

HANTRO_PP_REG_WRITE(vpu, max_burst, 16);

drivers/media/platform/verisilicon/hantro_postproc.c

99

HANTRO_PP_REG_WRITE(vpu, out_luma_base, dst_dma);

drivers/media/platform/verisilicon/hantro_v4l2.c

177

struct hantro_dev *vpu = video_drvdata(file);

drivers/media/platform/verisilicon/hantro_v4l2.c

180

strscpy(cap->driver, vpu->dev->driver->name, sizeof(cap->driver));

drivers/media/platform/verisilicon/hantro_v4l2.c

64

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_v4l2.c

66

if (ctx->is_encoder || !vpu->variant->postproc_fmts) {

drivers/media/platform/verisilicon/hantro_vp8.c

147

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_vp8.c

164

aux_buf->cpu = dma_alloc_coherent(vpu->dev, aux_buf->size,

drivers/media/platform/verisilicon/hantro_vp8.c

175

aux_buf->cpu = dma_alloc_coherent(vpu->dev, aux_buf->size,

drivers/media/platform/verisilicon/hantro_vp8.c

185

dma_free_coherent(vpu->dev, ctx->vp8_dec.segment_map.size,

drivers/media/platform/verisilicon/hantro_vp8.c

195

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_vp8.c

197

dma_free_coherent(vpu->dev, vp8_dec->segment_map.size,

drivers/media/platform/verisilicon/hantro_vp8.c

199

dma_free_coherent(vpu->dev, vp8_dec->prob_tbl.size,

drivers/media/platform/verisilicon/hantro_vp9.c

160

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_vp9.c

161

const struct hantro_variant *variant = vpu->variant;

drivers/media/platform/verisilicon/hantro_vp9.c

178

max_width = vpu->variant->dec_fmts[i].frmsize.max_width;

drivers/media/platform/verisilicon/hantro_vp9.c

179

max_height = vpu->variant->dec_fmts[i].frmsize.max_height;

drivers/media/platform/verisilicon/hantro_vp9.c

185

tile_edge->cpu = dma_alloc_coherent(vpu->dev, size, &tile_edge->dma, GFP_KERNEL);

drivers/media/platform/verisilicon/hantro_vp9.c

196

segment_map->cpu = dma_alloc_coherent(vpu->dev, size, &segment_map->dma, GFP_KERNEL);

drivers/media/platform/verisilicon/hantro_vp9.c

209

misc->cpu = dma_alloc_coherent(vpu->dev, size, &misc->dma, GFP_KERNEL);

drivers/media/platform/verisilicon/hantro_vp9.c

221

dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma);

drivers/media/platform/verisilicon/hantro_vp9.c

224

dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma);

drivers/media/platform/verisilicon/hantro_vp9.c

231

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/hantro_vp9.c

237

dma_free_coherent(vpu->dev, misc->size, misc->cpu, misc->dma);

drivers/media/platform/verisilicon/hantro_vp9.c

238

dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma);

drivers/media/platform/verisilicon/hantro_vp9.c

239

dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

237

static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

239

vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

246

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

248

imx8m_soft_reset(vpu, RESET_G1);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

28

static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits)

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

33

val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

35

writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

40

val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

42

writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

45

static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits)

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

49

val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

51

writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

54

static int imx8mq_runtime_resume(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

58

ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

60

dev_err(vpu->dev, "Failed to enable clocks\n");

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

64

imx8m_soft_reset(vpu, RESET_G1 | RESET_G2);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

65

imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

68

writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

69

writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

70

writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE);

drivers/media/platform/verisilicon/imx8m_vpu_hw.c

72

clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

199

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

207

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

211

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

216

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

219

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

227

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

233

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

248

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

253

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

256

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

259

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

265

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

269

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

275

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

279

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

285

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

296

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

302

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

316

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

324

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

328

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

332

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

336

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

340

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

344

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

348

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

352

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

356

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

364

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

372

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

378

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

386

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

394

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

400

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

406

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

409

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

412

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

418

vdpu_write_relaxed(vpu, dma_addr, VDPU_REG_REFER_BASE(i));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

426

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

432

vdpu_write_relaxed(vpu, src_dma, VDPU_REG_RLC_VLC_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

440

vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DEC_OUT_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

460

vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DIR_MV_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

464

vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

469

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

487

reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

488

vdpu_write(vpu, reg, VDPU_SWREG(57));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

100

vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

101

vepu_write_relaxed(vpu, src[2], VEPU_REG_ADDR_IN_PLANE_2);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

106

rockchip_vpu2_jpeg_enc_set_qtable(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

123

vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

128

vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_CHROMA_QUAT(i));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

134

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

155

vepu_write_relaxed(vpu, VEPU_REG_ENCODE_FORMAT_JPEG,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

158

rockchip_vpu2_set_src_img_ctrl(vpu, ctx);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

159

rockchip_vpu2_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

161

rockchip_vpu2_jpeg_enc_set_qtable(vpu, jpeg_ctx.hw_luma_qtable,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

171

vepu_write(vpu, reg, VEPU_REG_DATA_ENDIAN);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

174

vepu_write_relaxed(vpu, reg, VEPU_REG_AXI_CTRL);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

184

vepu_write(vpu, reg, VEPU_REG_ENCODE_START);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

191

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

192

u32 bytesused = vepu_read(vpu, VEPU_REG_STR_BUF_LIMIT) / 8;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

35

static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

51

vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

61

vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

64

vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

67

static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

82

vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) +

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

85

vepu_write_relaxed(vpu, size_left, VEPU_REG_STR_BUF_LIMIT);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

89

vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

93

vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

94

vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_jpeg_enc.c

99

vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

114

vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

122

vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

136

vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

137

vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

139

vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

140

vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

142

vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

143

vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

147

vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER2_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

148

vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

153

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

173

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

177

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

182

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

185

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

193

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

199

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

211

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

217

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

225

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

234

vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

236

rockchip_vpu2_mpeg2_dec_set_quantisation(vpu, ctx);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

238

rockchip_vpu2_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

244

reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

245

vdpu_write(vpu, reg, VDPU_SWREG(57));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

83

rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

90

vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

94

rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

280

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

285

hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

291

hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

295

hantro_reg_write(vpu, &vp8_dec_lf_level[i],

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

302

vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

306

hantro_reg_write(vpu, &vp8_dec_mb_adj[i],

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

308

hantro_reg_write(vpu, &vp8_dec_ref_adj[i],

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

319

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

323

hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

329

hantro_reg_write(vpu, &vp8_dec_quant[i], quant);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

333

hantro_reg_write(vpu, &vp8_dec_quant[i],

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

337

hantro_reg_write(vpu, &vp8_dec_quant_delta[0], q->y_dc_delta);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

338

hantro_reg_write(vpu, &vp8_dec_quant_delta[1], q->y2_dc_delta);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

339

hantro_reg_write(vpu, &vp8_dec_quant_delta[2], q->y2_ac_delta);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

340

hantro_reg_write(vpu, &vp8_dec_quant_delta[3], q->uv_dc_delta);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

341

hantro_reg_write(vpu, &vp8_dec_quant_delta[4], q->uv_ac_delta);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

347

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

381

vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK)) +

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

383

hantro_reg_write(vpu, &vp8_dec_mb_start_bit, mb_start_bits);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

384

hantro_reg_write(vpu, &vp8_dec_mb_aligned_data_len, mb_size);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

402

hantro_reg_write(vpu, &vp8_dec_num_dct_partitions,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

406

hantro_reg_write(vpu, &vp8_dec_stream_len, dct_part_total_len);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

413

hantro_reg_write(vpu, &vp8_dec_dct_base[i],

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

416

hantro_reg_write(vpu, &vp8_dec_dct_start_bits[i],

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

430

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

439

hantro_reg_write(vpu,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

450

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

459

vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF0);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

469

vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(2));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

479

vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(3));

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

487

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

492

vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma,

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

502

vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_SEGMENT_VAL);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

506

vdpu_write_relaxed(vpu, dst_dma, VDPU_REG_ADDR_DST);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

512

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

545

vdpu_write_relaxed(vpu, reg, VDPU_REG_EN_FLAGS);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

553

vdpu_write_relaxed(vpu, reg, VDPU_REG_DATA_ENDIAN);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

556

vdpu_write_relaxed(vpu, reg, VDPU_REG_AXI_CTRL);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

559

vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_FORMAT);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

562

hantro_reg_write(vpu, &vp8_dec_skip_mode, 1);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

564

hantro_reg_write(vpu, &vp8_dec_filter_disable, 1);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

570

hantro_reg_write(vpu, &vp8_dec_mb_width, mb_width);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

571

hantro_reg_write(vpu, &vp8_dec_mb_height, mb_height);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

572

hantro_reg_write(vpu, &vp8_dec_mb_width_ext, mb_width >> 9);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

573

hantro_reg_write(vpu, &vp8_dec_mb_height_ext, mb_height >> 8);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

576

hantro_reg_write(vpu, &vp8_dec_bool_range, hdr->coder_state.range);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

577

hantro_reg_write(vpu, &vp8_dec_bool_value, hdr->coder_state.value);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

579

reg = vdpu_read(vpu, VDPU_REG_VP8_DCT_START_BIT);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

584

vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_DCT_START_BIT);

drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c

597

hantro_reg_write(vpu, &vp8_dec_start_dec, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1000

hantro_reg_write(vpu, &av1_filt_level_delta3_seg5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1002

hantro_reg_write(vpu, &av1_refpic_seg5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1004

hantro_reg_write(vpu, &av1_skip_seg5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1006

hantro_reg_write(vpu, &av1_global_mv_seg5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1009

hantro_reg_write(vpu, &av1_quant_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1011

hantro_reg_write(vpu, &av1_filt_level_delta0_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1013

hantro_reg_write(vpu, &av1_filt_level_delta1_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1015

hantro_reg_write(vpu, &av1_filt_level_delta2_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1017

hantro_reg_write(vpu, &av1_filt_level_delta3_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1019

hantro_reg_write(vpu, &av1_refpic_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1021

hantro_reg_write(vpu, &av1_skip_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1023

hantro_reg_write(vpu, &av1_global_mv_seg6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1026

hantro_reg_write(vpu, &av1_quant_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1028

hantro_reg_write(vpu, &av1_filt_level_delta0_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1030

hantro_reg_write(vpu, &av1_filt_level_delta1_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1032

hantro_reg_write(vpu, &av1_filt_level_delta2_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1034

hantro_reg_write(vpu, &av1_filt_level_delta3_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1036

hantro_reg_write(vpu, &av1_refpic_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1038

hantro_reg_write(vpu, &av1_skip_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1040

hantro_reg_write(vpu, &av1_global_mv_seg7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1080

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1082

hantro_reg_write(vpu, &av1_filtering_dis, filtering_dis);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1083

hantro_reg_write(vpu, &av1_filt_level_base_gt32, loop_filter->level[0] > 32);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1084

hantro_reg_write(vpu, &av1_filt_sharpness, loop_filter->sharpness);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1086

hantro_reg_write(vpu, &av1_filt_level0, loop_filter->level[0]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1087

hantro_reg_write(vpu, &av1_filt_level1, loop_filter->level[1]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1088

hantro_reg_write(vpu, &av1_filt_level2, loop_filter->level[2]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1089

hantro_reg_write(vpu, &av1_filt_level3, loop_filter->level[3]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1094

hantro_reg_write(vpu, &av1_filt_ref_adj_0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1096

hantro_reg_write(vpu, &av1_filt_ref_adj_1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1098

hantro_reg_write(vpu, &av1_filt_ref_adj_2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1100

hantro_reg_write(vpu, &av1_filt_ref_adj_3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1102

hantro_reg_write(vpu, &av1_filt_ref_adj_4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1104

hantro_reg_write(vpu, &av1_filt_ref_adj_5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1106

hantro_reg_write(vpu, &av1_filt_ref_adj_6,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1108

hantro_reg_write(vpu, &av1_filt_ref_adj_7,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1110

hantro_reg_write(vpu, &av1_filt_mb_adj_0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1112

hantro_reg_write(vpu, &av1_filt_mb_adj_1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1115

hantro_reg_write(vpu, &av1_filt_ref_adj_0, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1116

hantro_reg_write(vpu, &av1_filt_ref_adj_1, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1117

hantro_reg_write(vpu, &av1_filt_ref_adj_2, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1118

hantro_reg_write(vpu, &av1_filt_ref_adj_3, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1119

hantro_reg_write(vpu, &av1_filt_ref_adj_4, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1120

hantro_reg_write(vpu, &av1_filt_ref_adj_5, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1121

hantro_reg_write(vpu, &av1_filt_ref_adj_6, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1122

hantro_reg_write(vpu, &av1_filt_ref_adj_7, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1123

hantro_reg_write(vpu, &av1_filt_mb_adj_0, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1124

hantro_reg_write(vpu, &av1_filt_mb_adj_1, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1127

hantro_write_addr(vpu, AV1_DB_DATA_COL, av1_dec->db_data_col.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1128

hantro_write_addr(vpu, AV1_DB_CTRL_COL, av1_dec->db_ctrl_col.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1172

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1197

hantro_write_addr(vpu, AV1_PROP_TABLE_OUT, av1_dec->prob_tbl_out.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1198

hantro_write_addr(vpu, AV1_PROP_TABLE, av1_dec->prob_tbl.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1237

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1251

hantro_reg_write(vpu, &av1_apply_grain, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1254

hantro_reg_write(vpu, &av1_num_y_points_b, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1255

hantro_reg_write(vpu, &av1_num_cb_points_b, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1256

hantro_reg_write(vpu, &av1_num_cr_points_b, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1257

hantro_reg_write(vpu, &av1_scaling_shift, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1258

hantro_reg_write(vpu, &av1_cb_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1259

hantro_reg_write(vpu, &av1_cb_luma_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1260

hantro_reg_write(vpu, &av1_cb_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1261

hantro_reg_write(vpu, &av1_cr_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1262

hantro_reg_write(vpu, &av1_cr_luma_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1263

hantro_reg_write(vpu, &av1_cr_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1264

hantro_reg_write(vpu, &av1_overlap_flag, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1265

hantro_reg_write(vpu, &av1_clip_to_restricted_range, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1266

hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1267

hantro_reg_write(vpu, &av1_random_seed, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1268

hantro_write_addr(vpu, AV1_FILM_GRAIN, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1285

hantro_reg_write(vpu, &av1_apply_grain, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1287

hantro_reg_write(vpu, &av1_num_y_points_b,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1289

hantro_reg_write(vpu, &av1_num_cb_points_b,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1291

hantro_reg_write(vpu, &av1_num_cr_points_b,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1293

hantro_reg_write(vpu, &av1_scaling_shift,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1297

hantro_reg_write(vpu, &av1_cb_mult, film_grain->cb_mult - 128);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1298

hantro_reg_write(vpu, &av1_cb_luma_mult, film_grain->cb_luma_mult - 128);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1299

hantro_reg_write(vpu, &av1_cb_offset, film_grain->cb_offset - 256);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1300

hantro_reg_write(vpu, &av1_cr_mult, film_grain->cr_mult - 128);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1301

hantro_reg_write(vpu, &av1_cr_luma_mult, film_grain->cr_luma_mult - 128);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1302

hantro_reg_write(vpu, &av1_cr_offset, film_grain->cr_offset - 256);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1304

hantro_reg_write(vpu, &av1_cb_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1305

hantro_reg_write(vpu, &av1_cb_luma_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1306

hantro_reg_write(vpu, &av1_cb_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1307

hantro_reg_write(vpu, &av1_cr_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1308

hantro_reg_write(vpu, &av1_cr_luma_mult, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1309

hantro_reg_write(vpu, &av1_cr_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1312

hantro_reg_write(vpu, &av1_overlap_flag,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1314

hantro_reg_write(vpu, &av1_clip_to_restricted_range,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1316

hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, scaling_from_luma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1317

hantro_reg_write(vpu, &av1_random_seed, film_grain->grain_seed);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1385

hantro_write_addr(vpu, AV1_FILM_GRAIN, av1_dec->film_grain.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1402

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1416

hantro_reg_write(vpu, &av1_enable_cdef, enable_cdef);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1417

hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1418

hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1434

hantro_reg_write(vpu, &av1_cdef_luma_primary_strength,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1436

hantro_reg_write(vpu, &av1_cdef_luma_secondary_strength,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1438

hantro_reg_write(vpu, &av1_cdef_chroma_primary_strength,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1440

hantro_reg_write(vpu, &av1_cdef_chroma_secondary_strength,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1443

hantro_write_addr(vpu, AV1_CDEF_COL, av1_dec->cdef_col.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1453

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1472

hantro_reg_write(vpu, &av1_lr_type, lr_type);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1473

hantro_reg_write(vpu, &av1_lr_unit_size, lr_unit_size);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1474

hantro_write_addr(vpu, AV1_LR_COL, av1_dec->lr_col.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1482

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1553

hantro_reg_write(vpu, &av1_superres_pic_width, frame->upscaled_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1556

hantro_reg_write(vpu, &av1_scale_denom_minus9,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1559

hantro_reg_write(vpu, &av1_scale_denom_minus9, frame->superres_denom);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1561

hantro_reg_write(vpu, &av1_superres_luma_step, superres_luma_step);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1562

hantro_reg_write(vpu, &av1_superres_chroma_step, superres_chroma_step);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1563

hantro_reg_write(vpu, &av1_superres_luma_step_invra,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1565

hantro_reg_write(vpu, &av1_superres_chroma_step_invra,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1567

hantro_reg_write(vpu, &av1_superres_init_luma_subpel_x,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1569

hantro_reg_write(vpu, &av1_superres_init_chroma_subpel_x,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1571

hantro_reg_write(vpu, &av1_superres_is_scaled, superres_is_scaled);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1573

hantro_write_addr(vpu, AV1_SR_COL, av1_dec->sr_col.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1581

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1589

hantro_reg_write(vpu, &av1_pic_width_in_cbs, pic_width_in_cbs);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1590

hantro_reg_write(vpu, &av1_pic_height_in_cbs, pic_height_in_cbs);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1591

hantro_reg_write(vpu, &av1_pic_width_pad, pic_width_pad);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1592

hantro_reg_write(vpu, &av1_pic_height_pad, pic_height_pad);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1602

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1723

hantro_reg_write(vpu, &av1_use_temporal0_mvs, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1724

hantro_reg_write(vpu, &av1_use_temporal1_mvs, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1725

hantro_reg_write(vpu, &av1_use_temporal2_mvs, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1726

hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1728

hantro_reg_write(vpu, &av1_mf1_last_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1729

hantro_reg_write(vpu, &av1_mf1_last2_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1730

hantro_reg_write(vpu, &av1_mf1_last3_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1731

hantro_reg_write(vpu, &av1_mf1_golden_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1732

hantro_reg_write(vpu, &av1_mf1_bwdref_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1733

hantro_reg_write(vpu, &av1_mf1_altref2_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1734

hantro_reg_write(vpu, &av1_mf1_altref_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1744

hantro_reg_write(vpu, &av1_use_temporal0_mvs, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1747

hantro_reg_write(vpu, &av1_mf1_last_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1750

hantro_reg_write(vpu, &av1_mf1_last2_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1753

hantro_reg_write(vpu, &av1_mf1_last3_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1756

hantro_reg_write(vpu, &av1_mf1_golden_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1759

hantro_reg_write(vpu, &av1_mf1_bwdref_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1762

hantro_reg_write(vpu, &av1_mf1_altref2_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1765

hantro_reg_write(vpu, &av1_mf1_altref_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1768

hantro_reg_write(vpu, &av1_mf2_last_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1769

hantro_reg_write(vpu, &av1_mf2_last2_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1770

hantro_reg_write(vpu, &av1_mf2_last3_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1771

hantro_reg_write(vpu, &av1_mf2_golden_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1772

hantro_reg_write(vpu, &av1_mf2_bwdref_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1773

hantro_reg_write(vpu, &av1_mf2_altref2_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1774

hantro_reg_write(vpu, &av1_mf2_altref_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1784

hantro_reg_write(vpu, &av1_use_temporal1_mvs, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1787

hantro_reg_write(vpu, &av1_mf2_last_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1790

hantro_reg_write(vpu, &av1_mf2_last2_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1793

hantro_reg_write(vpu, &av1_mf2_last3_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1796

hantro_reg_write(vpu, &av1_mf2_golden_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1799

hantro_reg_write(vpu, &av1_mf2_bwdref_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1802

hantro_reg_write(vpu, &av1_mf2_altref2_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1805

hantro_reg_write(vpu, &av1_mf2_altref_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1808

hantro_reg_write(vpu, &av1_mf3_last_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1809

hantro_reg_write(vpu, &av1_mf3_last2_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1810

hantro_reg_write(vpu, &av1_mf3_last3_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1811

hantro_reg_write(vpu, &av1_mf3_golden_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1812

hantro_reg_write(vpu, &av1_mf3_bwdref_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1813

hantro_reg_write(vpu, &av1_mf3_altref2_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1814

hantro_reg_write(vpu, &av1_mf3_altref_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1824

hantro_reg_write(vpu, &av1_use_temporal2_mvs, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1827

hantro_reg_write(vpu, &av1_mf3_last_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1830

hantro_reg_write(vpu, &av1_mf3_last2_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1833

hantro_reg_write(vpu, &av1_mf3_last3_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1836

hantro_reg_write(vpu, &av1_mf3_golden_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1839

hantro_reg_write(vpu, &av1_mf3_bwdref_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1842

hantro_reg_write(vpu, &av1_mf3_altref2_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1845

hantro_reg_write(vpu, &av1_mf3_altref_offset, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1848

hantro_reg_write(vpu, &av1_cur_last_offset, cur_offset[0]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1849

hantro_reg_write(vpu, &av1_cur_last2_offset, cur_offset[1]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1850

hantro_reg_write(vpu, &av1_cur_last3_offset, cur_offset[2]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1851

hantro_reg_write(vpu, &av1_cur_golden_offset, cur_offset[3]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1852

hantro_reg_write(vpu, &av1_cur_bwdref_offset, cur_offset[4]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1853

hantro_reg_write(vpu, &av1_cur_altref2_offset, cur_offset[5]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1854

hantro_reg_write(vpu, &av1_cur_altref_offset, cur_offset[6]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1856

hantro_reg_write(vpu, &av1_cur_last_roffset, cur_roffset[0]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1857

hantro_reg_write(vpu, &av1_cur_last2_roffset, cur_roffset[1]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1858

hantro_reg_write(vpu, &av1_cur_last3_roffset, cur_roffset[2]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1859

hantro_reg_write(vpu, &av1_cur_golden_roffset, cur_roffset[3]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1860

hantro_reg_write(vpu, &av1_cur_bwdref_roffset, cur_roffset[4]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1861

hantro_reg_write(vpu, &av1_cur_altref2_roffset, cur_roffset[5]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1862

hantro_reg_write(vpu, &av1_cur_altref_roffset, cur_roffset[6]);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1864

hantro_reg_write(vpu, &av1_mf1_type, mf_types[0] - V4L2_AV1_REF_LAST_FRAME);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1865

hantro_reg_write(vpu, &av1_mf2_type, mf_types[1] - V4L2_AV1_REF_LAST_FRAME);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1866

hantro_reg_write(vpu, &av1_mf3_type, mf_types[2] - V4L2_AV1_REF_LAST_FRAME);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1877

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1899

hantro_reg_write(vpu, &av1_ref_frames, ref_frames);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1926

hantro_reg_write(vpu, &av1_ref_scaling_enable, scale_enable);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1928

hantro_reg_write(vpu, &av1_ref0_gm_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1930

hantro_reg_write(vpu, &av1_ref1_gm_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1932

hantro_reg_write(vpu, &av1_ref2_gm_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1934

hantro_reg_write(vpu, &av1_ref3_gm_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1936

hantro_reg_write(vpu, &av1_ref4_gm_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1938

hantro_reg_write(vpu, &av1_ref5_gm_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1940

hantro_reg_write(vpu, &av1_ref6_gm_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1962

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1967

hantro_reg_write(vpu, &av1_skip_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1969

hantro_reg_write(vpu, &av1_tempor_mvp_e,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1971

hantro_reg_write(vpu, &av1_delta_lf_res_log,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1973

hantro_reg_write(vpu, &av1_delta_lf_multi,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1976

hantro_reg_write(vpu, &av1_delta_lf_present,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1979

hantro_reg_write(vpu, &av1_disable_cdf_update,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1981

hantro_reg_write(vpu, &av1_allow_warp,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1983

hantro_reg_write(vpu, &av1_show_frame,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1985

hantro_reg_write(vpu, &av1_switchable_motion_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1987

hantro_reg_write(vpu, &av1_allow_masked_compound,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1990

hantro_reg_write(vpu, &av1_allow_interintra,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1993

hantro_reg_write(vpu, &av1_enable_intra_edge_filter,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1996

hantro_reg_write(vpu, &av1_allow_filter_intra,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

1998

hantro_reg_write(vpu, &av1_enable_jnt_comp,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2000

hantro_reg_write(vpu, &av1_enable_dual_filter,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2002

hantro_reg_write(vpu, &av1_reduced_tx_set_used,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2004

hantro_reg_write(vpu, &av1_allow_screen_content_tools,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2006

hantro_reg_write(vpu, &av1_allow_intrabc,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2010

hantro_reg_write(vpu, &av1_force_interger_mv, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2012

hantro_reg_write(vpu, &av1_force_interger_mv,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2015

hantro_reg_write(vpu, &av1_blackwhite_e, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2016

hantro_reg_write(vpu, &av1_delta_q_res_log, ctrls->frame->quantization.delta_q_res);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2017

hantro_reg_write(vpu, &av1_delta_q_present,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2021

hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type));

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2022

hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2023

hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2024

hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2026

hantro_reg_write(vpu, &av1_mcomp_filt_type, ctrls->frame->interpolation_filter);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2027

hantro_reg_write(vpu, &av1_high_prec_mv_e,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2029

hantro_reg_write(vpu, &av1_comp_pred_mode,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2033

hantro_reg_write(vpu, &av1_transform_mode, tx_mode);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2034

hantro_reg_write(vpu, &av1_max_cb_size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2037

hantro_reg_write(vpu, &av1_min_cb_size, 3);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2039

hantro_reg_write(vpu, &av1_comp_pred_fixed_ref, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2040

hantro_reg_write(vpu, &av1_comp_pred_var_ref0_av1, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2041

hantro_reg_write(vpu, &av1_comp_pred_var_ref1_av1, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2042

hantro_reg_write(vpu, &av1_filt_level_seg0, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2043

hantro_reg_write(vpu, &av1_filt_level_seg1, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2044

hantro_reg_write(vpu, &av1_filt_level_seg2, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2045

hantro_reg_write(vpu, &av1_filt_level_seg3, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2046

hantro_reg_write(vpu, &av1_filt_level_seg4, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2047

hantro_reg_write(vpu, &av1_filt_level_seg5, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2048

hantro_reg_write(vpu, &av1_filt_level_seg6, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2049

hantro_reg_write(vpu, &av1_filt_level_seg7, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2051

hantro_reg_write(vpu, &av1_qp_delta_y_dc_av1, ctrls->frame->quantization.delta_q_y_dc);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2052

hantro_reg_write(vpu, &av1_qp_delta_ch_dc_av1, ctrls->frame->quantization.delta_q_u_dc);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2053

hantro_reg_write(vpu, &av1_qp_delta_ch_ac_av1, ctrls->frame->quantization.delta_q_u_ac);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2055

hantro_reg_write(vpu, &av1_qmlevel_y, ctrls->frame->quantization.qm_y);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2056

hantro_reg_write(vpu, &av1_qmlevel_u, ctrls->frame->quantization.qm_u);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2057

hantro_reg_write(vpu, &av1_qmlevel_v, ctrls->frame->quantization.qm_v);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2059

hantro_reg_write(vpu, &av1_qmlevel_y, 0xff);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2060

hantro_reg_write(vpu, &av1_qmlevel_u, 0xff);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2061

hantro_reg_write(vpu, &av1_qmlevel_v, 0xff);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2064

hantro_reg_write(vpu, &av1_lossless_e, rockchip_vpu981_av1_dec_is_lossless(ctx));

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2065

hantro_reg_write(vpu, &av1_quant_delta_v_dc, ctrls->frame->quantization.delta_q_v_dc);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2066

hantro_reg_write(vpu, &av1_quant_delta_v_ac, ctrls->frame->quantization.delta_q_v_ac);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2068

hantro_reg_write(vpu, &av1_skip_ref0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2070

hantro_reg_write(vpu, &av1_skip_ref1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2073

hantro_write_addr(vpu, AV1_MC_SYNC_CURR, av1_dec->tile_buf.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2074

hantro_write_addr(vpu, AV1_MC_SYNC_LEFT, av1_dec->tile_buf.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2085

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2097

hantro_reg_write(vpu, &av1_strm_buffer_len, src_buf_len);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2098

hantro_reg_write(vpu, &av1_strm_start_bit, start_bit);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2099

hantro_reg_write(vpu, &av1_stream_len, src_len);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2100

hantro_reg_write(vpu, &av1_strm_start_offset, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2101

hantro_write_addr(vpu, AV1_INPUT_STREAM, src_dma + offset);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2108

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2124

hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2125

hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2126

hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2131

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2162

hantro_reg_write(vpu, &av1_dec_mode, AV1_DEC_MODE);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2163

hantro_reg_write(vpu, &av1_dec_out_ec_byte_word, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2164

hantro_reg_write(vpu, &av1_write_mvs_e, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2165

hantro_reg_write(vpu, &av1_dec_out_ec_bypass, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2166

hantro_reg_write(vpu, &av1_dec_clk_gate_e, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2168

hantro_reg_write(vpu, &av1_dec_abort_e, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2169

hantro_reg_write(vpu, &av1_dec_tile_int_e, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2171

hantro_reg_write(vpu, &av1_dec_alignment, 64);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2172

hantro_reg_write(vpu, &av1_apf_disable, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2173

hantro_reg_write(vpu, &av1_apf_threshold, 8);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2174

hantro_reg_write(vpu, &av1_dec_buswidth, 2);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2175

hantro_reg_write(vpu, &av1_dec_max_burst, 16);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2176

hantro_reg_write(vpu, &av1_error_conceal_e, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2177

hantro_reg_write(vpu, &av1_axi_rd_ostd_threshold, 64);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2178

hantro_reg_write(vpu, &av1_axi_wr_ostd_threshold, 64);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2180

hantro_reg_write(vpu, &av1_ext_timeout_cycles, 0xfffffff);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2181

hantro_reg_write(vpu, &av1_ext_timeout_override_e, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2182

hantro_reg_write(vpu, &av1_timeout_cycles, 0xfffffff);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2183

hantro_reg_write(vpu, &av1_timeout_override_e, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2190

hantro_reg_write(vpu, &av1_dec_e, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2196

hantro_irq_done(vpu, VB2_BUF_STATE_ERROR);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2202

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2216

hantro_reg_write(vpu, &av1_pp_out_e, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2217

hantro_reg_write(vpu, &av1_pp_in_format, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2218

hantro_reg_write(vpu, &av1_pp0_dup_hor, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2219

hantro_reg_write(vpu, &av1_pp0_dup_ver, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2221

hantro_reg_write(vpu, &av1_pp_in_height, height / 2);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2222

hantro_reg_write(vpu, &av1_pp_in_width, width / 2);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2223

hantro_reg_write(vpu, &av1_pp_out_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2224

hantro_reg_write(vpu, &av1_pp_out_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2225

hantro_reg_write(vpu, &av1_pp_out_y_stride,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2227

hantro_reg_write(vpu, &av1_pp_out_c_stride,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2231

hantro_reg_write(vpu, &av1_pp_out_format, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2234

hantro_reg_write(vpu, &av1_pp_out_format, 3);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2238

hantro_reg_write(vpu, &av1_pp_out_format, 10);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2241

hantro_reg_write(vpu, &av1_pp_out_format, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2244

hantro_reg_write(vpu, &av1_ppd_blend_exist, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2245

hantro_reg_write(vpu, &av1_ppd_dith_exist, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2246

hantro_reg_write(vpu, &av1_ablend_crop_e, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2247

hantro_reg_write(vpu, &av1_pp_format_customer1_e, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2248

hantro_reg_write(vpu, &av1_pp_crop_exist, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2249

hantro_reg_write(vpu, &av1_pp_up_level, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2250

hantro_reg_write(vpu, &av1_pp_down_level, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2251

hantro_reg_write(vpu, &av1_pp_exist, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2253

hantro_write_addr(vpu, AV1_PP_OUT_LU, dst_dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2254

hantro_write_addr(vpu, AV1_PP_OUT_CH, dst_dma + chroma_offset);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2259

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

2262

hantro_reg_write(vpu, &av1_pp_out_e, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

231

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

235

dma_free_coherent(vpu->dev, av1_dec->db_data_col.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

241

dma_free_coherent(vpu->dev, av1_dec->db_ctrl_col.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

247

dma_free_coherent(vpu->dev, av1_dec->cdef_col.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

252

dma_free_coherent(vpu->dev, av1_dec->sr_col.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

257

dma_free_coherent(vpu->dev, av1_dec->lr_col.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

264

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

281

av1_dec->db_data_col.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

289

av1_dec->db_ctrl_col.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

297

av1_dec->cdef_col.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

305

av1_dec->sr_col.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

313

av1_dec->lr_col.cpu = dma_alloc_coherent(vpu->dev, size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

330

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

334

dma_free_coherent(vpu->dev, av1_dec->global_model.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

340

dma_free_coherent(vpu->dev, av1_dec->tile_info.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

346

dma_free_coherent(vpu->dev, av1_dec->film_grain.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

352

dma_free_coherent(vpu->dev, av1_dec->prob_tbl.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

357

dma_free_coherent(vpu->dev, av1_dec->prob_tbl_out.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

363

dma_free_coherent(vpu->dev, av1_dec->tile_buf.size,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

372

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

377

av1_dec->global_model.cpu = dma_alloc_coherent(vpu->dev, GLOBAL_MODEL_SIZE,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

384

av1_dec->tile_info.cpu = dma_alloc_coherent(vpu->dev, AV1_TILE_INFO_SIZE,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

391

av1_dec->film_grain.cpu = dma_alloc_coherent(vpu->dev,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

399

av1_dec->prob_tbl.cpu = dma_alloc_coherent(vpu->dev,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

407

av1_dec->prob_tbl_out.cpu = dma_alloc_coherent(vpu->dev,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

419

av1_dec->tile_buf.cpu = dma_alloc_coherent(vpu->dev,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

524

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

558

hantro_write_addr(vpu, AV1_GLOBAL_MODEL, av1_dec->global_model.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

588

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

627

hantro_reg_write(vpu, &av1_multicore_expect_context_update, !!(context_update_x == 0));

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

628

hantro_reg_write(vpu, &av1_tile_enable,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

630

hantro_reg_write(vpu, &av1_num_tile_cols_8k, tile_info->tile_cols);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

631

hantro_reg_write(vpu, &av1_num_tile_rows_8k, tile_info->tile_rows);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

632

hantro_reg_write(vpu, &av1_context_update_tile_id, context_update_tile_id);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

633

hantro_reg_write(vpu, &av1_tile_transpose, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

636

hantro_reg_write(vpu, &av1_dec_tile_size_mag, tile_info->tile_size_bytes - 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

638

hantro_reg_write(vpu, &av1_dec_tile_size_mag, 3);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

640

hantro_write_addr(vpu, AV1_TILE_BASE, av1_dec->tile_info.dma);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

694

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

706

hantro_reg_write(vpu, &av1_ref0_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

707

hantro_reg_write(vpu, &av1_ref0_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

708

hantro_reg_write(vpu, &av1_ref0_ver_scale, scale_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

709

hantro_reg_write(vpu, &av1_ref0_hor_scale, scale_height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

712

hantro_reg_write(vpu, &av1_ref1_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

713

hantro_reg_write(vpu, &av1_ref1_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

714

hantro_reg_write(vpu, &av1_ref1_ver_scale, scale_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

715

hantro_reg_write(vpu, &av1_ref1_hor_scale, scale_height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

718

hantro_reg_write(vpu, &av1_ref2_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

719

hantro_reg_write(vpu, &av1_ref2_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

720

hantro_reg_write(vpu, &av1_ref2_ver_scale, scale_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

721

hantro_reg_write(vpu, &av1_ref2_hor_scale, scale_height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

724

hantro_reg_write(vpu, &av1_ref3_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

725

hantro_reg_write(vpu, &av1_ref3_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

726

hantro_reg_write(vpu, &av1_ref3_ver_scale, scale_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

727

hantro_reg_write(vpu, &av1_ref3_hor_scale, scale_height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

730

hantro_reg_write(vpu, &av1_ref4_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

731

hantro_reg_write(vpu, &av1_ref4_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

732

hantro_reg_write(vpu, &av1_ref4_ver_scale, scale_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

733

hantro_reg_write(vpu, &av1_ref4_hor_scale, scale_height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

736

hantro_reg_write(vpu, &av1_ref5_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

737

hantro_reg_write(vpu, &av1_ref5_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

738

hantro_reg_write(vpu, &av1_ref5_ver_scale, scale_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

739

hantro_reg_write(vpu, &av1_ref5_hor_scale, scale_height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

742

hantro_reg_write(vpu, &av1_ref6_height, height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

743

hantro_reg_write(vpu, &av1_ref6_width, width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

744

hantro_reg_write(vpu, &av1_ref6_ver_scale, scale_width);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

745

hantro_reg_write(vpu, &av1_ref6_hor_scale, scale_height);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

756

hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

757

hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

758

hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), mv_addr);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

767

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

771

hantro_reg_write(vpu, &av1_ref0_sign_bias, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

774

hantro_reg_write(vpu, &av1_ref1_sign_bias, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

777

hantro_reg_write(vpu, &av1_ref2_sign_bias, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

780

hantro_reg_write(vpu, &av1_ref3_sign_bias, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

783

hantro_reg_write(vpu, &av1_ref4_sign_bias, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

786

hantro_reg_write(vpu, &av1_ref5_sign_bias, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

789

hantro_reg_write(vpu, &av1_ref6_sign_bias, val);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

804

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

820

hantro_write_addr(vpu, AV1_SEGMENTATION, mv_addr);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

821

hantro_reg_write(vpu, &av1_use_temporal3_mvs, 1);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

825

hantro_reg_write(vpu, &av1_segment_temp_upd_e,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

827

hantro_reg_write(vpu, &av1_segment_upd_e,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

829

hantro_reg_write(vpu, &av1_segment_e,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

832

hantro_reg_write(vpu, &av1_error_resilient,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

837

hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

901

hantro_reg_write(vpu, &av1_last_active_seg, last_active_seg);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

902

hantro_reg_write(vpu, &av1_preskip_segid, preskip_segid);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

904

hantro_reg_write(vpu, &av1_seg_quant_sign, segsign);

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

907

hantro_reg_write(vpu, &av1_quant_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

909

hantro_reg_write(vpu, &av1_filt_level_delta0_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

911

hantro_reg_write(vpu, &av1_filt_level_delta1_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

913

hantro_reg_write(vpu, &av1_filt_level_delta2_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

915

hantro_reg_write(vpu, &av1_filt_level_delta3_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

917

hantro_reg_write(vpu, &av1_refpic_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

919

hantro_reg_write(vpu, &av1_skip_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

921

hantro_reg_write(vpu, &av1_global_mv_seg0,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

924

hantro_reg_write(vpu, &av1_quant_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

926

hantro_reg_write(vpu, &av1_filt_level_delta0_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

928

hantro_reg_write(vpu, &av1_filt_level_delta1_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

930

hantro_reg_write(vpu, &av1_filt_level_delta2_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

932

hantro_reg_write(vpu, &av1_filt_level_delta3_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

934

hantro_reg_write(vpu, &av1_refpic_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

936

hantro_reg_write(vpu, &av1_skip_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

938

hantro_reg_write(vpu, &av1_global_mv_seg1,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

941

hantro_reg_write(vpu, &av1_quant_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

943

hantro_reg_write(vpu, &av1_filt_level_delta0_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

945

hantro_reg_write(vpu, &av1_filt_level_delta1_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

947

hantro_reg_write(vpu, &av1_filt_level_delta2_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

949

hantro_reg_write(vpu, &av1_filt_level_delta3_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

951

hantro_reg_write(vpu, &av1_refpic_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

953

hantro_reg_write(vpu, &av1_skip_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

955

hantro_reg_write(vpu, &av1_global_mv_seg2,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

958

hantro_reg_write(vpu, &av1_quant_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

960

hantro_reg_write(vpu, &av1_filt_level_delta0_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

962

hantro_reg_write(vpu, &av1_filt_level_delta1_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

964

hantro_reg_write(vpu, &av1_filt_level_delta2_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

966

hantro_reg_write(vpu, &av1_filt_level_delta3_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

968

hantro_reg_write(vpu, &av1_refpic_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

970

hantro_reg_write(vpu, &av1_skip_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

972

hantro_reg_write(vpu, &av1_global_mv_seg3,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

975

hantro_reg_write(vpu, &av1_quant_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

977

hantro_reg_write(vpu, &av1_filt_level_delta0_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

979

hantro_reg_write(vpu, &av1_filt_level_delta1_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

981

hantro_reg_write(vpu, &av1_filt_level_delta2_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

983

hantro_reg_write(vpu, &av1_filt_level_delta3_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

985

hantro_reg_write(vpu, &av1_refpic_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

987

hantro_reg_write(vpu, &av1_skip_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

989

hantro_reg_write(vpu, &av1_global_mv_seg4,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

992

hantro_reg_write(vpu, &av1_quant_seg5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

994

hantro_reg_write(vpu, &av1_filt_level_delta0_seg5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

996

hantro_reg_write(vpu, &av1_filt_level_delta1_seg5,

drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

998

hantro_reg_write(vpu, &av1_filt_level_delta2_seg5,

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

371

struct hantro_dev *vpu = dev_id;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

375

status = vepu_read(vpu, H1_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

379

vepu_write(vpu, 0, H1_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

380

vepu_write(vpu, 0, H1_REG_AXI_CTRL);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

382

hantro_irq_done(vpu, state);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

389

struct hantro_dev *vpu = dev_id;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

393

status = vdpu_read(vpu, VDPU_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

397

vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

398

vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

400

hantro_irq_done(vpu, state);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

407

struct hantro_dev *vpu = dev_id;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

411

status = vepu_read(vpu, VEPU_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

415

vepu_write(vpu, 0, VEPU_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

416

vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

418

hantro_irq_done(vpu, state);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

425

struct hantro_dev *vpu = dev_id;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

429

status = vdpu_read(vpu, AV1_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

433

vdpu_write(vpu, 0, AV1_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

434

vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

436

hantro_irq_done(vpu, state);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

441

static int rk3036_vpu_hw_init(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

444

clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

448

static int rk3066_vpu_hw_init(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

451

clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

452

clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

456

static int rockchip_vpu_hw_init(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

459

clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

465

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

467

vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

468

vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

473

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

475

vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

476

vepu_write(vpu, 0, H1_REG_ENC_CTRL);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

477

vepu_write(vpu, 0, H1_REG_AXI_CTRL);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

482

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

484

vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

485

vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

486

vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

491

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

493

vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

494

vepu_write(vpu, 0, VEPU_REG_ENCODE_START);

drivers/media/platform/verisilicon/rockchip_vpu_hw.c

495

vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);

drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c

103

status = vepu_read(vpu, H1_REG_INTERRUPT);

drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c

107

vepu_write(vpu, H1_REG_INTERRUPT_BIT, H1_REG_INTERRUPT);

drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c

109

hantro_irq_done(vpu, state);

drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c

116

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c

118

reset_control_reset(vpu->resets);

drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c

99

struct hantro_dev *vpu = dev_id;

drivers/media/platform/verisilicon/sunxi_vpu_hw.c

83

static int sunxi_vpu_hw_init(struct hantro_dev *vpu)

drivers/media/platform/verisilicon/sunxi_vpu_hw.c

85

clk_set_rate(vpu->clocks[0].clk, 300000000);

drivers/media/platform/verisilicon/sunxi_vpu_hw.c

92

struct hantro_dev *vpu = ctx->dev;

drivers/media/platform/verisilicon/sunxi_vpu_hw.c

94

reset_control_reset(vpu->resets);

drivers/remoteproc/ingenic_rproc.c

100

writel(ctrl, vpu->aux_base + REG_AUX_CTRL);

drivers/remoteproc/ingenic_rproc.c

107

struct vpu *vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

109

disable_irq(vpu->irq);

drivers/remoteproc/ingenic_rproc.c

112

writel(AUX_CTRL_SW_RESET, vpu->aux_base + REG_AUX_CTRL);

drivers/remoteproc/ingenic_rproc.c

119

struct vpu *vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

121

writel(vqid, vpu->aux_base + REG_CORE_MSG);

drivers/remoteproc/ingenic_rproc.c

126

struct vpu *vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

131

const struct vpu_mem_info *info = &vpu->mem_info[i];

drivers/remoteproc/ingenic_rproc.c

155

struct vpu *vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

158

vring = readl(vpu->aux_base + REG_AUX_MSG);

drivers/remoteproc/ingenic_rproc.c

161

writel(0, vpu->aux_base + REG_AUX_MSG_ACK);

drivers/remoteproc/ingenic_rproc.c

171

struct vpu *vpu;

drivers/remoteproc/ingenic_rproc.c

176

&ingenic_rproc_ops, NULL, sizeof(*vpu));

drivers/remoteproc/ingenic_rproc.c

182

vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

183

vpu->dev = &pdev->dev;

drivers/remoteproc/ingenic_rproc.c

184

platform_set_drvdata(pdev, vpu);

drivers/remoteproc/ingenic_rproc.c

186

vpu->aux_base = devm_platform_ioremap_resource_byname(pdev, "aux");

drivers/remoteproc/ingenic_rproc.c

187

if (IS_ERR(vpu->aux_base)) {

drivers/remoteproc/ingenic_rproc.c

189

return PTR_ERR(vpu->aux_base);

drivers/remoteproc/ingenic_rproc.c

196

vpu->mem_info[i].base = devm_ioremap_resource(dev, mem);

drivers/remoteproc/ingenic_rproc.c

197

if (IS_ERR(vpu->mem_info[i].base)) {

drivers/remoteproc/ingenic_rproc.c

198

ret = PTR_ERR(vpu->mem_info[i].base);

drivers/remoteproc/ingenic_rproc.c

203

vpu->mem_info[i].len = resource_size(mem);

drivers/remoteproc/ingenic_rproc.c

204

vpu->mem_info[i].map = &vpu_mem_map[i];

drivers/remoteproc/ingenic_rproc.c

207

vpu->clks[0].id = "vpu";

drivers/remoteproc/ingenic_rproc.c

208

vpu->clks[1].id = "aux";

drivers/remoteproc/ingenic_rproc.c

210

ret = devm_clk_bulk_get(dev, ARRAY_SIZE(vpu->clks), vpu->clks);

drivers/remoteproc/ingenic_rproc.c

216

vpu->irq = platform_get_irq(pdev, 0);

drivers/remoteproc/ingenic_rproc.c

217

if (vpu->irq < 0)

drivers/remoteproc/ingenic_rproc.c

218

return vpu->irq;

drivers/remoteproc/ingenic_rproc.c

220

ret = devm_request_irq(dev, vpu->irq, vpu_interrupt, IRQF_NO_AUTOEN,

drivers/remoteproc/ingenic_rproc.c

71

struct vpu *vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

75

ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks);

drivers/remoteproc/ingenic_rproc.c

77

dev_err(vpu->dev, "Unable to start clocks: %d\n", ret);

drivers/remoteproc/ingenic_rproc.c

84

struct vpu *vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

86

clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks);

drivers/remoteproc/ingenic_rproc.c

93

struct vpu *vpu = rproc->priv;

drivers/remoteproc/ingenic_rproc.c

96

enable_irq(vpu->irq);

include/uapi/drm/radeon_drm.h

261

} vpu;