txop
p->txop = params->txop * 32;
params->txop = __cpu_to_le32(arg->txop);
__le32 txop;
u32 txop;
p->txop = params->mu_edca_param_rec.mu_edca_timer;
p->txop = params->txop;
wmm_param->txoplimit = wmi_wmm_arg->txop;
u16 txop;
p->txop = params->txop;
wmm_param->txoplimit = cpu_to_le32(wmi_wmm_arg->txop);
u16 txop;
qi.tqi_burst_time = params->txop * 32;
params->cw_max, params->txop);
void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
qi.tqi_burstTime = params->txop * 32;
params->cw_max, params->txop);
qi.tqi_burstTime = params->txop * 32;
params->cw_max, params->txop);
void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
if (!txop || txop > 4096)
txop = 4096;
cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
ar->edcf[0].txop | ar->edcf[1].txop << 16);
ar->edcf[2].txop | ar->edcf[3].txop << 16 |
ar->edcf[4].txop << 24);
queue.txop = _txop; \
params[B43_QOSPARAM_TXOP] = p->txop * 32;
params->p.txop = 0;
params->p.txop = 0;
params->p.txop = 0;
params->p.txop = 0;
u16 txop;
acp_shm.txop = params->txop;
wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
EDCF_TXOP2USEC(acp_shm.txop);
if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
txq_pars.txop = edcf_acp->TXOP;
#define EDCF_TXOP2USEC(txop) ((txop) << 5)
u32 txop;
txop = le16_to_cpu(ac_params->tx_op_limit) * 32;
qos_param->tx_op_limit[i] = cpu_to_le16(txop);
cpu_to_le16((params->txop * 32));
cpu_to_le16((params->txop * 32));
cpu_to_le16(mld_link->queue_params[mac_ac].txop * 32);
i, mvmvif->deflink.queue_params[i].txop,
cpu_to_le16(mvm_link->queue_params[i].txop * 32);
params->cw_min, params->cw_max, params->txop);
queue.txop = cpu_to_le16(_txop); \
__le16 txop;
__le16 txop;
__u8 aifs, __u16 txop)
cmd->txop = cpu_to_le16(txop);
params->txop);
val |= params->txop << MT_WMM_TXOP_SHIFT(queue);
__le16 txop;
.txop = cpu_to_le16(params->txop),
val = FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop) |
val |= params->txop << MT_WMM_TXOP_SHIFT(qid);
e->txop = cpu_to_le16(q->txop);
__le16 txop;
u16 cw_max, u16 txop)
e->txop = cpu_to_le16(txop);
__le16 txop;
e->txop = cpu_to_le16(q->txop);
e->txop = cpu_to_le16(q->txop);
__le16 txop;
e->txop = cpu_to_le16(q->txop);
__le16 txop;
WARN_ON(params->txop > 0xff);
val |= FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop);
val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q);
rt2x00_set_field32(®, field, queue->txop);
rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
queue->txop = params->txop;
queue->txop);
queue->txop = 0;
txdesc->u.ht.txop = TXOP_SIFS;
txdesc->u.ht.txop = TXOP_BACKOFF;
txdesc->u.ht.txop = TXOP_BACKOFF;
txdesc->u.ht.txop = TXOP_SIFS;
txdesc->u.ht.txop = TXOP_HTTXOP;
enum txop txop;
unsigned short txop;
rt2x00_set_field32(®, field, queue->txop);
rt2x00_set_field32(®, field, queue->txop);
u8 txop;
txop = params->txop;
ac_param = txop << AC_PARAM_TXOP_LIMIT_SHIFT |
(params->txop << 16) | (cw_max << 12) |
(u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
reg |= (param->txop & 0x7FF) << 16;
mac->ac[aci].tx_op = cpu_to_le16(param->txop);
u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
value |= (u32)txop << 16;
u16 txop,
rtw_write32_mask(rtwdev, edca_param, BIT_MASK_TXOP_LMT, params->txop);
val = FIELD_PREP(FW_EDCA_PARAM_TXOPLMT_MSK, params->txop) |
txop = ((txop << 5) / 80);
txop -= le16_to_cpu(r_txop);
} while (txop > 0);
s16 txop = common->tx_qinfo[q_num].txop * 32;
params->cw_min, params->cw_max, params->txop);
cpu_to_le16(common->edca_params[ii].txop);
s32 txop;
body->tx_op_limit = cpu_to_le16(arg->txop * USEC_PER_TXOP);
params->txop, 0xc8,
u8 aifs, u16 txop)
"aifs %d txop %d", ac, cw_min, cw_max, aifs, txop);
acx->txop_limit = txop;
u8 aifs, u16 txop);
params->aifs, params->txop * 32);
u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop)
"aifs %d txop %d", ac, cw_min, cw_max, aifsn, txop);
acx->tx_op_limit = cpu_to_le16(txop);
u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop);
params->aifs, params->txop << 5);
params->txop, params->cw_min,
uint8_t *txop, uint8_t *rxop)
*txop = BG_OP_IN_CSUM_OUT_NODIF;
*txop = BG_OP_IN_NODIF_OUT_CRC;
*txop = BG_OP_IN_CSUM_OUT_CRC;
*txop = BG_OP_IN_NODIF_OUT_CRC;
*txop = BG_OP_IN_CRC_OUT_CRC;
*txop = BG_OP_IN_CRC_OUT_NODIF;
uint8_t *txop, uint8_t *rxop)
*txop = BG_OP_IN_CRC_OUT_NODIF;
*txop = BG_OP_IN_NODIF_OUT_CSUM;
*txop = BG_OP_IN_CRC_OUT_CSUM;
*txop = BG_OP_IN_NODIF_OUT_CSUM;
*txop = BG_OP_IN_CSUM_OUT_CSUM;
*txop = BG_OP_IN_CSUM_OUT_NODIF;
uint8_t txop, rxop;
status = lpfc_sc_to_bg_opcodes(phba, sc, &txop, &rxop);
lpfc_bg_err_opcodes(phba, sc, &txop, &rxop);
bf_set(pde6_optx, pde6, txop);
uint8_t txop, rxop;
status = lpfc_sc_to_bg_opcodes(phba, sc, &txop, &rxop);
lpfc_bg_err_opcodes(phba, sc, &txop, &rxop);
bf_set(pde6_optx, pde6, txop);
uint8_t txop, rxop;
status = lpfc_sc_to_bg_opcodes(phba, sc, &txop, &rxop);
lpfc_bg_err_opcodes(phba, sc, &txop, &rxop);
bf_set(lpfc_sli4_sge_dif_optx, diseed, txop);
uint8_t txop, rxop;
status = lpfc_sc_to_bg_opcodes(phba, sc, &txop, &rxop);
lpfc_bg_err_opcodes(phba, sc, &txop, &rxop);
if (txop == BG_OP_IN_CRC_OUT_CRC) {
txop = BG_OP_RAW_MODE;
bf_set(lpfc_sli4_sge_dif_optx, diseed, txop);
u16 txop;
u16 txop;
p.txop = params->txop;
params[ac].txop, params[ac].uapsd,
params[ac].txop = get_unaligned_le16(pos + 2);
wmm->ac[i].txop_limit = cpu_to_le16(txq->txop);
__field(u16, txop)
__entry->txop = params->txop;
qparam->txop = min_t(u16, qparam->txop, wmm_ac->cot / 32);
qparam.txop = 0;
qparam.txop = 0;
qparam.txop = 0;
qparam.txop = 0;
qparam.txop = 6016/32;
qparam.txop = 3008/32;
qparam.txop = 0;
qparam.txop = 3264/32;
qparam.txop = 1504/32;
txq_params->txop = nla_get_u16(tb[NL80211_TXQ_ATTR_TXOP]);
__field(u16, txop)
__entry->txop = params->txop;
WIPHY_PR_ARG, NETDEV_PR_ARG, __entry->ac, __entry->txop,