#ifndef _WMI_H_
#define _WMI_H_
#include <linux/types.h>
#include <linux/ieee80211.h>
struct wmi_cmd_hdr {
__le32 cmd_id;
} __packed;
#define WMI_CMD_HDR_CMD_ID_MASK 0x00FFFFFF
#define WMI_CMD_HDR_CMD_ID_LSB 0
#define WMI_CMD_HDR_PLT_PRIV_MASK 0xFF000000
#define WMI_CMD_HDR_PLT_PRIV_LSB 24
#define HTC_PROTOCOL_VERSION 0x0002
#define WMI_PROTOCOL_VERSION 0x0002
typedef __s32 __bitwise a_sle32;
static inline a_sle32 a_cpu_to_sle32(s32 val)
{
return (__force a_sle32)cpu_to_le32(val);
}
static inline s32 a_sle32_to_cpu(a_sle32 val)
{
return le32_to_cpu((__force __le32)val);
}
enum wmi_service {
WMI_SERVICE_BEACON_OFFLOAD = 0,
WMI_SERVICE_SCAN_OFFLOAD,
WMI_SERVICE_ROAM_OFFLOAD,
WMI_SERVICE_BCN_MISS_OFFLOAD,
WMI_SERVICE_STA_PWRSAVE,
WMI_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_SERVICE_AP_UAPSD,
WMI_SERVICE_AP_DFS,
WMI_SERVICE_11AC,
WMI_SERVICE_BLOCKACK,
WMI_SERVICE_PHYERR,
WMI_SERVICE_BCN_FILTER,
WMI_SERVICE_RTT,
WMI_SERVICE_RATECTRL,
WMI_SERVICE_WOW,
WMI_SERVICE_RATECTRL_CACHE,
WMI_SERVICE_IRAM_TIDS,
WMI_SERVICE_ARPNS_OFFLOAD,
WMI_SERVICE_NLO,
WMI_SERVICE_GTK_OFFLOAD,
WMI_SERVICE_SCAN_SCH,
WMI_SERVICE_CSA_OFFLOAD,
WMI_SERVICE_CHATTER,
WMI_SERVICE_COEX_FREQAVOID,
WMI_SERVICE_PACKET_POWER_SAVE,
WMI_SERVICE_FORCE_FW_HANG,
WMI_SERVICE_GPIO,
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM,
WMI_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_SERVICE_STA_KEEP_ALIVE,
WMI_SERVICE_TX_ENCAP,
WMI_SERVICE_BURST,
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT,
WMI_SERVICE_ROAM_SCAN_OFFLOAD,
WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC,
WMI_SERVICE_EARLY_RX,
WMI_SERVICE_STA_SMPS,
WMI_SERVICE_FWTEST,
WMI_SERVICE_STA_WMMAC,
WMI_SERVICE_TDLS,
WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE,
WMI_SERVICE_ADAPTIVE_OCS,
WMI_SERVICE_BA_SSN_SUPPORT,
WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE,
WMI_SERVICE_WLAN_HB,
WMI_SERVICE_LTE_ANT_SHARE_SUPPORT,
WMI_SERVICE_BATCH_SCAN,
WMI_SERVICE_QPOWER,
WMI_SERVICE_PLMREQ,
WMI_SERVICE_THERMAL_MGMT,
WMI_SERVICE_RMC,
WMI_SERVICE_MHF_OFFLOAD,
WMI_SERVICE_COEX_SAR,
WMI_SERVICE_BCN_TXRATE_OVERRIDE,
WMI_SERVICE_NAN,
WMI_SERVICE_L1SS_STAT,
WMI_SERVICE_ESTIMATE_LINKSPEED,
WMI_SERVICE_OBSS_SCAN,
WMI_SERVICE_TDLS_OFFCHAN,
WMI_SERVICE_TDLS_UAPSD_BUFFER_STA,
WMI_SERVICE_TDLS_UAPSD_SLEEP_STA,
WMI_SERVICE_IBSS_PWRSAVE,
WMI_SERVICE_LPASS,
WMI_SERVICE_EXTSCAN,
WMI_SERVICE_D0WOW,
WMI_SERVICE_HSOFFLOAD,
WMI_SERVICE_ROAM_HO_OFFLOAD,
WMI_SERVICE_RX_FULL_REORDER,
WMI_SERVICE_DHCP_OFFLOAD,
WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT,
WMI_SERVICE_MDNS_OFFLOAD,
WMI_SERVICE_SAP_AUTH_OFFLOAD,
WMI_SERVICE_ATF,
WMI_SERVICE_COEX_GPIO,
WMI_SERVICE_ENHANCED_PROXY_STA,
WMI_SERVICE_TT,
WMI_SERVICE_PEER_CACHING,
WMI_SERVICE_AUX_SPECTRAL_INTF,
WMI_SERVICE_AUX_CHAN_LOAD_INTF,
WMI_SERVICE_BSS_CHANNEL_INFO_64,
WMI_SERVICE_EXT_RES_CFG_SUPPORT,
WMI_SERVICE_MESH_11S,
WMI_SERVICE_MESH_NON_11S,
WMI_SERVICE_PEER_STATS,
WMI_SERVICE_RESTRT_CHNL_SUPPORT,
WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT,
WMI_SERVICE_TX_MODE_PUSH_ONLY,
WMI_SERVICE_TX_MODE_PUSH_PULL,
WMI_SERVICE_TX_MODE_DYNAMIC,
WMI_SERVICE_VDEV_RX_FILTER,
WMI_SERVICE_BTCOEX,
WMI_SERVICE_CHECK_CAL_VERSION,
WMI_SERVICE_DBGLOG_WARN2,
WMI_SERVICE_BTCOEX_DUTY_CYCLE,
WMI_SERVICE_4_WIRE_COEX_SUPPORT,
WMI_SERVICE_EXTENDED_NSS_SUPPORT,
WMI_SERVICE_PROG_GPIO_BAND_SELECT,
WMI_SERVICE_SMART_LOGGING_SUPPORT,
WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE,
WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
WMI_SERVICE_MGMT_TX_WMI,
WMI_SERVICE_TDLS_WIDER_BANDWIDTH,
WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
WMI_SERVICE_HOST_DFS_CHECK_SUPPORT,
WMI_SERVICE_TPC_STATS_FINAL,
WMI_SERVICE_RESET_CHIP,
WMI_SERVICE_SPOOF_MAC_SUPPORT,
WMI_SERVICE_TX_DATA_ACK_RSSI,
WMI_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT,
WMI_SERVICE_VDEV_DISABLE_4_ADDR_SRC_LRN_SUPPORT,
WMI_SERVICE_BB_TIMING_CONFIG_SUPPORT,
WMI_SERVICE_THERM_THROT,
WMI_SERVICE_RTT_RESPONDER_ROLE,
WMI_SERVICE_PER_PACKET_SW_ENCRYPT,
WMI_SERVICE_REPORT_AIRTIME,
WMI_SERVICE_SYNC_DELETE_CMDS,
WMI_SERVICE_TX_PWR_PER_PEER,
WMI_SERVICE_SUPPORT_EXTEND_ADDRESS,
WMI_SERVICE_PEER_TID_CONFIGS_SUPPORT,
WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
WMI_SERVICE_MAX,
};
enum wmi_10x_service {
WMI_10X_SERVICE_BEACON_OFFLOAD = 0,
WMI_10X_SERVICE_SCAN_OFFLOAD,
WMI_10X_SERVICE_ROAM_OFFLOAD,
WMI_10X_SERVICE_BCN_MISS_OFFLOAD,
WMI_10X_SERVICE_STA_PWRSAVE,
WMI_10X_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_10X_SERVICE_AP_UAPSD,
WMI_10X_SERVICE_AP_DFS,
WMI_10X_SERVICE_11AC,
WMI_10X_SERVICE_BLOCKACK,
WMI_10X_SERVICE_PHYERR,
WMI_10X_SERVICE_BCN_FILTER,
WMI_10X_SERVICE_RTT,
WMI_10X_SERVICE_RATECTRL,
WMI_10X_SERVICE_WOW,
WMI_10X_SERVICE_RATECTRL_CACHE,
WMI_10X_SERVICE_IRAM_TIDS,
WMI_10X_SERVICE_BURST,
WMI_10X_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_10X_SERVICE_FORCE_FW_HANG,
WMI_10X_SERVICE_SMART_ANTENNA_HW_SUPPORT,
WMI_10X_SERVICE_ATF,
WMI_10X_SERVICE_COEX_GPIO,
WMI_10X_SERVICE_AUX_SPECTRAL_INTF,
WMI_10X_SERVICE_AUX_CHAN_LOAD_INTF,
WMI_10X_SERVICE_BSS_CHANNEL_INFO_64,
WMI_10X_SERVICE_MESH,
WMI_10X_SERVICE_EXT_RES_CFG_SUPPORT,
WMI_10X_SERVICE_PEER_STATS,
WMI_10X_SERVICE_RESET_CHIP,
WMI_10X_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
WMI_10X_SERVICE_VDEV_BCN_RATE_CONTROL,
WMI_10X_SERVICE_PER_PACKET_SW_ENCRYPT,
WMI_10X_SERVICE_BB_TIMING_CONFIG_SUPPORT,
};
enum wmi_main_service {
WMI_MAIN_SERVICE_BEACON_OFFLOAD = 0,
WMI_MAIN_SERVICE_SCAN_OFFLOAD,
WMI_MAIN_SERVICE_ROAM_OFFLOAD,
WMI_MAIN_SERVICE_BCN_MISS_OFFLOAD,
WMI_MAIN_SERVICE_STA_PWRSAVE,
WMI_MAIN_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_MAIN_SERVICE_AP_UAPSD,
WMI_MAIN_SERVICE_AP_DFS,
WMI_MAIN_SERVICE_11AC,
WMI_MAIN_SERVICE_BLOCKACK,
WMI_MAIN_SERVICE_PHYERR,
WMI_MAIN_SERVICE_BCN_FILTER,
WMI_MAIN_SERVICE_RTT,
WMI_MAIN_SERVICE_RATECTRL,
WMI_MAIN_SERVICE_WOW,
WMI_MAIN_SERVICE_RATECTRL_CACHE,
WMI_MAIN_SERVICE_IRAM_TIDS,
WMI_MAIN_SERVICE_ARPNS_OFFLOAD,
WMI_MAIN_SERVICE_NLO,
WMI_MAIN_SERVICE_GTK_OFFLOAD,
WMI_MAIN_SERVICE_SCAN_SCH,
WMI_MAIN_SERVICE_CSA_OFFLOAD,
WMI_MAIN_SERVICE_CHATTER,
WMI_MAIN_SERVICE_COEX_FREQAVOID,
WMI_MAIN_SERVICE_PACKET_POWER_SAVE,
WMI_MAIN_SERVICE_FORCE_FW_HANG,
WMI_MAIN_SERVICE_GPIO,
WMI_MAIN_SERVICE_STA_DTIM_PS_MODULATED_DTIM,
WMI_MAIN_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_MAIN_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_MAIN_SERVICE_STA_KEEP_ALIVE,
WMI_MAIN_SERVICE_TX_ENCAP,
};
enum wmi_10_4_service {
WMI_10_4_SERVICE_BEACON_OFFLOAD = 0,
WMI_10_4_SERVICE_SCAN_OFFLOAD,
WMI_10_4_SERVICE_ROAM_OFFLOAD,
WMI_10_4_SERVICE_BCN_MISS_OFFLOAD,
WMI_10_4_SERVICE_STA_PWRSAVE,
WMI_10_4_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_10_4_SERVICE_AP_UAPSD,
WMI_10_4_SERVICE_AP_DFS,
WMI_10_4_SERVICE_11AC,
WMI_10_4_SERVICE_BLOCKACK,
WMI_10_4_SERVICE_PHYERR,
WMI_10_4_SERVICE_BCN_FILTER,
WMI_10_4_SERVICE_RTT,
WMI_10_4_SERVICE_RATECTRL,
WMI_10_4_SERVICE_WOW,
WMI_10_4_SERVICE_RATECTRL_CACHE,
WMI_10_4_SERVICE_IRAM_TIDS,
WMI_10_4_SERVICE_BURST,
WMI_10_4_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_10_4_SERVICE_GTK_OFFLOAD,
WMI_10_4_SERVICE_SCAN_SCH,
WMI_10_4_SERVICE_CSA_OFFLOAD,
WMI_10_4_SERVICE_CHATTER,
WMI_10_4_SERVICE_COEX_FREQAVOID,
WMI_10_4_SERVICE_PACKET_POWER_SAVE,
WMI_10_4_SERVICE_FORCE_FW_HANG,
WMI_10_4_SERVICE_SMART_ANTENNA_HW_SUPPORT,
WMI_10_4_SERVICE_GPIO,
WMI_10_4_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_10_4_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_10_4_SERVICE_STA_KEEP_ALIVE,
WMI_10_4_SERVICE_TX_ENCAP,
WMI_10_4_SERVICE_AP_PS_DETECT_OUT_OF_SYNC,
WMI_10_4_SERVICE_EARLY_RX,
WMI_10_4_SERVICE_ENHANCED_PROXY_STA,
WMI_10_4_SERVICE_TT,
WMI_10_4_SERVICE_ATF,
WMI_10_4_SERVICE_PEER_CACHING,
WMI_10_4_SERVICE_COEX_GPIO,
WMI_10_4_SERVICE_AUX_SPECTRAL_INTF,
WMI_10_4_SERVICE_AUX_CHAN_LOAD_INTF,
WMI_10_4_SERVICE_BSS_CHANNEL_INFO_64,
WMI_10_4_SERVICE_EXT_RES_CFG_SUPPORT,
WMI_10_4_SERVICE_MESH_NON_11S,
WMI_10_4_SERVICE_RESTRT_CHNL_SUPPORT,
WMI_10_4_SERVICE_PEER_STATS,
WMI_10_4_SERVICE_MESH_11S,
WMI_10_4_SERVICE_PERIODIC_CHAN_STAT_SUPPORT,
WMI_10_4_SERVICE_TX_MODE_PUSH_ONLY,
WMI_10_4_SERVICE_TX_MODE_PUSH_PULL,
WMI_10_4_SERVICE_TX_MODE_DYNAMIC,
WMI_10_4_SERVICE_VDEV_RX_FILTER,
WMI_10_4_SERVICE_BTCOEX,
WMI_10_4_SERVICE_CHECK_CAL_VERSION,
WMI_10_4_SERVICE_DBGLOG_WARN2,
WMI_10_4_SERVICE_BTCOEX_DUTY_CYCLE,
WMI_10_4_SERVICE_4_WIRE_COEX_SUPPORT,
WMI_10_4_SERVICE_EXTENDED_NSS_SUPPORT,
WMI_10_4_SERVICE_PROG_GPIO_BAND_SELECT,
WMI_10_4_SERVICE_SMART_LOGGING_SUPPORT,
WMI_10_4_SERVICE_TDLS,
WMI_10_4_SERVICE_TDLS_OFFCHAN,
WMI_10_4_SERVICE_TDLS_UAPSD_BUFFER_STA,
WMI_10_4_SERVICE_TDLS_UAPSD_SLEEP_STA,
WMI_10_4_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE,
WMI_10_4_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
WMI_10_4_SERVICE_TDLS_WIDER_BANDWIDTH,
WMI_10_4_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
WMI_10_4_SERVICE_HOST_DFS_CHECK_SUPPORT,
WMI_10_4_SERVICE_TPC_STATS_FINAL,
WMI_10_4_SERVICE_CFR_CAPTURE_SUPPORT,
WMI_10_4_SERVICE_TX_DATA_ACK_RSSI,
WMI_10_4_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_LEGACY,
WMI_10_4_SERVICE_PER_PACKET_SW_ENCRYPT,
WMI_10_4_SERVICE_PEER_TID_CONFIGS_SUPPORT,
WMI_10_4_SERVICE_VDEV_BCN_RATE_CONTROL,
WMI_10_4_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT,
WMI_10_4_SERVICE_HTT_ASSERT_TRIGGER_SUPPORT,
WMI_10_4_SERVICE_VDEV_FILTER_NEIGHBOR_RX_PACKETS,
WMI_10_4_SERVICE_VDEV_DISABLE_4_ADDR_SRC_LRN_SUPPORT,
WMI_10_4_SERVICE_PEER_CHWIDTH_CHANGE,
WMI_10_4_SERVICE_RX_FILTER_OUT_COUNT,
WMI_10_4_SERVICE_RTT_RESPONDER_ROLE,
WMI_10_4_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
WMI_10_4_SERVICE_REPORT_AIRTIME,
WMI_10_4_SERVICE_TX_PWR_PER_PEER,
WMI_10_4_SERVICE_FETCH_PEER_TX_PN,
WMI_10_4_SERVICE_MULTIPLE_VDEV_RESTART,
WMI_10_4_SERVICE_ENHANCED_RADIO_COUNTERS,
WMI_10_4_SERVICE_QINQ_SUPPORT,
WMI_10_4_SERVICE_RESET_CHIP,
};
static inline char *wmi_service_name(enum wmi_service service_id)
{
#define SVCSTR(x) case x: return #x
switch (service_id) {
SVCSTR(WMI_SERVICE_BEACON_OFFLOAD);
SVCSTR(WMI_SERVICE_SCAN_OFFLOAD);
SVCSTR(WMI_SERVICE_ROAM_OFFLOAD);
SVCSTR(WMI_SERVICE_BCN_MISS_OFFLOAD);
SVCSTR(WMI_SERVICE_STA_PWRSAVE);
SVCSTR(WMI_SERVICE_STA_ADVANCED_PWRSAVE);
SVCSTR(WMI_SERVICE_AP_UAPSD);
SVCSTR(WMI_SERVICE_AP_DFS);
SVCSTR(WMI_SERVICE_11AC);
SVCSTR(WMI_SERVICE_BLOCKACK);
SVCSTR(WMI_SERVICE_PHYERR);
SVCSTR(WMI_SERVICE_BCN_FILTER);
SVCSTR(WMI_SERVICE_RTT);
SVCSTR(WMI_SERVICE_RATECTRL);
SVCSTR(WMI_SERVICE_WOW);
SVCSTR(WMI_SERVICE_RATECTRL_CACHE);
SVCSTR(WMI_SERVICE_IRAM_TIDS);
SVCSTR(WMI_SERVICE_ARPNS_OFFLOAD);
SVCSTR(WMI_SERVICE_NLO);
SVCSTR(WMI_SERVICE_GTK_OFFLOAD);
SVCSTR(WMI_SERVICE_SCAN_SCH);
SVCSTR(WMI_SERVICE_CSA_OFFLOAD);
SVCSTR(WMI_SERVICE_CHATTER);
SVCSTR(WMI_SERVICE_COEX_FREQAVOID);
SVCSTR(WMI_SERVICE_PACKET_POWER_SAVE);
SVCSTR(WMI_SERVICE_FORCE_FW_HANG);
SVCSTR(WMI_SERVICE_GPIO);
SVCSTR(WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM);
SVCSTR(WMI_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG);
SVCSTR(WMI_SERVICE_STA_UAPSD_VAR_AUTO_TRIG);
SVCSTR(WMI_SERVICE_STA_KEEP_ALIVE);
SVCSTR(WMI_SERVICE_TX_ENCAP);
SVCSTR(WMI_SERVICE_BURST);
SVCSTR(WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT);
SVCSTR(WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT);
SVCSTR(WMI_SERVICE_ROAM_SCAN_OFFLOAD);
SVCSTR(WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC);
SVCSTR(WMI_SERVICE_EARLY_RX);
SVCSTR(WMI_SERVICE_STA_SMPS);
SVCSTR(WMI_SERVICE_FWTEST);
SVCSTR(WMI_SERVICE_STA_WMMAC);
SVCSTR(WMI_SERVICE_TDLS);
SVCSTR(WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE);
SVCSTR(WMI_SERVICE_ADAPTIVE_OCS);
SVCSTR(WMI_SERVICE_BA_SSN_SUPPORT);
SVCSTR(WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE);
SVCSTR(WMI_SERVICE_WLAN_HB);
SVCSTR(WMI_SERVICE_LTE_ANT_SHARE_SUPPORT);
SVCSTR(WMI_SERVICE_BATCH_SCAN);
SVCSTR(WMI_SERVICE_QPOWER);
SVCSTR(WMI_SERVICE_PLMREQ);
SVCSTR(WMI_SERVICE_THERMAL_MGMT);
SVCSTR(WMI_SERVICE_RMC);
SVCSTR(WMI_SERVICE_MHF_OFFLOAD);
SVCSTR(WMI_SERVICE_COEX_SAR);
SVCSTR(WMI_SERVICE_BCN_TXRATE_OVERRIDE);
SVCSTR(WMI_SERVICE_NAN);
SVCSTR(WMI_SERVICE_L1SS_STAT);
SVCSTR(WMI_SERVICE_ESTIMATE_LINKSPEED);
SVCSTR(WMI_SERVICE_OBSS_SCAN);
SVCSTR(WMI_SERVICE_TDLS_OFFCHAN);
SVCSTR(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA);
SVCSTR(WMI_SERVICE_TDLS_UAPSD_SLEEP_STA);
SVCSTR(WMI_SERVICE_IBSS_PWRSAVE);
SVCSTR(WMI_SERVICE_LPASS);
SVCSTR(WMI_SERVICE_EXTSCAN);
SVCSTR(WMI_SERVICE_D0WOW);
SVCSTR(WMI_SERVICE_HSOFFLOAD);
SVCSTR(WMI_SERVICE_ROAM_HO_OFFLOAD);
SVCSTR(WMI_SERVICE_RX_FULL_REORDER);
SVCSTR(WMI_SERVICE_DHCP_OFFLOAD);
SVCSTR(WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT);
SVCSTR(WMI_SERVICE_MDNS_OFFLOAD);
SVCSTR(WMI_SERVICE_SAP_AUTH_OFFLOAD);
SVCSTR(WMI_SERVICE_ATF);
SVCSTR(WMI_SERVICE_COEX_GPIO);
SVCSTR(WMI_SERVICE_ENHANCED_PROXY_STA);
SVCSTR(WMI_SERVICE_TT);
SVCSTR(WMI_SERVICE_PEER_CACHING);
SVCSTR(WMI_SERVICE_AUX_SPECTRAL_INTF);
SVCSTR(WMI_SERVICE_AUX_CHAN_LOAD_INTF);
SVCSTR(WMI_SERVICE_BSS_CHANNEL_INFO_64);
SVCSTR(WMI_SERVICE_EXT_RES_CFG_SUPPORT);
SVCSTR(WMI_SERVICE_MESH_11S);
SVCSTR(WMI_SERVICE_MESH_NON_11S);
SVCSTR(WMI_SERVICE_PEER_STATS);
SVCSTR(WMI_SERVICE_RESTRT_CHNL_SUPPORT);
SVCSTR(WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT);
SVCSTR(WMI_SERVICE_TX_MODE_PUSH_ONLY);
SVCSTR(WMI_SERVICE_TX_MODE_PUSH_PULL);
SVCSTR(WMI_SERVICE_TX_MODE_DYNAMIC);
SVCSTR(WMI_SERVICE_VDEV_RX_FILTER);
SVCSTR(WMI_SERVICE_BTCOEX);
SVCSTR(WMI_SERVICE_CHECK_CAL_VERSION);
SVCSTR(WMI_SERVICE_DBGLOG_WARN2);
SVCSTR(WMI_SERVICE_BTCOEX_DUTY_CYCLE);
SVCSTR(WMI_SERVICE_4_WIRE_COEX_SUPPORT);
SVCSTR(WMI_SERVICE_EXTENDED_NSS_SUPPORT);
SVCSTR(WMI_SERVICE_PROG_GPIO_BAND_SELECT);
SVCSTR(WMI_SERVICE_SMART_LOGGING_SUPPORT);
SVCSTR(WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE);
SVCSTR(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY);
SVCSTR(WMI_SERVICE_MGMT_TX_WMI);
SVCSTR(WMI_SERVICE_TDLS_WIDER_BANDWIDTH);
SVCSTR(WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS);
SVCSTR(WMI_SERVICE_HOST_DFS_CHECK_SUPPORT);
SVCSTR(WMI_SERVICE_TPC_STATS_FINAL);
SVCSTR(WMI_SERVICE_RESET_CHIP);
SVCSTR(WMI_SERVICE_SPOOF_MAC_SUPPORT);
SVCSTR(WMI_SERVICE_TX_DATA_ACK_RSSI);
SVCSTR(WMI_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT);
SVCSTR(WMI_SERVICE_VDEV_DISABLE_4_ADDR_SRC_LRN_SUPPORT);
SVCSTR(WMI_SERVICE_BB_TIMING_CONFIG_SUPPORT);
SVCSTR(WMI_SERVICE_THERM_THROT);
SVCSTR(WMI_SERVICE_RTT_RESPONDER_ROLE);
SVCSTR(WMI_SERVICE_PER_PACKET_SW_ENCRYPT);
SVCSTR(WMI_SERVICE_REPORT_AIRTIME);
SVCSTR(WMI_SERVICE_SYNC_DELETE_CMDS);
SVCSTR(WMI_SERVICE_TX_PWR_PER_PEER);
SVCSTR(WMI_SERVICE_SUPPORT_EXTEND_ADDRESS);
SVCSTR(WMI_SERVICE_PEER_TID_CONFIGS_SUPPORT);
SVCSTR(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT);
case WMI_SERVICE_MAX:
return NULL;
}
#undef SVCSTR
return NULL;
}
#define WMI_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id, len) \
((svc_id) < (len) && \
__le32_to_cpu((wmi_svc_bmap)[(svc_id) / (sizeof(u32))]) & \
BIT((svc_id) % (sizeof(u32))))
#define WMI_EXT_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id, len) \
((svc_id) >= (len) && \
__le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 28]) & \
BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4))
#define SVCMAP(x, y, len) \
do { \
if ((WMI_SERVICE_IS_ENABLED((in), (x), (len))) || \
(WMI_EXT_SERVICE_IS_ENABLED((in), (x), (len)))) \
__set_bit(y, out); \
} while (0)
static inline void wmi_10x_svc_map(const __le32 *in, unsigned long *out,
size_t len)
{
SVCMAP(WMI_10X_SERVICE_BEACON_OFFLOAD,
WMI_SERVICE_BEACON_OFFLOAD, len);
SVCMAP(WMI_10X_SERVICE_SCAN_OFFLOAD,
WMI_SERVICE_SCAN_OFFLOAD, len);
SVCMAP(WMI_10X_SERVICE_ROAM_OFFLOAD,
WMI_SERVICE_ROAM_OFFLOAD, len);
SVCMAP(WMI_10X_SERVICE_BCN_MISS_OFFLOAD,
WMI_SERVICE_BCN_MISS_OFFLOAD, len);
SVCMAP(WMI_10X_SERVICE_STA_PWRSAVE,
WMI_SERVICE_STA_PWRSAVE, len);
SVCMAP(WMI_10X_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_SERVICE_STA_ADVANCED_PWRSAVE, len);
SVCMAP(WMI_10X_SERVICE_AP_UAPSD,
WMI_SERVICE_AP_UAPSD, len);
SVCMAP(WMI_10X_SERVICE_AP_DFS,
WMI_SERVICE_AP_DFS, len);
SVCMAP(WMI_10X_SERVICE_11AC,
WMI_SERVICE_11AC, len);
SVCMAP(WMI_10X_SERVICE_BLOCKACK,
WMI_SERVICE_BLOCKACK, len);
SVCMAP(WMI_10X_SERVICE_PHYERR,
WMI_SERVICE_PHYERR, len);
SVCMAP(WMI_10X_SERVICE_BCN_FILTER,
WMI_SERVICE_BCN_FILTER, len);
SVCMAP(WMI_10X_SERVICE_RTT,
WMI_SERVICE_RTT, len);
SVCMAP(WMI_10X_SERVICE_RATECTRL,
WMI_SERVICE_RATECTRL, len);
SVCMAP(WMI_10X_SERVICE_WOW,
WMI_SERVICE_WOW, len);
SVCMAP(WMI_10X_SERVICE_RATECTRL_CACHE,
WMI_SERVICE_RATECTRL_CACHE, len);
SVCMAP(WMI_10X_SERVICE_IRAM_TIDS,
WMI_SERVICE_IRAM_TIDS, len);
SVCMAP(WMI_10X_SERVICE_BURST,
WMI_SERVICE_BURST, len);
SVCMAP(WMI_10X_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT, len);
SVCMAP(WMI_10X_SERVICE_FORCE_FW_HANG,
WMI_SERVICE_FORCE_FW_HANG, len);
SVCMAP(WMI_10X_SERVICE_SMART_ANTENNA_HW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT, len);
SVCMAP(WMI_10X_SERVICE_ATF,
WMI_SERVICE_ATF, len);
SVCMAP(WMI_10X_SERVICE_COEX_GPIO,
WMI_SERVICE_COEX_GPIO, len);
SVCMAP(WMI_10X_SERVICE_AUX_SPECTRAL_INTF,
WMI_SERVICE_AUX_SPECTRAL_INTF, len);
SVCMAP(WMI_10X_SERVICE_AUX_CHAN_LOAD_INTF,
WMI_SERVICE_AUX_CHAN_LOAD_INTF, len);
SVCMAP(WMI_10X_SERVICE_BSS_CHANNEL_INFO_64,
WMI_SERVICE_BSS_CHANNEL_INFO_64, len);
SVCMAP(WMI_10X_SERVICE_MESH,
WMI_SERVICE_MESH_11S, len);
SVCMAP(WMI_10X_SERVICE_EXT_RES_CFG_SUPPORT,
WMI_SERVICE_EXT_RES_CFG_SUPPORT, len);
SVCMAP(WMI_10X_SERVICE_PEER_STATS,
WMI_SERVICE_PEER_STATS, len);
SVCMAP(WMI_10X_SERVICE_RESET_CHIP,
WMI_SERVICE_RESET_CHIP, len);
SVCMAP(WMI_10X_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS, len);
SVCMAP(WMI_10X_SERVICE_BB_TIMING_CONFIG_SUPPORT,
WMI_SERVICE_BB_TIMING_CONFIG_SUPPORT, len);
SVCMAP(WMI_10X_SERVICE_PER_PACKET_SW_ENCRYPT,
WMI_SERVICE_PER_PACKET_SW_ENCRYPT, len);
}
static inline void wmi_main_svc_map(const __le32 *in, unsigned long *out,
size_t len)
{
SVCMAP(WMI_MAIN_SERVICE_BEACON_OFFLOAD,
WMI_SERVICE_BEACON_OFFLOAD, len);
SVCMAP(WMI_MAIN_SERVICE_SCAN_OFFLOAD,
WMI_SERVICE_SCAN_OFFLOAD, len);
SVCMAP(WMI_MAIN_SERVICE_ROAM_OFFLOAD,
WMI_SERVICE_ROAM_OFFLOAD, len);
SVCMAP(WMI_MAIN_SERVICE_BCN_MISS_OFFLOAD,
WMI_SERVICE_BCN_MISS_OFFLOAD, len);
SVCMAP(WMI_MAIN_SERVICE_STA_PWRSAVE,
WMI_SERVICE_STA_PWRSAVE, len);
SVCMAP(WMI_MAIN_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_SERVICE_STA_ADVANCED_PWRSAVE, len);
SVCMAP(WMI_MAIN_SERVICE_AP_UAPSD,
WMI_SERVICE_AP_UAPSD, len);
SVCMAP(WMI_MAIN_SERVICE_AP_DFS,
WMI_SERVICE_AP_DFS, len);
SVCMAP(WMI_MAIN_SERVICE_11AC,
WMI_SERVICE_11AC, len);
SVCMAP(WMI_MAIN_SERVICE_BLOCKACK,
WMI_SERVICE_BLOCKACK, len);
SVCMAP(WMI_MAIN_SERVICE_PHYERR,
WMI_SERVICE_PHYERR, len);
SVCMAP(WMI_MAIN_SERVICE_BCN_FILTER,
WMI_SERVICE_BCN_FILTER, len);
SVCMAP(WMI_MAIN_SERVICE_RTT,
WMI_SERVICE_RTT, len);
SVCMAP(WMI_MAIN_SERVICE_RATECTRL,
WMI_SERVICE_RATECTRL, len);
SVCMAP(WMI_MAIN_SERVICE_WOW,
WMI_SERVICE_WOW, len);
SVCMAP(WMI_MAIN_SERVICE_RATECTRL_CACHE,
WMI_SERVICE_RATECTRL_CACHE, len);
SVCMAP(WMI_MAIN_SERVICE_IRAM_TIDS,
WMI_SERVICE_IRAM_TIDS, len);
SVCMAP(WMI_MAIN_SERVICE_ARPNS_OFFLOAD,
WMI_SERVICE_ARPNS_OFFLOAD, len);
SVCMAP(WMI_MAIN_SERVICE_NLO,
WMI_SERVICE_NLO, len);
SVCMAP(WMI_MAIN_SERVICE_GTK_OFFLOAD,
WMI_SERVICE_GTK_OFFLOAD, len);
SVCMAP(WMI_MAIN_SERVICE_SCAN_SCH,
WMI_SERVICE_SCAN_SCH, len);
SVCMAP(WMI_MAIN_SERVICE_CSA_OFFLOAD,
WMI_SERVICE_CSA_OFFLOAD, len);
SVCMAP(WMI_MAIN_SERVICE_CHATTER,
WMI_SERVICE_CHATTER, len);
SVCMAP(WMI_MAIN_SERVICE_COEX_FREQAVOID,
WMI_SERVICE_COEX_FREQAVOID, len);
SVCMAP(WMI_MAIN_SERVICE_PACKET_POWER_SAVE,
WMI_SERVICE_PACKET_POWER_SAVE, len);
SVCMAP(WMI_MAIN_SERVICE_FORCE_FW_HANG,
WMI_SERVICE_FORCE_FW_HANG, len);
SVCMAP(WMI_MAIN_SERVICE_GPIO,
WMI_SERVICE_GPIO, len);
SVCMAP(WMI_MAIN_SERVICE_STA_DTIM_PS_MODULATED_DTIM,
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM, len);
SVCMAP(WMI_MAIN_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG, len);
SVCMAP(WMI_MAIN_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_VAR_AUTO_TRIG, len);
SVCMAP(WMI_MAIN_SERVICE_STA_KEEP_ALIVE,
WMI_SERVICE_STA_KEEP_ALIVE, len);
SVCMAP(WMI_MAIN_SERVICE_TX_ENCAP,
WMI_SERVICE_TX_ENCAP, len);
}
static inline void wmi_10_4_svc_map(const __le32 *in, unsigned long *out,
size_t len)
{
SVCMAP(WMI_10_4_SERVICE_BEACON_OFFLOAD,
WMI_SERVICE_BEACON_OFFLOAD, len);
SVCMAP(WMI_10_4_SERVICE_SCAN_OFFLOAD,
WMI_SERVICE_SCAN_OFFLOAD, len);
SVCMAP(WMI_10_4_SERVICE_ROAM_OFFLOAD,
WMI_SERVICE_ROAM_OFFLOAD, len);
SVCMAP(WMI_10_4_SERVICE_BCN_MISS_OFFLOAD,
WMI_SERVICE_BCN_MISS_OFFLOAD, len);
SVCMAP(WMI_10_4_SERVICE_STA_PWRSAVE,
WMI_SERVICE_STA_PWRSAVE, len);
SVCMAP(WMI_10_4_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_SERVICE_STA_ADVANCED_PWRSAVE, len);
SVCMAP(WMI_10_4_SERVICE_AP_UAPSD,
WMI_SERVICE_AP_UAPSD, len);
SVCMAP(WMI_10_4_SERVICE_AP_DFS,
WMI_SERVICE_AP_DFS, len);
SVCMAP(WMI_10_4_SERVICE_11AC,
WMI_SERVICE_11AC, len);
SVCMAP(WMI_10_4_SERVICE_BLOCKACK,
WMI_SERVICE_BLOCKACK, len);
SVCMAP(WMI_10_4_SERVICE_PHYERR,
WMI_SERVICE_PHYERR, len);
SVCMAP(WMI_10_4_SERVICE_BCN_FILTER,
WMI_SERVICE_BCN_FILTER, len);
SVCMAP(WMI_10_4_SERVICE_RTT,
WMI_SERVICE_RTT, len);
SVCMAP(WMI_10_4_SERVICE_RATECTRL,
WMI_SERVICE_RATECTRL, len);
SVCMAP(WMI_10_4_SERVICE_WOW,
WMI_SERVICE_WOW, len);
SVCMAP(WMI_10_4_SERVICE_RATECTRL_CACHE,
WMI_SERVICE_RATECTRL_CACHE, len);
SVCMAP(WMI_10_4_SERVICE_IRAM_TIDS,
WMI_SERVICE_IRAM_TIDS, len);
SVCMAP(WMI_10_4_SERVICE_BURST,
WMI_SERVICE_BURST, len);
SVCMAP(WMI_10_4_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_GTK_OFFLOAD,
WMI_SERVICE_GTK_OFFLOAD, len);
SVCMAP(WMI_10_4_SERVICE_SCAN_SCH,
WMI_SERVICE_SCAN_SCH, len);
SVCMAP(WMI_10_4_SERVICE_CSA_OFFLOAD,
WMI_SERVICE_CSA_OFFLOAD, len);
SVCMAP(WMI_10_4_SERVICE_CHATTER,
WMI_SERVICE_CHATTER, len);
SVCMAP(WMI_10_4_SERVICE_COEX_FREQAVOID,
WMI_SERVICE_COEX_FREQAVOID, len);
SVCMAP(WMI_10_4_SERVICE_PACKET_POWER_SAVE,
WMI_SERVICE_PACKET_POWER_SAVE, len);
SVCMAP(WMI_10_4_SERVICE_FORCE_FW_HANG,
WMI_SERVICE_FORCE_FW_HANG, len);
SVCMAP(WMI_10_4_SERVICE_SMART_ANTENNA_HW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_GPIO,
WMI_SERVICE_GPIO, len);
SVCMAP(WMI_10_4_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG, len);
SVCMAP(WMI_10_4_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_VAR_AUTO_TRIG, len);
SVCMAP(WMI_10_4_SERVICE_STA_KEEP_ALIVE,
WMI_SERVICE_STA_KEEP_ALIVE, len);
SVCMAP(WMI_10_4_SERVICE_TX_ENCAP,
WMI_SERVICE_TX_ENCAP, len);
SVCMAP(WMI_10_4_SERVICE_AP_PS_DETECT_OUT_OF_SYNC,
WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC, len);
SVCMAP(WMI_10_4_SERVICE_EARLY_RX,
WMI_SERVICE_EARLY_RX, len);
SVCMAP(WMI_10_4_SERVICE_ENHANCED_PROXY_STA,
WMI_SERVICE_ENHANCED_PROXY_STA, len);
SVCMAP(WMI_10_4_SERVICE_TT,
WMI_SERVICE_TT, len);
SVCMAP(WMI_10_4_SERVICE_ATF,
WMI_SERVICE_ATF, len);
SVCMAP(WMI_10_4_SERVICE_PEER_CACHING,
WMI_SERVICE_PEER_CACHING, len);
SVCMAP(WMI_10_4_SERVICE_COEX_GPIO,
WMI_SERVICE_COEX_GPIO, len);
SVCMAP(WMI_10_4_SERVICE_AUX_SPECTRAL_INTF,
WMI_SERVICE_AUX_SPECTRAL_INTF, len);
SVCMAP(WMI_10_4_SERVICE_AUX_CHAN_LOAD_INTF,
WMI_SERVICE_AUX_CHAN_LOAD_INTF, len);
SVCMAP(WMI_10_4_SERVICE_BSS_CHANNEL_INFO_64,
WMI_SERVICE_BSS_CHANNEL_INFO_64, len);
SVCMAP(WMI_10_4_SERVICE_EXT_RES_CFG_SUPPORT,
WMI_SERVICE_EXT_RES_CFG_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_MESH_NON_11S,
WMI_SERVICE_MESH_NON_11S, len);
SVCMAP(WMI_10_4_SERVICE_RESTRT_CHNL_SUPPORT,
WMI_SERVICE_RESTRT_CHNL_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_PEER_STATS,
WMI_SERVICE_PEER_STATS, len);
SVCMAP(WMI_10_4_SERVICE_MESH_11S,
WMI_SERVICE_MESH_11S, len);
SVCMAP(WMI_10_4_SERVICE_PERIODIC_CHAN_STAT_SUPPORT,
WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_TX_MODE_PUSH_ONLY,
WMI_SERVICE_TX_MODE_PUSH_ONLY, len);
SVCMAP(WMI_10_4_SERVICE_TX_MODE_PUSH_PULL,
WMI_SERVICE_TX_MODE_PUSH_PULL, len);
SVCMAP(WMI_10_4_SERVICE_TX_MODE_DYNAMIC,
WMI_SERVICE_TX_MODE_DYNAMIC, len);
SVCMAP(WMI_10_4_SERVICE_VDEV_RX_FILTER,
WMI_SERVICE_VDEV_RX_FILTER, len);
SVCMAP(WMI_10_4_SERVICE_BTCOEX,
WMI_SERVICE_BTCOEX, len);
SVCMAP(WMI_10_4_SERVICE_CHECK_CAL_VERSION,
WMI_SERVICE_CHECK_CAL_VERSION, len);
SVCMAP(WMI_10_4_SERVICE_DBGLOG_WARN2,
WMI_SERVICE_DBGLOG_WARN2, len);
SVCMAP(WMI_10_4_SERVICE_BTCOEX_DUTY_CYCLE,
WMI_SERVICE_BTCOEX_DUTY_CYCLE, len);
SVCMAP(WMI_10_4_SERVICE_4_WIRE_COEX_SUPPORT,
WMI_SERVICE_4_WIRE_COEX_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_EXTENDED_NSS_SUPPORT,
WMI_SERVICE_EXTENDED_NSS_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_PROG_GPIO_BAND_SELECT,
WMI_SERVICE_PROG_GPIO_BAND_SELECT, len);
SVCMAP(WMI_10_4_SERVICE_SMART_LOGGING_SUPPORT,
WMI_SERVICE_SMART_LOGGING_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_TDLS,
WMI_SERVICE_TDLS, len);
SVCMAP(WMI_10_4_SERVICE_TDLS_OFFCHAN,
WMI_SERVICE_TDLS_OFFCHAN, len);
SVCMAP(WMI_10_4_SERVICE_TDLS_UAPSD_BUFFER_STA,
WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, len);
SVCMAP(WMI_10_4_SERVICE_TDLS_UAPSD_SLEEP_STA,
WMI_SERVICE_TDLS_UAPSD_SLEEP_STA, len);
SVCMAP(WMI_10_4_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE,
WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE, len);
SVCMAP(WMI_10_4_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, len);
SVCMAP(WMI_10_4_SERVICE_TDLS_WIDER_BANDWIDTH,
WMI_SERVICE_TDLS_WIDER_BANDWIDTH, len);
SVCMAP(WMI_10_4_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS, len);
SVCMAP(WMI_10_4_SERVICE_HOST_DFS_CHECK_SUPPORT,
WMI_SERVICE_HOST_DFS_CHECK_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_TPC_STATS_FINAL,
WMI_SERVICE_TPC_STATS_FINAL, len);
SVCMAP(WMI_10_4_SERVICE_TX_DATA_ACK_RSSI,
WMI_SERVICE_TX_DATA_ACK_RSSI, len);
SVCMAP(WMI_10_4_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT,
WMI_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_VDEV_DISABLE_4_ADDR_SRC_LRN_SUPPORT,
WMI_SERVICE_VDEV_DISABLE_4_ADDR_SRC_LRN_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_RTT_RESPONDER_ROLE,
WMI_SERVICE_RTT_RESPONDER_ROLE, len);
SVCMAP(WMI_10_4_SERVICE_PER_PACKET_SW_ENCRYPT,
WMI_SERVICE_PER_PACKET_SW_ENCRYPT, len);
SVCMAP(WMI_10_4_SERVICE_REPORT_AIRTIME,
WMI_SERVICE_REPORT_AIRTIME, len);
SVCMAP(WMI_10_4_SERVICE_TX_PWR_PER_PEER,
WMI_SERVICE_TX_PWR_PER_PEER, len);
SVCMAP(WMI_10_4_SERVICE_RESET_CHIP,
WMI_SERVICE_RESET_CHIP, len);
SVCMAP(WMI_10_4_SERVICE_PEER_TID_CONFIGS_SUPPORT,
WMI_SERVICE_PEER_TID_CONFIGS_SUPPORT, len);
SVCMAP(WMI_10_4_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
WMI_SERVICE_PEER_TID_CONFIGS_SUPPORT, len);
}
#undef SVCMAP
struct wmi_mac_addr {
union {
u8 addr[6];
struct {
u32 word0;
u32 word1;
} __packed;
} __packed;
} __packed;
struct wmi_cmd_map {
u32 init_cmdid;
u32 start_scan_cmdid;
u32 stop_scan_cmdid;
u32 scan_chan_list_cmdid;
u32 scan_sch_prio_tbl_cmdid;
u32 scan_prob_req_oui_cmdid;
u32 pdev_set_regdomain_cmdid;
u32 pdev_set_channel_cmdid;
u32 pdev_set_param_cmdid;
u32 pdev_pktlog_enable_cmdid;
u32 pdev_pktlog_disable_cmdid;
u32 pdev_set_wmm_params_cmdid;
u32 pdev_set_ht_cap_ie_cmdid;
u32 pdev_set_vht_cap_ie_cmdid;
u32 pdev_set_dscp_tid_map_cmdid;
u32 pdev_set_quiet_mode_cmdid;
u32 pdev_green_ap_ps_enable_cmdid;
u32 pdev_get_tpc_config_cmdid;
u32 pdev_set_base_macaddr_cmdid;
u32 vdev_create_cmdid;
u32 vdev_delete_cmdid;
u32 vdev_start_request_cmdid;
u32 vdev_restart_request_cmdid;
u32 vdev_up_cmdid;
u32 vdev_stop_cmdid;
u32 vdev_down_cmdid;
u32 vdev_set_param_cmdid;
u32 vdev_install_key_cmdid;
u32 peer_create_cmdid;
u32 peer_delete_cmdid;
u32 peer_flush_tids_cmdid;
u32 peer_set_param_cmdid;
u32 peer_assoc_cmdid;
u32 peer_add_wds_entry_cmdid;
u32 peer_remove_wds_entry_cmdid;
u32 peer_mcast_group_cmdid;
u32 bcn_tx_cmdid;
u32 pdev_send_bcn_cmdid;
u32 bcn_tmpl_cmdid;
u32 bcn_filter_rx_cmdid;
u32 prb_req_filter_rx_cmdid;
u32 mgmt_tx_cmdid;
u32 mgmt_tx_send_cmdid;
u32 prb_tmpl_cmdid;
u32 addba_clear_resp_cmdid;
u32 addba_send_cmdid;
u32 addba_status_cmdid;
u32 delba_send_cmdid;
u32 addba_set_resp_cmdid;
u32 send_singleamsdu_cmdid;
u32 sta_powersave_mode_cmdid;
u32 sta_powersave_param_cmdid;
u32 sta_mimo_ps_mode_cmdid;
u32 pdev_dfs_enable_cmdid;
u32 pdev_dfs_disable_cmdid;
u32 roam_scan_mode;
u32 roam_scan_rssi_threshold;
u32 roam_scan_period;
u32 roam_scan_rssi_change_threshold;
u32 roam_ap_profile;
u32 ofl_scan_add_ap_profile;
u32 ofl_scan_remove_ap_profile;
u32 ofl_scan_period;
u32 p2p_dev_set_device_info;
u32 p2p_dev_set_discoverability;
u32 p2p_go_set_beacon_ie;
u32 p2p_go_set_probe_resp_ie;
u32 p2p_set_vendor_ie_data_cmdid;
u32 ap_ps_peer_param_cmdid;
u32 ap_ps_peer_uapsd_coex_cmdid;
u32 peer_rate_retry_sched_cmdid;
u32 wlan_profile_trigger_cmdid;
u32 wlan_profile_set_hist_intvl_cmdid;
u32 wlan_profile_get_profile_data_cmdid;
u32 wlan_profile_enable_profile_id_cmdid;
u32 wlan_profile_list_profile_id_cmdid;
u32 pdev_suspend_cmdid;
u32 pdev_resume_cmdid;
u32 add_bcn_filter_cmdid;
u32 rmv_bcn_filter_cmdid;
u32 wow_add_wake_pattern_cmdid;
u32 wow_del_wake_pattern_cmdid;
u32 wow_enable_disable_wake_event_cmdid;
u32 wow_enable_cmdid;
u32 wow_hostwakeup_from_sleep_cmdid;
u32 rtt_measreq_cmdid;
u32 rtt_tsf_cmdid;
u32 vdev_spectral_scan_configure_cmdid;
u32 vdev_spectral_scan_enable_cmdid;
u32 request_stats_cmdid;
u32 request_peer_stats_info_cmdid;
u32 set_arp_ns_offload_cmdid;
u32 network_list_offload_config_cmdid;
u32 gtk_offload_cmdid;
u32 csa_offload_enable_cmdid;
u32 csa_offload_chanswitch_cmdid;
u32 chatter_set_mode_cmdid;
u32 peer_tid_addba_cmdid;
u32 peer_tid_delba_cmdid;
u32 sta_dtim_ps_method_cmdid;
u32 sta_uapsd_auto_trig_cmdid;
u32 sta_keepalive_cmd;
u32 echo_cmdid;
u32 pdev_utf_cmdid;
u32 dbglog_cfg_cmdid;
u32 pdev_qvit_cmdid;
u32 pdev_ftm_intg_cmdid;
u32 vdev_set_keepalive_cmdid;
u32 vdev_get_keepalive_cmdid;
u32 force_fw_hang_cmdid;
u32 gpio_config_cmdid;
u32 gpio_output_cmdid;
u32 pdev_get_temperature_cmdid;
u32 vdev_set_wmm_params_cmdid;
u32 tdls_set_state_cmdid;
u32 tdls_peer_update_cmdid;
u32 adaptive_qcs_cmdid;
u32 scan_update_request_cmdid;
u32 vdev_standby_response_cmdid;
u32 vdev_resume_response_cmdid;
u32 wlan_peer_caching_add_peer_cmdid;
u32 wlan_peer_caching_evict_peer_cmdid;
u32 wlan_peer_caching_restore_peer_cmdid;
u32 wlan_peer_caching_print_all_peers_info_cmdid;
u32 peer_update_wds_entry_cmdid;
u32 peer_add_proxy_sta_entry_cmdid;
u32 rtt_keepalive_cmdid;
u32 oem_req_cmdid;
u32 nan_cmdid;
u32 vdev_ratemask_cmdid;
u32 qboost_cfg_cmdid;
u32 pdev_smart_ant_enable_cmdid;
u32 pdev_smart_ant_set_rx_antenna_cmdid;
u32 peer_smart_ant_set_tx_antenna_cmdid;
u32 peer_smart_ant_set_train_info_cmdid;
u32 peer_smart_ant_set_node_config_ops_cmdid;
u32 pdev_set_antenna_switch_table_cmdid;
u32 pdev_set_ctl_table_cmdid;
u32 pdev_set_mimogain_table_cmdid;
u32 pdev_ratepwr_table_cmdid;
u32 pdev_ratepwr_chainmsk_table_cmdid;
u32 pdev_fips_cmdid;
u32 tt_set_conf_cmdid;
u32 fwtest_cmdid;
u32 vdev_atf_request_cmdid;
u32 peer_atf_request_cmdid;
u32 pdev_get_ani_cck_config_cmdid;
u32 pdev_get_ani_ofdm_config_cmdid;
u32 pdev_reserve_ast_entry_cmdid;
u32 pdev_get_nfcal_power_cmdid;
u32 pdev_get_tpc_cmdid;
u32 pdev_get_ast_info_cmdid;
u32 vdev_set_dscp_tid_map_cmdid;
u32 pdev_get_info_cmdid;
u32 vdev_get_info_cmdid;
u32 vdev_filter_neighbor_rx_packets_cmdid;
u32 mu_cal_start_cmdid;
u32 set_cca_params_cmdid;
u32 pdev_bss_chan_info_request_cmdid;
u32 pdev_enable_adaptive_cca_cmdid;
u32 ext_resource_cfg_cmdid;
u32 vdev_set_ie_cmdid;
u32 set_lteu_config_cmdid;
u32 atf_ssid_grouping_request_cmdid;
u32 peer_atf_ext_request_cmdid;
u32 set_periodic_channel_stats_cfg_cmdid;
u32 peer_bwf_request_cmdid;
u32 btcoex_cfg_cmdid;
u32 peer_tx_mu_txmit_count_cmdid;
u32 peer_tx_mu_txmit_rstcnt_cmdid;
u32 peer_gid_userpos_list_cmdid;
u32 pdev_check_cal_version_cmdid;
u32 coex_version_cfg_cmid;
u32 pdev_get_rx_filter_cmdid;
u32 pdev_extended_nss_cfg_cmdid;
u32 vdev_set_scan_nac_rssi_cmdid;
u32 prog_gpio_band_select_cmdid;
u32 config_smart_logging_cmdid;
u32 debug_fatal_condition_cmdid;
u32 get_tsf_timer_cmdid;
u32 pdev_get_tpc_table_cmdid;
u32 vdev_sifs_trigger_time_cmdid;
u32 pdev_wds_entry_list_cmdid;
u32 tdls_set_offchan_mode_cmdid;
u32 radar_found_cmdid;
u32 set_bb_timing_cmdid;
u32 per_peer_per_tid_config_cmdid;
};
enum wmi_cmd_group {
WMI_GRP_START = 0x3,
WMI_GRP_SCAN = WMI_GRP_START,
WMI_GRP_PDEV,
WMI_GRP_VDEV,
WMI_GRP_PEER,
WMI_GRP_MGMT,
WMI_GRP_BA_NEG,
WMI_GRP_STA_PS,
WMI_GRP_DFS,
WMI_GRP_ROAM,
WMI_GRP_OFL_SCAN,
WMI_GRP_P2P,
WMI_GRP_AP_PS,
WMI_GRP_RATE_CTRL,
WMI_GRP_PROFILE,
WMI_GRP_SUSPEND,
WMI_GRP_BCN_FILTER,
WMI_GRP_WOW,
WMI_GRP_RTT,
WMI_GRP_SPECTRAL,
WMI_GRP_STATS,
WMI_GRP_ARP_NS_OFL,
WMI_GRP_NLO_OFL,
WMI_GRP_GTK_OFL,
WMI_GRP_CSA_OFL,
WMI_GRP_CHATTER,
WMI_GRP_TID_ADDBA,
WMI_GRP_MISC,
WMI_GRP_GPIO,
};
#define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1)
#define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
#define WMI_CMD_UNSUPPORTED 0
enum wmi_cmd_id {
WMI_INIT_CMDID = 0x1,
WMI_START_SCAN_CMDID = WMI_CMD_GRP(WMI_GRP_SCAN),
WMI_STOP_SCAN_CMDID,
WMI_SCAN_CHAN_LIST_CMDID,
WMI_SCAN_SCH_PRIO_TBL_CMDID,
WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_CMD_GRP(WMI_GRP_PDEV),
WMI_PDEV_SET_CHANNEL_CMDID,
WMI_PDEV_SET_PARAM_CMDID,
WMI_PDEV_PKTLOG_ENABLE_CMDID,
WMI_PDEV_PKTLOG_DISABLE_CMDID,
WMI_PDEV_SET_WMM_PARAMS_CMDID,
WMI_PDEV_SET_HT_CAP_IE_CMDID,
WMI_PDEV_SET_VHT_CAP_IE_CMDID,
WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
WMI_PDEV_SET_QUIET_MODE_CMDID,
WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
WMI_PDEV_GET_TPC_CONFIG_CMDID,
WMI_PDEV_SET_BASE_MACADDR_CMDID,
WMI_VDEV_CREATE_CMDID = WMI_CMD_GRP(WMI_GRP_VDEV),
WMI_VDEV_DELETE_CMDID,
WMI_VDEV_START_REQUEST_CMDID,
WMI_VDEV_RESTART_REQUEST_CMDID,
WMI_VDEV_UP_CMDID,
WMI_VDEV_STOP_CMDID,
WMI_VDEV_DOWN_CMDID,
WMI_VDEV_SET_PARAM_CMDID,
WMI_VDEV_INSTALL_KEY_CMDID,
WMI_PEER_CREATE_CMDID = WMI_CMD_GRP(WMI_GRP_PEER),
WMI_PEER_DELETE_CMDID,
WMI_PEER_FLUSH_TIDS_CMDID,
WMI_PEER_SET_PARAM_CMDID,
WMI_PEER_ASSOC_CMDID,
WMI_PEER_ADD_WDS_ENTRY_CMDID,
WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
WMI_PEER_MCAST_GROUP_CMDID,
WMI_BCN_TX_CMDID = WMI_CMD_GRP(WMI_GRP_MGMT),
WMI_PDEV_SEND_BCN_CMDID,
WMI_BCN_TMPL_CMDID,
WMI_BCN_FILTER_RX_CMDID,
WMI_PRB_REQ_FILTER_RX_CMDID,
WMI_MGMT_TX_CMDID,
WMI_PRB_TMPL_CMDID,
WMI_ADDBA_CLEAR_RESP_CMDID = WMI_CMD_GRP(WMI_GRP_BA_NEG),
WMI_ADDBA_SEND_CMDID,
WMI_ADDBA_STATUS_CMDID,
WMI_DELBA_SEND_CMDID,
WMI_ADDBA_SET_RESP_CMDID,
WMI_SEND_SINGLEAMSDU_CMDID,
WMI_STA_POWERSAVE_MODE_CMDID = WMI_CMD_GRP(WMI_GRP_STA_PS),
WMI_STA_POWERSAVE_PARAM_CMDID,
WMI_STA_MIMO_PS_MODE_CMDID,
WMI_PDEV_DFS_ENABLE_CMDID = WMI_CMD_GRP(WMI_GRP_DFS),
WMI_PDEV_DFS_DISABLE_CMDID,
WMI_ROAM_SCAN_MODE = WMI_CMD_GRP(WMI_GRP_ROAM),
WMI_ROAM_SCAN_RSSI_THRESHOLD,
WMI_ROAM_SCAN_PERIOD,
WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
WMI_ROAM_AP_PROFILE,
WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_CMD_GRP(WMI_GRP_OFL_SCAN),
WMI_OFL_SCAN_REMOVE_AP_PROFILE,
WMI_OFL_SCAN_PERIOD,
WMI_P2P_DEV_SET_DEVICE_INFO = WMI_CMD_GRP(WMI_GRP_P2P),
WMI_P2P_DEV_SET_DISCOVERABILITY,
WMI_P2P_GO_SET_BEACON_IE,
WMI_P2P_GO_SET_PROBE_RESP_IE,
WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
WMI_AP_PS_PEER_PARAM_CMDID = WMI_CMD_GRP(WMI_GRP_AP_PS),
WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
WMI_PEER_RATE_RETRY_SCHED_CMDID =
WMI_CMD_GRP(WMI_GRP_RATE_CTRL),
WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_CMD_GRP(WMI_GRP_PROFILE),
WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
WMI_PDEV_SUSPEND_CMDID = WMI_CMD_GRP(WMI_GRP_SUSPEND),
WMI_PDEV_RESUME_CMDID,
WMI_ADD_BCN_FILTER_CMDID = WMI_CMD_GRP(WMI_GRP_BCN_FILTER),
WMI_RMV_BCN_FILTER_CMDID,
WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_CMD_GRP(WMI_GRP_WOW),
WMI_WOW_DEL_WAKE_PATTERN_CMDID,
WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
WMI_WOW_ENABLE_CMDID,
WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
WMI_RTT_MEASREQ_CMDID = WMI_CMD_GRP(WMI_GRP_RTT),
WMI_RTT_TSF_CMDID,
WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_CMD_GRP(WMI_GRP_SPECTRAL),
WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
WMI_REQUEST_STATS_CMDID = WMI_CMD_GRP(WMI_GRP_STATS),
WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_CMD_GRP(WMI_GRP_ARP_NS_OFL),
WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_CMD_GRP(WMI_GRP_NLO_OFL),
WMI_GTK_OFFLOAD_CMDID = WMI_CMD_GRP(WMI_GRP_GTK_OFL),
WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP(WMI_GRP_CSA_OFL),
WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
WMI_CHATTER_SET_MODE_CMDID = WMI_CMD_GRP(WMI_GRP_CHATTER),
WMI_PEER_TID_ADDBA_CMDID = WMI_CMD_GRP(WMI_GRP_TID_ADDBA),
WMI_PEER_TID_DELBA_CMDID,
WMI_STA_DTIM_PS_METHOD_CMDID,
WMI_STA_UAPSD_AUTO_TRIG_CMDID,
WMI_STA_KEEPALIVE_CMD,
WMI_ECHO_CMDID = WMI_CMD_GRP(WMI_GRP_MISC),
WMI_PDEV_UTF_CMDID,
WMI_DBGLOG_CFG_CMDID,
WMI_PDEV_QVIT_CMDID,
WMI_PDEV_FTM_INTG_CMDID,
WMI_VDEV_SET_KEEPALIVE_CMDID,
WMI_VDEV_GET_KEEPALIVE_CMDID,
WMI_FORCE_FW_HANG_CMDID,
WMI_GPIO_CONFIG_CMDID = WMI_CMD_GRP(WMI_GRP_GPIO),
WMI_GPIO_OUTPUT_CMDID,
};
enum wmi_event_id {
WMI_SERVICE_READY_EVENTID = 0x1,
WMI_READY_EVENTID,
WMI_SERVICE_AVAILABLE_EVENTID,
WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV),
WMI_CHAN_INFO_EVENTID,
WMI_PHYERR_EVENTID,
WMI_VDEV_START_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VDEV),
WMI_VDEV_STOPPED_EVENTID,
WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID,
WMI_PEER_STA_KICKOUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PEER),
WMI_MGMT_RX_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MGMT),
WMI_HOST_SWBA_EVENTID,
WMI_TBTTOFFSET_UPDATE_EVENTID,
WMI_TX_DELBA_COMPLETE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_BA_NEG),
WMI_TX_ADDBA_COMPLETE_EVENTID,
WMI_ROAM_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ROAM),
WMI_PROFILE_MATCH,
WMI_WOW_WAKEUP_HOST_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_WOW),
WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_RTT),
WMI_TSF_MEASUREMENT_REPORT_EVENTID,
WMI_RTT_ERROR_REPORT_EVENTID,
WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GTK_OFL),
WMI_GTK_REKEY_FAIL_EVENTID,
WMI_CSA_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CSA_OFL),
WMI_ECHO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MISC),
WMI_PDEV_UTF_EVENTID,
WMI_DEBUG_MESG_EVENTID,
WMI_UPDATE_STATS_EVENTID,
WMI_DEBUG_PRINT_EVENTID,
WMI_DCS_INTERFERENCE_EVENTID,
WMI_PDEV_QVIT_EVENTID,
WMI_WLAN_PROFILE_DATA_EVENTID,
WMI_PDEV_FTM_INTG_EVENTID,
WMI_WLAN_FREQ_AVOID_EVENTID,
WMI_VDEV_GET_KEEPALIVE_EVENTID,
WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO),
};
enum wmi_10x_cmd_id {
WMI_10X_START_CMDID = 0x9000,
WMI_10X_END_CMDID = 0x9FFF,
WMI_10X_INIT_CMDID,
WMI_10X_START_SCAN_CMDID = WMI_10X_START_CMDID,
WMI_10X_STOP_SCAN_CMDID,
WMI_10X_SCAN_CHAN_LIST_CMDID,
WMI_10X_ECHO_CMDID,
WMI_10X_PDEV_SET_REGDOMAIN_CMDID,
WMI_10X_PDEV_SET_CHANNEL_CMDID,
WMI_10X_PDEV_SET_PARAM_CMDID,
WMI_10X_PDEV_PKTLOG_ENABLE_CMDID,
WMI_10X_PDEV_PKTLOG_DISABLE_CMDID,
WMI_10X_PDEV_SET_WMM_PARAMS_CMDID,
WMI_10X_PDEV_SET_HT_CAP_IE_CMDID,
WMI_10X_PDEV_SET_VHT_CAP_IE_CMDID,
WMI_10X_PDEV_SET_BASE_MACADDR_CMDID,
WMI_10X_PDEV_SET_DSCP_TID_MAP_CMDID,
WMI_10X_PDEV_SET_QUIET_MODE_CMDID,
WMI_10X_PDEV_GREEN_AP_PS_ENABLE_CMDID,
WMI_10X_PDEV_GET_TPC_CONFIG_CMDID,
WMI_10X_VDEV_CREATE_CMDID,
WMI_10X_VDEV_DELETE_CMDID,
WMI_10X_VDEV_START_REQUEST_CMDID,
WMI_10X_VDEV_RESTART_REQUEST_CMDID,
WMI_10X_VDEV_UP_CMDID,
WMI_10X_VDEV_STOP_CMDID,
WMI_10X_VDEV_DOWN_CMDID,
WMI_10X_VDEV_STANDBY_RESPONSE_CMDID,
WMI_10X_VDEV_RESUME_RESPONSE_CMDID,
WMI_10X_VDEV_SET_PARAM_CMDID,
WMI_10X_VDEV_INSTALL_KEY_CMDID,
WMI_10X_PEER_CREATE_CMDID,
WMI_10X_PEER_DELETE_CMDID,
WMI_10X_PEER_FLUSH_TIDS_CMDID,
WMI_10X_PEER_SET_PARAM_CMDID,
WMI_10X_PEER_ASSOC_CMDID,
WMI_10X_PEER_ADD_WDS_ENTRY_CMDID,
WMI_10X_PEER_REMOVE_WDS_ENTRY_CMDID,
WMI_10X_PEER_MCAST_GROUP_CMDID,
WMI_10X_BCN_TX_CMDID,
WMI_10X_BCN_PRB_TMPL_CMDID,
WMI_10X_BCN_FILTER_RX_CMDID,
WMI_10X_PRB_REQ_FILTER_RX_CMDID,
WMI_10X_MGMT_TX_CMDID,
WMI_10X_ADDBA_CLEAR_RESP_CMDID,
WMI_10X_ADDBA_SEND_CMDID,
WMI_10X_ADDBA_STATUS_CMDID,
WMI_10X_DELBA_SEND_CMDID,
WMI_10X_ADDBA_SET_RESP_CMDID,
WMI_10X_SEND_SINGLEAMSDU_CMDID,
WMI_10X_STA_POWERSAVE_MODE_CMDID,
WMI_10X_STA_POWERSAVE_PARAM_CMDID,
WMI_10X_STA_MIMO_PS_MODE_CMDID,
WMI_10X_DBGLOG_CFG_CMDID,
WMI_10X_PDEV_DFS_ENABLE_CMDID,
WMI_10X_PDEV_DFS_DISABLE_CMDID,
WMI_10X_PDEV_QVIT_CMDID,
WMI_10X_ROAM_SCAN_MODE,
WMI_10X_ROAM_SCAN_RSSI_THRESHOLD,
WMI_10X_ROAM_SCAN_PERIOD,
WMI_10X_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
WMI_10X_ROAM_AP_PROFILE,
WMI_10X_OFL_SCAN_ADD_AP_PROFILE,
WMI_10X_OFL_SCAN_REMOVE_AP_PROFILE,
WMI_10X_OFL_SCAN_PERIOD,
WMI_10X_P2P_DEV_SET_DEVICE_INFO,
WMI_10X_P2P_DEV_SET_DISCOVERABILITY,
WMI_10X_P2P_GO_SET_BEACON_IE,
WMI_10X_P2P_GO_SET_PROBE_RESP_IE,
WMI_10X_AP_PS_PEER_PARAM_CMDID,
WMI_10X_AP_PS_PEER_UAPSD_COEX_CMDID,
WMI_10X_PEER_RATE_RETRY_SCHED_CMDID,
WMI_10X_WLAN_PROFILE_TRIGGER_CMDID,
WMI_10X_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
WMI_10X_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
WMI_10X_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
WMI_10X_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
WMI_10X_PDEV_SUSPEND_CMDID,
WMI_10X_PDEV_RESUME_CMDID,
WMI_10X_ADD_BCN_FILTER_CMDID,
WMI_10X_RMV_BCN_FILTER_CMDID,
WMI_10X_WOW_ADD_WAKE_PATTERN_CMDID,
WMI_10X_WOW_DEL_WAKE_PATTERN_CMDID,
WMI_10X_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
WMI_10X_WOW_ENABLE_CMDID,
WMI_10X_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
WMI_10X_RTT_MEASREQ_CMDID,
WMI_10X_RTT_TSF_CMDID,
WMI_10X_PDEV_SEND_BCN_CMDID,
WMI_10X_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID,
WMI_10X_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
WMI_10X_REQUEST_STATS_CMDID,
WMI_10X_GPIO_CONFIG_CMDID,
WMI_10X_GPIO_OUTPUT_CMDID,
WMI_10X_PDEV_UTF_CMDID = WMI_10X_END_CMDID - 1,
};
enum wmi_10x_event_id {
WMI_10X_SERVICE_READY_EVENTID = 0x8000,
WMI_10X_READY_EVENTID,
WMI_10X_START_EVENTID = 0x9000,
WMI_10X_END_EVENTID = 0x9FFF,
WMI_10X_SCAN_EVENTID = WMI_10X_START_EVENTID,
WMI_10X_ECHO_EVENTID,
WMI_10X_DEBUG_MESG_EVENTID,
WMI_10X_UPDATE_STATS_EVENTID,
WMI_10X_INST_RSSI_STATS_EVENTID,
WMI_10X_VDEV_START_RESP_EVENTID,
WMI_10X_VDEV_STANDBY_REQ_EVENTID,
WMI_10X_VDEV_RESUME_REQ_EVENTID,
WMI_10X_VDEV_STOPPED_EVENTID,
WMI_10X_PEER_STA_KICKOUT_EVENTID,
WMI_10X_HOST_SWBA_EVENTID,
WMI_10X_TBTTOFFSET_UPDATE_EVENTID,
WMI_10X_MGMT_RX_EVENTID,
WMI_10X_CHAN_INFO_EVENTID,
WMI_10X_PHYERR_EVENTID,
WMI_10X_ROAM_EVENTID,
WMI_10X_PROFILE_MATCH,
WMI_10X_DEBUG_PRINT_EVENTID,
WMI_10X_PDEV_QVIT_EVENTID,
WMI_10X_WLAN_PROFILE_DATA_EVENTID,
WMI_10X_RTT_MEASUREMENT_REPORT_EVENTID,
WMI_10X_TSF_MEASUREMENT_REPORT_EVENTID,
WMI_10X_RTT_ERROR_REPORT_EVENTID,
WMI_10X_WOW_WAKEUP_HOST_EVENTID,
WMI_10X_DCS_INTERFERENCE_EVENTID,
WMI_10X_PDEV_TPC_CONFIG_EVENTID,
WMI_10X_GPIO_INPUT_EVENTID,
WMI_10X_PDEV_UTF_EVENTID = WMI_10X_END_EVENTID - 1,
};
enum wmi_10_2_cmd_id {
WMI_10_2_START_CMDID = 0x9000,
WMI_10_2_END_CMDID = 0x9FFF,
WMI_10_2_INIT_CMDID,
WMI_10_2_START_SCAN_CMDID = WMI_10_2_START_CMDID,
WMI_10_2_STOP_SCAN_CMDID,
WMI_10_2_SCAN_CHAN_LIST_CMDID,
WMI_10_2_ECHO_CMDID,
WMI_10_2_PDEV_SET_REGDOMAIN_CMDID,
WMI_10_2_PDEV_SET_CHANNEL_CMDID,
WMI_10_2_PDEV_SET_PARAM_CMDID,
WMI_10_2_PDEV_PKTLOG_ENABLE_CMDID,
WMI_10_2_PDEV_PKTLOG_DISABLE_CMDID,
WMI_10_2_PDEV_SET_WMM_PARAMS_CMDID,
WMI_10_2_PDEV_SET_HT_CAP_IE_CMDID,
WMI_10_2_PDEV_SET_VHT_CAP_IE_CMDID,
WMI_10_2_PDEV_SET_BASE_MACADDR_CMDID,
WMI_10_2_PDEV_SET_QUIET_MODE_CMDID,
WMI_10_2_PDEV_GREEN_AP_PS_ENABLE_CMDID,
WMI_10_2_PDEV_GET_TPC_CONFIG_CMDID,
WMI_10_2_VDEV_CREATE_CMDID,
WMI_10_2_VDEV_DELETE_CMDID,
WMI_10_2_VDEV_START_REQUEST_CMDID,
WMI_10_2_VDEV_RESTART_REQUEST_CMDID,
WMI_10_2_VDEV_UP_CMDID,
WMI_10_2_VDEV_STOP_CMDID,
WMI_10_2_VDEV_DOWN_CMDID,
WMI_10_2_VDEV_STANDBY_RESPONSE_CMDID,
WMI_10_2_VDEV_RESUME_RESPONSE_CMDID,
WMI_10_2_VDEV_SET_PARAM_CMDID,
WMI_10_2_VDEV_INSTALL_KEY_CMDID,
WMI_10_2_VDEV_SET_DSCP_TID_MAP_CMDID,
WMI_10_2_PEER_CREATE_CMDID,
WMI_10_2_PEER_DELETE_CMDID,
WMI_10_2_PEER_FLUSH_TIDS_CMDID,
WMI_10_2_PEER_SET_PARAM_CMDID,
WMI_10_2_PEER_ASSOC_CMDID,
WMI_10_2_PEER_ADD_WDS_ENTRY_CMDID,
WMI_10_2_PEER_UPDATE_WDS_ENTRY_CMDID,
WMI_10_2_PEER_REMOVE_WDS_ENTRY_CMDID,
WMI_10_2_PEER_MCAST_GROUP_CMDID,
WMI_10_2_BCN_TX_CMDID,
WMI_10_2_BCN_PRB_TMPL_CMDID,
WMI_10_2_BCN_FILTER_RX_CMDID,
WMI_10_2_PRB_REQ_FILTER_RX_CMDID,
WMI_10_2_MGMT_TX_CMDID,
WMI_10_2_ADDBA_CLEAR_RESP_CMDID,
WMI_10_2_ADDBA_SEND_CMDID,
WMI_10_2_ADDBA_STATUS_CMDID,
WMI_10_2_DELBA_SEND_CMDID,
WMI_10_2_ADDBA_SET_RESP_CMDID,
WMI_10_2_SEND_SINGLEAMSDU_CMDID,
WMI_10_2_STA_POWERSAVE_MODE_CMDID,
WMI_10_2_STA_POWERSAVE_PARAM_CMDID,
WMI_10_2_STA_MIMO_PS_MODE_CMDID,
WMI_10_2_DBGLOG_CFG_CMDID,
WMI_10_2_PDEV_DFS_ENABLE_CMDID,
WMI_10_2_PDEV_DFS_DISABLE_CMDID,
WMI_10_2_PDEV_QVIT_CMDID,
WMI_10_2_ROAM_SCAN_MODE,
WMI_10_2_ROAM_SCAN_RSSI_THRESHOLD,
WMI_10_2_ROAM_SCAN_PERIOD,
WMI_10_2_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
WMI_10_2_ROAM_AP_PROFILE,
WMI_10_2_OFL_SCAN_ADD_AP_PROFILE,
WMI_10_2_OFL_SCAN_REMOVE_AP_PROFILE,
WMI_10_2_OFL_SCAN_PERIOD,
WMI_10_2_P2P_DEV_SET_DEVICE_INFO,
WMI_10_2_P2P_DEV_SET_DISCOVERABILITY,
WMI_10_2_P2P_GO_SET_BEACON_IE,
WMI_10_2_P2P_GO_SET_PROBE_RESP_IE,
WMI_10_2_AP_PS_PEER_PARAM_CMDID,
WMI_10_2_AP_PS_PEER_UAPSD_COEX_CMDID,
WMI_10_2_PEER_RATE_RETRY_SCHED_CMDID,
WMI_10_2_WLAN_PROFILE_TRIGGER_CMDID,
WMI_10_2_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
WMI_10_2_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
WMI_10_2_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
WMI_10_2_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
WMI_10_2_PDEV_SUSPEND_CMDID,
WMI_10_2_PDEV_RESUME_CMDID,
WMI_10_2_ADD_BCN_FILTER_CMDID,
WMI_10_2_RMV_BCN_FILTER_CMDID,
WMI_10_2_WOW_ADD_WAKE_PATTERN_CMDID,
WMI_10_2_WOW_DEL_WAKE_PATTERN_CMDID,
WMI_10_2_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
WMI_10_2_WOW_ENABLE_CMDID,
WMI_10_2_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
WMI_10_2_RTT_MEASREQ_CMDID,
WMI_10_2_RTT_TSF_CMDID,
WMI_10_2_RTT_KEEPALIVE_CMDID,
WMI_10_2_PDEV_SEND_BCN_CMDID,
WMI_10_2_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID,
WMI_10_2_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
WMI_10_2_REQUEST_STATS_CMDID,
WMI_10_2_GPIO_CONFIG_CMDID,
WMI_10_2_GPIO_OUTPUT_CMDID,
WMI_10_2_VDEV_RATEMASK_CMDID,
WMI_10_2_PDEV_SMART_ANT_ENABLE_CMDID,
WMI_10_2_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
WMI_10_2_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
WMI_10_2_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
WMI_10_2_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
WMI_10_2_FORCE_FW_HANG_CMDID,
WMI_10_2_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
WMI_10_2_PDEV_SET_CTL_TABLE_CMDID,
WMI_10_2_PDEV_SET_MIMOGAIN_TABLE_CMDID,
WMI_10_2_PDEV_RATEPWR_TABLE_CMDID,
WMI_10_2_PDEV_RATEPWR_CHAINMSK_TABLE_CMDID,
WMI_10_2_PDEV_GET_INFO,
WMI_10_2_VDEV_GET_INFO,
WMI_10_2_VDEV_ATF_REQUEST_CMDID,
WMI_10_2_PEER_ATF_REQUEST_CMDID,
WMI_10_2_PDEV_GET_TEMPERATURE_CMDID,
WMI_10_2_MU_CAL_START_CMDID,
WMI_10_2_SET_LTEU_CONFIG_CMDID,
WMI_10_2_SET_CCA_PARAMS,
WMI_10_2_PDEV_BSS_CHAN_INFO_REQUEST_CMDID,
WMI_10_2_FWTEST_CMDID,
WMI_10_2_PDEV_SET_BB_TIMING_CONFIG_CMDID,
WMI_10_2_PDEV_UTF_CMDID = WMI_10_2_END_CMDID - 1,
};
enum wmi_10_2_event_id {
WMI_10_2_SERVICE_READY_EVENTID = 0x8000,
WMI_10_2_READY_EVENTID,
WMI_10_2_DEBUG_MESG_EVENTID,
WMI_10_2_START_EVENTID = 0x9000,
WMI_10_2_END_EVENTID = 0x9FFF,
WMI_10_2_SCAN_EVENTID = WMI_10_2_START_EVENTID,
WMI_10_2_ECHO_EVENTID,
WMI_10_2_UPDATE_STATS_EVENTID,
WMI_10_2_INST_RSSI_STATS_EVENTID,
WMI_10_2_VDEV_START_RESP_EVENTID,
WMI_10_2_VDEV_STANDBY_REQ_EVENTID,
WMI_10_2_VDEV_RESUME_REQ_EVENTID,
WMI_10_2_VDEV_STOPPED_EVENTID,
WMI_10_2_PEER_STA_KICKOUT_EVENTID,
WMI_10_2_HOST_SWBA_EVENTID,
WMI_10_2_TBTTOFFSET_UPDATE_EVENTID,
WMI_10_2_MGMT_RX_EVENTID,
WMI_10_2_CHAN_INFO_EVENTID,
WMI_10_2_PHYERR_EVENTID,
WMI_10_2_ROAM_EVENTID,
WMI_10_2_PROFILE_MATCH,
WMI_10_2_DEBUG_PRINT_EVENTID,
WMI_10_2_PDEV_QVIT_EVENTID,
WMI_10_2_WLAN_PROFILE_DATA_EVENTID,
WMI_10_2_RTT_MEASUREMENT_REPORT_EVENTID,
WMI_10_2_TSF_MEASUREMENT_REPORT_EVENTID,
WMI_10_2_RTT_ERROR_REPORT_EVENTID,
WMI_10_2_RTT_KEEPALIVE_EVENTID,
WMI_10_2_WOW_WAKEUP_HOST_EVENTID,
WMI_10_2_DCS_INTERFERENCE_EVENTID,
WMI_10_2_PDEV_TPC_CONFIG_EVENTID,
WMI_10_2_GPIO_INPUT_EVENTID,
WMI_10_2_PEER_RATECODE_LIST_EVENTID,
WMI_10_2_GENERIC_BUFFER_EVENTID,
WMI_10_2_MCAST_BUF_RELEASE_EVENTID,
WMI_10_2_MCAST_LIST_AGEOUT_EVENTID,
WMI_10_2_WDS_PEER_EVENTID,
WMI_10_2_PEER_STA_PS_STATECHG_EVENTID,
WMI_10_2_PDEV_TEMPERATURE_EVENTID,
WMI_10_2_MU_REPORT_EVENTID,
WMI_10_2_PDEV_BSS_CHAN_INFO_EVENTID,
WMI_10_2_PDEV_UTF_EVENTID = WMI_10_2_END_EVENTID - 1,
};
enum wmi_10_4_cmd_id {
WMI_10_4_START_CMDID = 0x9000,
WMI_10_4_END_CMDID = 0x9FFF,
WMI_10_4_INIT_CMDID,
WMI_10_4_START_SCAN_CMDID = WMI_10_4_START_CMDID,
WMI_10_4_STOP_SCAN_CMDID,
WMI_10_4_SCAN_CHAN_LIST_CMDID,
WMI_10_4_SCAN_SCH_PRIO_TBL_CMDID,
WMI_10_4_SCAN_UPDATE_REQUEST_CMDID,
WMI_10_4_ECHO_CMDID,
WMI_10_4_PDEV_SET_REGDOMAIN_CMDID,
WMI_10_4_PDEV_SET_CHANNEL_CMDID,
WMI_10_4_PDEV_SET_PARAM_CMDID,
WMI_10_4_PDEV_PKTLOG_ENABLE_CMDID,
WMI_10_4_PDEV_PKTLOG_DISABLE_CMDID,
WMI_10_4_PDEV_SET_WMM_PARAMS_CMDID,
WMI_10_4_PDEV_SET_HT_CAP_IE_CMDID,
WMI_10_4_PDEV_SET_VHT_CAP_IE_CMDID,
WMI_10_4_PDEV_SET_BASE_MACADDR_CMDID,
WMI_10_4_PDEV_SET_DSCP_TID_MAP_CMDID,
WMI_10_4_PDEV_SET_QUIET_MODE_CMDID,
WMI_10_4_PDEV_GREEN_AP_PS_ENABLE_CMDID,
WMI_10_4_PDEV_GET_TPC_CONFIG_CMDID,
WMI_10_4_VDEV_CREATE_CMDID,
WMI_10_4_VDEV_DELETE_CMDID,
WMI_10_4_VDEV_START_REQUEST_CMDID,
WMI_10_4_VDEV_RESTART_REQUEST_CMDID,
WMI_10_4_VDEV_UP_CMDID,
WMI_10_4_VDEV_STOP_CMDID,
WMI_10_4_VDEV_DOWN_CMDID,
WMI_10_4_VDEV_STANDBY_RESPONSE_CMDID,
WMI_10_4_VDEV_RESUME_RESPONSE_CMDID,
WMI_10_4_VDEV_SET_PARAM_CMDID,
WMI_10_4_VDEV_INSTALL_KEY_CMDID,
WMI_10_4_WLAN_PEER_CACHING_ADD_PEER_CMDID,
WMI_10_4_WLAN_PEER_CACHING_EVICT_PEER_CMDID,
WMI_10_4_WLAN_PEER_CACHING_RESTORE_PEER_CMDID,
WMI_10_4_WLAN_PEER_CACHING_PRINT_ALL_PEERS_INFO_CMDID,
WMI_10_4_PEER_CREATE_CMDID,
WMI_10_4_PEER_DELETE_CMDID,
WMI_10_4_PEER_FLUSH_TIDS_CMDID,
WMI_10_4_PEER_SET_PARAM_CMDID,
WMI_10_4_PEER_ASSOC_CMDID,
WMI_10_4_PEER_ADD_WDS_ENTRY_CMDID,
WMI_10_4_PEER_UPDATE_WDS_ENTRY_CMDID,
WMI_10_4_PEER_REMOVE_WDS_ENTRY_CMDID,
WMI_10_4_PEER_ADD_PROXY_STA_ENTRY_CMDID,
WMI_10_4_PEER_MCAST_GROUP_CMDID,
WMI_10_4_BCN_TX_CMDID,
WMI_10_4_PDEV_SEND_BCN_CMDID,
WMI_10_4_BCN_PRB_TMPL_CMDID,
WMI_10_4_BCN_FILTER_RX_CMDID,
WMI_10_4_PRB_REQ_FILTER_RX_CMDID,
WMI_10_4_MGMT_TX_CMDID,
WMI_10_4_PRB_TMPL_CMDID,
WMI_10_4_ADDBA_CLEAR_RESP_CMDID,
WMI_10_4_ADDBA_SEND_CMDID,
WMI_10_4_ADDBA_STATUS_CMDID,
WMI_10_4_DELBA_SEND_CMDID,
WMI_10_4_ADDBA_SET_RESP_CMDID,
WMI_10_4_SEND_SINGLEAMSDU_CMDID,
WMI_10_4_STA_POWERSAVE_MODE_CMDID,
WMI_10_4_STA_POWERSAVE_PARAM_CMDID,
WMI_10_4_STA_MIMO_PS_MODE_CMDID,
WMI_10_4_DBGLOG_CFG_CMDID,
WMI_10_4_PDEV_DFS_ENABLE_CMDID,
WMI_10_4_PDEV_DFS_DISABLE_CMDID,
WMI_10_4_PDEV_QVIT_CMDID,
WMI_10_4_ROAM_SCAN_MODE,
WMI_10_4_ROAM_SCAN_RSSI_THRESHOLD,
WMI_10_4_ROAM_SCAN_PERIOD,
WMI_10_4_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
WMI_10_4_ROAM_AP_PROFILE,
WMI_10_4_OFL_SCAN_ADD_AP_PROFILE,
WMI_10_4_OFL_SCAN_REMOVE_AP_PROFILE,
WMI_10_4_OFL_SCAN_PERIOD,
WMI_10_4_P2P_DEV_SET_DEVICE_INFO,
WMI_10_4_P2P_DEV_SET_DISCOVERABILITY,
WMI_10_4_P2P_GO_SET_BEACON_IE,
WMI_10_4_P2P_GO_SET_PROBE_RESP_IE,
WMI_10_4_P2P_SET_VENDOR_IE_DATA_CMDID,
WMI_10_4_AP_PS_PEER_PARAM_CMDID,
WMI_10_4_AP_PS_PEER_UAPSD_COEX_CMDID,
WMI_10_4_PEER_RATE_RETRY_SCHED_CMDID,
WMI_10_4_WLAN_PROFILE_TRIGGER_CMDID,
WMI_10_4_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
WMI_10_4_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
WMI_10_4_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
WMI_10_4_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
WMI_10_4_PDEV_SUSPEND_CMDID,
WMI_10_4_PDEV_RESUME_CMDID,
WMI_10_4_ADD_BCN_FILTER_CMDID,
WMI_10_4_RMV_BCN_FILTER_CMDID,
WMI_10_4_WOW_ADD_WAKE_PATTERN_CMDID,
WMI_10_4_WOW_DEL_WAKE_PATTERN_CMDID,
WMI_10_4_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
WMI_10_4_WOW_ENABLE_CMDID,
WMI_10_4_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
WMI_10_4_RTT_MEASREQ_CMDID,
WMI_10_4_RTT_TSF_CMDID,
WMI_10_4_RTT_KEEPALIVE_CMDID,
WMI_10_4_OEM_REQ_CMDID,
WMI_10_4_NAN_CMDID,
WMI_10_4_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID,
WMI_10_4_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
WMI_10_4_REQUEST_STATS_CMDID,
WMI_10_4_GPIO_CONFIG_CMDID,
WMI_10_4_GPIO_OUTPUT_CMDID,
WMI_10_4_VDEV_RATEMASK_CMDID,
WMI_10_4_CSA_OFFLOAD_ENABLE_CMDID,
WMI_10_4_GTK_OFFLOAD_CMDID,
WMI_10_4_QBOOST_CFG_CMDID,
WMI_10_4_CSA_OFFLOAD_CHANSWITCH_CMDID,
WMI_10_4_PDEV_SMART_ANT_ENABLE_CMDID,
WMI_10_4_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
WMI_10_4_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
WMI_10_4_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
WMI_10_4_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
WMI_10_4_VDEV_SET_KEEPALIVE_CMDID,
WMI_10_4_VDEV_GET_KEEPALIVE_CMDID,
WMI_10_4_FORCE_FW_HANG_CMDID,
WMI_10_4_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
WMI_10_4_PDEV_SET_CTL_TABLE_CMDID,
WMI_10_4_PDEV_SET_MIMOGAIN_TABLE_CMDID,
WMI_10_4_PDEV_RATEPWR_TABLE_CMDID,
WMI_10_4_PDEV_RATEPWR_CHAINMSK_TABLE_CMDID,
WMI_10_4_PDEV_FIPS_CMDID,
WMI_10_4_TT_SET_CONF_CMDID,
WMI_10_4_FWTEST_CMDID,
WMI_10_4_VDEV_ATF_REQUEST_CMDID,
WMI_10_4_PEER_ATF_REQUEST_CMDID,
WMI_10_4_PDEV_GET_ANI_CCK_CONFIG_CMDID,
WMI_10_4_PDEV_GET_ANI_OFDM_CONFIG_CMDID,
WMI_10_4_PDEV_RESERVE_AST_ENTRY_CMDID,
WMI_10_4_PDEV_GET_NFCAL_POWER_CMDID,
WMI_10_4_PDEV_GET_TPC_CMDID,
WMI_10_4_PDEV_GET_AST_INFO_CMDID,
WMI_10_4_VDEV_SET_DSCP_TID_MAP_CMDID,
WMI_10_4_PDEV_GET_TEMPERATURE_CMDID,
WMI_10_4_PDEV_GET_INFO_CMDID,
WMI_10_4_VDEV_GET_INFO_CMDID,
WMI_10_4_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID,
WMI_10_4_MU_CAL_START_CMDID,
WMI_10_4_SET_CCA_PARAMS_CMDID,
WMI_10_4_PDEV_BSS_CHAN_INFO_REQUEST_CMDID,
WMI_10_4_EXT_RESOURCE_CFG_CMDID,
WMI_10_4_VDEV_SET_IE_CMDID,
WMI_10_4_SET_LTEU_CONFIG_CMDID,
WMI_10_4_ATF_SSID_GROUPING_REQUEST_CMDID,
WMI_10_4_PEER_ATF_EXT_REQUEST_CMDID,
WMI_10_4_SET_PERIODIC_CHANNEL_STATS_CONFIG,
WMI_10_4_PEER_BWF_REQUEST_CMDID,
WMI_10_4_BTCOEX_CFG_CMDID,
WMI_10_4_PEER_TX_MU_TXMIT_COUNT_CMDID,
WMI_10_4_PEER_TX_MU_TXMIT_RSTCNT_CMDID,
WMI_10_4_PEER_GID_USERPOS_LIST_CMDID,
WMI_10_4_PDEV_CHECK_CAL_VERSION_CMDID,
WMI_10_4_COEX_VERSION_CFG_CMID,
WMI_10_4_PDEV_GET_RX_FILTER_CMDID,
WMI_10_4_PDEV_EXTENDED_NSS_CFG_CMDID,
WMI_10_4_VDEV_SET_SCAN_NAC_RSSI_CMDID,
WMI_10_4_PROG_GPIO_BAND_SELECT_CMDID,
WMI_10_4_CONFIG_SMART_LOGGING_CMDID,
WMI_10_4_DEBUG_FATAL_CONDITION_CMDID,
WMI_10_4_GET_TSF_TIMER_CMDID,
WMI_10_4_PDEV_GET_TPC_TABLE_CMDID,
WMI_10_4_VDEV_SIFS_TRIGGER_TIME_CMDID,
WMI_10_4_PDEV_WDS_ENTRY_LIST_CMDID,
WMI_10_4_TDLS_SET_STATE_CMDID,
WMI_10_4_TDLS_PEER_UPDATE_CMDID,
WMI_10_4_TDLS_SET_OFFCHAN_MODE_CMDID,
WMI_10_4_PDEV_SEND_FD_CMDID,
WMI_10_4_ENABLE_FILS_CMDID,
WMI_10_4_PDEV_SET_BRIDGE_MACADDR_CMDID,
WMI_10_4_ATF_GROUP_WMM_AC_CONFIG_REQUEST_CMDID,
WMI_10_4_RADAR_FOUND_CMDID,
WMI_10_4_PEER_CFR_CAPTURE_CMDID,
WMI_10_4_PER_PEER_PER_TID_CONFIG_CMDID,
WMI_10_4_PDEV_UTF_CMDID = WMI_10_4_END_CMDID - 1,
};
enum wmi_10_4_event_id {
WMI_10_4_SERVICE_READY_EVENTID = 0x8000,
WMI_10_4_READY_EVENTID,
WMI_10_4_DEBUG_MESG_EVENTID,
WMI_10_4_START_EVENTID = 0x9000,
WMI_10_4_END_EVENTID = 0x9FFF,
WMI_10_4_SCAN_EVENTID = WMI_10_4_START_EVENTID,
WMI_10_4_ECHO_EVENTID,
WMI_10_4_UPDATE_STATS_EVENTID,
WMI_10_4_INST_RSSI_STATS_EVENTID,
WMI_10_4_VDEV_START_RESP_EVENTID,
WMI_10_4_VDEV_STANDBY_REQ_EVENTID,
WMI_10_4_VDEV_RESUME_REQ_EVENTID,
WMI_10_4_VDEV_STOPPED_EVENTID,
WMI_10_4_PEER_STA_KICKOUT_EVENTID,
WMI_10_4_HOST_SWBA_EVENTID,
WMI_10_4_TBTTOFFSET_UPDATE_EVENTID,
WMI_10_4_MGMT_RX_EVENTID,
WMI_10_4_CHAN_INFO_EVENTID,
WMI_10_4_PHYERR_EVENTID,
WMI_10_4_ROAM_EVENTID,
WMI_10_4_PROFILE_MATCH,
WMI_10_4_DEBUG_PRINT_EVENTID,
WMI_10_4_PDEV_QVIT_EVENTID,
WMI_10_4_WLAN_PROFILE_DATA_EVENTID,
WMI_10_4_RTT_MEASUREMENT_REPORT_EVENTID,
WMI_10_4_TSF_MEASUREMENT_REPORT_EVENTID,
WMI_10_4_RTT_ERROR_REPORT_EVENTID,
WMI_10_4_RTT_KEEPALIVE_EVENTID,
WMI_10_4_OEM_CAPABILITY_EVENTID,
WMI_10_4_OEM_MEASUREMENT_REPORT_EVENTID,
WMI_10_4_OEM_ERROR_REPORT_EVENTID,
WMI_10_4_NAN_EVENTID,
WMI_10_4_WOW_WAKEUP_HOST_EVENTID,
WMI_10_4_GTK_OFFLOAD_STATUS_EVENTID,
WMI_10_4_GTK_REKEY_FAIL_EVENTID,
WMI_10_4_DCS_INTERFERENCE_EVENTID,
WMI_10_4_PDEV_TPC_CONFIG_EVENTID,
WMI_10_4_CSA_HANDLING_EVENTID,
WMI_10_4_GPIO_INPUT_EVENTID,
WMI_10_4_PEER_RATECODE_LIST_EVENTID,
WMI_10_4_GENERIC_BUFFER_EVENTID,
WMI_10_4_MCAST_BUF_RELEASE_EVENTID,
WMI_10_4_MCAST_LIST_AGEOUT_EVENTID,
WMI_10_4_VDEV_GET_KEEPALIVE_EVENTID,
WMI_10_4_WDS_PEER_EVENTID,
WMI_10_4_PEER_STA_PS_STATECHG_EVENTID,
WMI_10_4_PDEV_FIPS_EVENTID,
WMI_10_4_TT_STATS_EVENTID,
WMI_10_4_PDEV_CHANNEL_HOPPING_EVENTID,
WMI_10_4_PDEV_ANI_CCK_LEVEL_EVENTID,
WMI_10_4_PDEV_ANI_OFDM_LEVEL_EVENTID,
WMI_10_4_PDEV_RESERVE_AST_ENTRY_EVENTID,
WMI_10_4_PDEV_NFCAL_POWER_EVENTID,
WMI_10_4_PDEV_TPC_EVENTID,
WMI_10_4_PDEV_GET_AST_INFO_EVENTID,
WMI_10_4_PDEV_TEMPERATURE_EVENTID,
WMI_10_4_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID,
WMI_10_4_PDEV_BSS_CHAN_INFO_EVENTID,
WMI_10_4_MU_REPORT_EVENTID,
WMI_10_4_TX_DATA_TRAFFIC_CTRL_EVENTID,
WMI_10_4_PEER_TX_MU_TXMIT_COUNT_EVENTID,
WMI_10_4_PEER_GID_USERPOS_LIST_EVENTID,
WMI_10_4_PDEV_CHECK_CAL_VERSION_EVENTID,
WMI_10_4_ATF_PEER_STATS_EVENTID,
WMI_10_4_PDEV_GET_RX_FILTER_EVENTID,
WMI_10_4_NAC_RSSI_EVENTID,
WMI_10_4_DEBUG_FATAL_CONDITION_EVENTID,
WMI_10_4_GET_TSF_TIMER_RESP_EVENTID,
WMI_10_4_PDEV_TPC_TABLE_EVENTID,
WMI_10_4_PDEV_WDS_ENTRY_LIST_EVENTID,
WMI_10_4_TDLS_PEER_EVENTID,
WMI_10_4_HOST_SWFDA_EVENTID,
WMI_10_4_ESP_ESTIMATE_EVENTID,
WMI_10_4_DFS_STATUS_CHECK_EVENTID,
WMI_10_4_PDEV_UTF_EVENTID = WMI_10_4_END_EVENTID - 1,
};
enum wmi_phy_mode {
MODE_11A = 0,
MODE_11G = 1,
MODE_11B = 2,
MODE_11GONLY = 3,
MODE_11NA_HT20 = 4,
MODE_11NG_HT20 = 5,
MODE_11NA_HT40 = 6,
MODE_11NG_HT40 = 7,
MODE_11AC_VHT20 = 8,
MODE_11AC_VHT40 = 9,
MODE_11AC_VHT80 = 10,
MODE_11AC_VHT20_2G = 11,
MODE_11AC_VHT40_2G = 12,
MODE_11AC_VHT80_2G = 13,
MODE_11AC_VHT80_80 = 14,
MODE_11AC_VHT160 = 15,
MODE_UNKNOWN = 16,
MODE_MAX = 16
};
static inline const char *ath10k_wmi_phymode_str(enum wmi_phy_mode mode)
{
switch (mode) {
case MODE_11A:
return "11a";
case MODE_11G:
return "11g";
case MODE_11B:
return "11b";
case MODE_11GONLY:
return "11gonly";
case MODE_11NA_HT20:
return "11na-ht20";
case MODE_11NG_HT20:
return "11ng-ht20";
case MODE_11NA_HT40:
return "11na-ht40";
case MODE_11NG_HT40:
return "11ng-ht40";
case MODE_11AC_VHT20:
return "11ac-vht20";
case MODE_11AC_VHT40:
return "11ac-vht40";
case MODE_11AC_VHT80:
return "11ac-vht80";
case MODE_11AC_VHT160:
return "11ac-vht160";
case MODE_11AC_VHT80_80:
return "11ac-vht80+80";
case MODE_11AC_VHT20_2G:
return "11ac-vht20-2g";
case MODE_11AC_VHT40_2G:
return "11ac-vht40-2g";
case MODE_11AC_VHT80_2G:
return "11ac-vht80-2g";
case MODE_UNKNOWN:
break;
}
return "<unknown>";
}
#define WMI_CHAN_LIST_TAG 0x1
#define WMI_SSID_LIST_TAG 0x2
#define WMI_BSSID_LIST_TAG 0x3
#define WMI_IE_TAG 0x4
struct wmi_channel {
__le32 mhz;
__le32 band_center_freq1;
__le32 band_center_freq2;
union {
__le32 flags;
struct {
u8 mode;
} __packed;
} __packed;
union {
__le32 reginfo0;
struct {
u8 min_power;
u8 max_power;
u8 reg_power;
u8 reg_classid;
} __packed;
} __packed;
union {
__le32 reginfo1;
struct {
u8 antenna_max;
u8 max_tx_power;
} __packed;
} __packed;
} __packed;
struct wmi_channel_arg {
u32 freq;
u32 band_center_freq1;
u32 band_center_freq2;
bool passive;
bool allow_ibss;
bool allow_ht;
bool allow_vht;
bool ht40plus;
bool chan_radar;
u32 min_power;
u32 max_power;
u32 max_reg_power;
u32 max_antenna_gain;
u32 reg_class_id;
enum wmi_phy_mode mode;
};
enum wmi_channel_change_cause {
WMI_CHANNEL_CHANGE_CAUSE_NONE = 0,
WMI_CHANNEL_CHANGE_CAUSE_CSA,
};
#define WMI_CHAN_FLAG_HT40_PLUS (1 << 6)
#define WMI_CHAN_FLAG_PASSIVE (1 << 7)
#define WMI_CHAN_FLAG_ADHOC_ALLOWED (1 << 8)
#define WMI_CHAN_FLAG_AP_DISABLED (1 << 9)
#define WMI_CHAN_FLAG_DFS (1 << 10)
#define WMI_CHAN_FLAG_ALLOW_HT (1 << 11)
#define WMI_CHAN_FLAG_ALLOW_VHT (1 << 12)
#define WMI_CHANNEL_CHANGE_CAUSE_CSA (1 << 13)
#define WMI_CHAN_FLAG_DFS_CFREQ2 (1 << 15)
#define WMI_MAX_SPATIAL_STREAM 3
#define WMI_HT_CAP_ENABLED 0x0001
#define WMI_HT_CAP_HT20_SGI 0x0002
#define WMI_HT_CAP_DYNAMIC_SMPS 0x0004
#define WMI_HT_CAP_TX_STBC 0x0008
#define WMI_HT_CAP_TX_STBC_MASK_SHIFT 3
#define WMI_HT_CAP_RX_STBC 0x0030
#define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4
#define WMI_HT_CAP_LDPC 0x0040
#define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080
#define WMI_HT_CAP_MPDU_DENSITY 0x0700
#define WMI_HT_CAP_MPDU_DENSITY_MASK_SHIFT 8
#define WMI_HT_CAP_HT40_SGI 0x0800
#define WMI_HT_CAP_RX_LDPC 0x1000
#define WMI_HT_CAP_TX_LDPC 0x2000
#define WMI_HT_CAP_DEFAULT_ALL (WMI_HT_CAP_ENABLED | \
WMI_HT_CAP_HT20_SGI | \
WMI_HT_CAP_HT40_SGI | \
WMI_HT_CAP_TX_STBC | \
WMI_HT_CAP_RX_STBC | \
WMI_HT_CAP_LDPC)
#define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003
#define WMI_VHT_CAP_RX_LDPC 0x00000010
#define WMI_VHT_CAP_SGI_80MHZ 0x00000020
#define WMI_VHT_CAP_SGI_160MHZ 0x00000040
#define WMI_VHT_CAP_TX_STBC 0x00000080
#define WMI_VHT_CAP_RX_STBC_MASK 0x00000300
#define WMI_VHT_CAP_RX_STBC_MASK_SHIFT 8
#define WMI_VHT_CAP_SU_BFER 0x00000800
#define WMI_VHT_CAP_SU_BFEE 0x00001000
#define WMI_VHT_CAP_MAX_CS_ANT_MASK 0x0000E000
#define WMI_VHT_CAP_MAX_CS_ANT_MASK_SHIFT 13
#define WMI_VHT_CAP_MAX_SND_DIM_MASK 0x00070000
#define WMI_VHT_CAP_MAX_SND_DIM_MASK_SHIFT 16
#define WMI_VHT_CAP_MU_BFER 0x00080000
#define WMI_VHT_CAP_MU_BFEE 0x00100000
#define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000
#define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIFT 23
#define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000
#define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000
#define WMI_VHT_CAP_MAX_MPDU_LEN_3839 0x00000000
#define WMI_VHT_CAP_MAX_MPDU_LEN_7935 0x00000001
#define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002
#define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454 | \
WMI_VHT_CAP_RX_LDPC | \
WMI_VHT_CAP_SGI_80MHZ | \
WMI_VHT_CAP_TX_STBC | \
WMI_VHT_CAP_RX_STBC_MASK | \
WMI_VHT_CAP_MAX_AMPDU_LEN_EXP | \
WMI_VHT_CAP_RX_FIXED_ANT | \
WMI_VHT_CAP_TX_FIXED_ANT)
#define WMI_VHT_MAX_MCS_4_SS_MASK(r, ss) ((3 & (r)) << (((ss) - 1) << 1))
#define WMI_VHT_MAX_SUPP_RATE_MASK 0x1fff0000
#define WMI_VHT_MAX_SUPP_RATE_MASK_SHIFT 16
enum {
REGDMN_MODE_11A = 0x00001,
REGDMN_MODE_TURBO = 0x00002,
REGDMN_MODE_11B = 0x00004,
REGDMN_MODE_PUREG = 0x00008,
REGDMN_MODE_11G = 0x00008,
REGDMN_MODE_108G = 0x00020,
REGDMN_MODE_108A = 0x00040,
REGDMN_MODE_XR = 0x00100,
REGDMN_MODE_11A_HALF_RATE = 0x00200,
REGDMN_MODE_11A_QUARTER_RATE = 0x00400,
REGDMN_MODE_11NG_HT20 = 0x00800,
REGDMN_MODE_11NA_HT20 = 0x01000,
REGDMN_MODE_11NG_HT40PLUS = 0x02000,
REGDMN_MODE_11NG_HT40MINUS = 0x04000,
REGDMN_MODE_11NA_HT40PLUS = 0x08000,
REGDMN_MODE_11NA_HT40MINUS = 0x10000,
REGDMN_MODE_11AC_VHT20 = 0x20000,
REGDMN_MODE_11AC_VHT40PLUS = 0x40000,
REGDMN_MODE_11AC_VHT40MINUS = 0x80000,
REGDMN_MODE_11AC_VHT80 = 0x100000,
REGDMN_MODE_11AC_VHT160 = 0x200000,
REGDMN_MODE_11AC_VHT80_80 = 0x400000,
REGDMN_MODE_ALL = 0xffffffff
};
#define REGDMN_CAP1_CHAN_HALF_RATE 0x00000001
#define REGDMN_CAP1_CHAN_QUARTER_RATE 0x00000002
#define REGDMN_CAP1_CHAN_HAL49GHZ 0x00000004
#define REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
#define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
#define REGDMN_EEPROM_EEREGCAP_EN_KK_U2 0x0100
#define REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
#define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
#define REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
struct hal_reg_capabilities {
__le32 eeprom_rd;
__le32 eeprom_rd_ext;
__le32 regcap1;
__le32 regcap2;
__le32 wireless_modes;
__le32 low_2ghz_chan;
__le32 high_2ghz_chan;
__le32 low_5ghz_chan;
__le32 high_5ghz_chan;
} __packed;
enum wlan_mode_capability {
WHAL_WLAN_11A_CAPABILITY = 0x1,
WHAL_WLAN_11G_CAPABILITY = 0x2,
WHAL_WLAN_11AG_CAPABILITY = 0x3,
};
struct wlan_host_mem_req {
__le32 req_id;
__le32 unit_size;
__le32 num_unit_info;
__le32 num_units;
} __packed;
struct wmi_service_ready_event {
__le32 sw_version;
__le32 sw_version_1;
__le32 abi_version;
__le32 phy_capability;
__le32 max_frag_entry;
__le32 wmi_service_bitmap[16];
__le32 num_rf_chains;
__le32 ht_cap_info;
__le32 vht_cap_info;
__le32 vht_supp_mcs;
__le32 hw_min_tx_power;
__le32 hw_max_tx_power;
struct hal_reg_capabilities hal_reg_capabilities;
__le32 sys_cap_info;
__le32 min_pkt_size_enable;
__le32 max_bcn_ie_size;
__le32 num_mem_reqs;
struct wlan_host_mem_req mem_reqs[];
} __packed;
struct wmi_10x_service_ready_event {
__le32 sw_version;
__le32 abi_version;
__le32 phy_capability;
__le32 max_frag_entry;
__le32 wmi_service_bitmap[16];
__le32 num_rf_chains;
__le32 ht_cap_info;
__le32 vht_cap_info;
__le32 vht_supp_mcs;
__le32 hw_min_tx_power;
__le32 hw_max_tx_power;
struct hal_reg_capabilities hal_reg_capabilities;
__le32 sys_cap_info;
__le32 min_pkt_size_enable;
__le32 num_mem_reqs;
struct wlan_host_mem_req mem_reqs[];
} __packed;
#define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ)
#define WMI_UNIFIED_READY_TIMEOUT_HZ (5 * HZ)
struct wmi_ready_event {
__le32 sw_version;
__le32 abi_version;
struct wmi_mac_addr mac_addr;
__le32 status;
} __packed;
struct wmi_resource_config {
__le32 num_vdevs;
__le32 num_peers;
__le32 num_offload_peers;
__le32 num_offload_reorder_bufs;
__le32 num_peer_keys;
__le32 num_tids;
__le32 ast_skid_limit;
__le32 tx_chain_mask;
__le32 rx_chain_mask;
__le32 rx_timeout_pri_vi;
__le32 rx_timeout_pri_vo;
__le32 rx_timeout_pri_be;
__le32 rx_timeout_pri_bk;
__le32 rx_decap_mode;
__le32 scan_max_pending_reqs;
__le32 bmiss_offload_max_vdev;
__le32 roam_offload_max_vdev;
__le32 roam_offload_max_ap_profiles;
__le32 num_mcast_groups;
__le32 num_mcast_table_elems;
__le32 mcast2ucast_mode;
__le32 tx_dbg_log_size;
__le32 num_wds_entries;
__le32 dma_burst_size;
__le32 mac_aggr_delim;
__le32 rx_skip_defrag_timeout_dup_detection_check;
__le32 vow_config;
__le32 gtk_offload_max_vdev;
__le32 num_msdu_desc;
__le32 max_frag_entries;
} __packed;
struct wmi_resource_config_10x {
__le32 num_vdevs;
__le32 num_peers;
__le32 num_peer_keys;
__le32 num_tids;
__le32 ast_skid_limit;
__le32 tx_chain_mask;
__le32 rx_chain_mask;
__le32 rx_timeout_pri_vi;
__le32 rx_timeout_pri_vo;
__le32 rx_timeout_pri_be;
__le32 rx_timeout_pri_bk;
__le32 rx_decap_mode;
__le32 scan_max_pending_reqs;
__le32 bmiss_offload_max_vdev;
__le32 roam_offload_max_vdev;
__le32 roam_offload_max_ap_profiles;
__le32 num_mcast_groups;
__le32 num_mcast_table_elems;
__le32 mcast2ucast_mode;
__le32 tx_dbg_log_size;
__le32 num_wds_entries;
__le32 dma_burst_size;
__le32 mac_aggr_delim;
__le32 rx_skip_defrag_timeout_dup_detection_check;
__le32 vow_config;
__le32 num_msdu_desc;
__le32 max_frag_entries;
} __packed;
enum wmi_10_2_feature_mask {
WMI_10_2_RX_BATCH_MODE = BIT(0),
WMI_10_2_ATF_CONFIG = BIT(1),
WMI_10_2_COEX_GPIO = BIT(3),
WMI_10_2_BSS_CHAN_INFO = BIT(6),
WMI_10_2_PEER_STATS = BIT(7),
};
struct wmi_resource_config_10_2 {
struct wmi_resource_config_10x common;
__le32 max_peer_ext_stats;
__le32 smart_ant_cap;
__le32 bk_min_free;
__le32 be_min_free;
__le32 vi_min_free;
__le32 vo_min_free;
__le32 feature_mask;
} __packed;
#define NUM_UNITS_IS_NUM_VDEVS BIT(0)
#define NUM_UNITS_IS_NUM_PEERS BIT(1)
#define NUM_UNITS_IS_NUM_ACTIVE_PEERS BIT(2)
struct wmi_resource_config_10_4 {
__le32 num_vdevs;
__le32 num_peers;
__le32 num_active_peers;
__le32 num_offload_peers;
__le32 num_offload_reorder_buffs;
__le32 num_peer_keys;
__le32 num_tids;
__le32 ast_skid_limit;
__le32 tx_chain_mask;
__le32 rx_chain_mask;
__le32 rx_timeout_pri[4];
__le32 rx_decap_mode;
__le32 scan_max_pending_req;
__le32 bmiss_offload_max_vdev;
__le32 roam_offload_max_vdev;
__le32 roam_offload_max_ap_profiles;
__le32 num_mcast_groups;
__le32 num_mcast_table_elems;
__le32 mcast2ucast_mode;
__le32 tx_dbg_log_size;
__le32 num_wds_entries;
__le32 dma_burst_size;
__le32 mac_aggr_delim;
__le32 rx_skip_defrag_timeout_dup_detection_check;
__le32 vow_config;
__le32 gtk_offload_max_vdev;
__le32 num_msdu_desc;
__le32 max_frag_entries;
__le32 max_peer_ext_stats;
__le32 smart_ant_cap;
__le32 bk_minfree;
__le32 be_minfree;
__le32 vi_minfree;
__le32 vo_minfree;
__le32 rx_batchmode;
__le32 tt_support;
__le32 atf_config;
__le32 iphdr_pad_config;
__le32 qwrap_config;
} __packed;
enum wmi_coex_version {
WMI_NO_COEX_VERSION_SUPPORT = 0,
WMI_COEX_VERSION_1 = 1,
WMI_COEX_VERSION_2 = 2,
WMI_COEX_VERSION_3 = 3,
WMI_COEX_VERSION_4 = 4,
};
enum wmi_10_4_feature_mask {
WMI_10_4_LTEU_SUPPORT = BIT(0),
WMI_10_4_COEX_GPIO_SUPPORT = BIT(1),
WMI_10_4_AUX_RADIO_SPECTRAL_INTF = BIT(2),
WMI_10_4_AUX_RADIO_CHAN_LOAD_INTF = BIT(3),
WMI_10_4_BSS_CHANNEL_INFO_64 = BIT(4),
WMI_10_4_PEER_STATS = BIT(5),
WMI_10_4_VDEV_STATS = BIT(6),
WMI_10_4_TDLS = BIT(7),
WMI_10_4_TDLS_OFFCHAN = BIT(8),
WMI_10_4_TDLS_UAPSD_BUFFER_STA = BIT(9),
WMI_10_4_TDLS_UAPSD_SLEEP_STA = BIT(10),
WMI_10_4_TDLS_CONN_TRACKER_IN_HOST_MODE = BIT(11),
WMI_10_4_TDLS_EXPLICIT_MODE_ONLY = BIT(12),
WMI_10_4_TX_DATA_ACK_RSSI = BIT(16),
WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT = BIT(17),
WMI_10_4_REPORT_AIRTIME = BIT(18),
};
enum {
WMI_GPIO_PULL_NONE,
WMI_GPIO_PULL_UP,
WMI_GPIO_PULL_DOWN,
};
enum {
WMI_GPIO_INTTYPE_DISABLE,
WMI_GPIO_INTTYPE_RISING_EDGE,
WMI_GPIO_INTTYPE_FALLING_EDGE,
WMI_GPIO_INTTYPE_BOTH_EDGE,
WMI_GPIO_INTTYPE_LEVEL_LOW,
WMI_GPIO_INTTYPE_LEVEL_HIGH
};
struct wmi_gpio_config_cmd {
__le32 gpio_num;
__le32 input;
__le32 pull_type;
__le32 intr_mode;
} __packed;
struct wmi_gpio_output_cmd {
__le32 gpio_num;
__le32 set;
} __packed;
struct wmi_gpio_input_event {
__le32 gpio_num;
} __packed;
struct wmi_ext_resource_config_10_4_cmd {
__le32 host_platform_config;
__le32 fw_feature_bitmap;
__le32 wlan_gpio_priority;
__le32 coex_version;
__le32 coex_gpio_pin1;
__le32 coex_gpio_pin2;
__le32 coex_gpio_pin3;
__le32 num_tdls_vdevs;
__le32 num_tdls_conn_table_entries;
__le32 max_tdls_concurrent_sleep_sta;
__le32 max_tdls_concurrent_buffer_sta;
};
struct host_memory_chunk {
__le32 req_id;
__le32 ptr;
__le32 size;
} __packed;
#define WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID 8
struct wmi_host_mem_chunks {
__le32 count;
union {
struct host_memory_chunk item;
DECLARE_FLEX_ARRAY(struct host_memory_chunk, items);
};
} __packed;
struct wmi_init_cmd {
struct wmi_resource_config resource_config;
struct wmi_host_mem_chunks mem_chunks;
} __packed;
struct wmi_init_cmd_10x {
struct wmi_resource_config_10x resource_config;
struct wmi_host_mem_chunks mem_chunks;
} __packed;
struct wmi_init_cmd_10_2 {
struct wmi_resource_config_10_2 resource_config;
struct wmi_host_mem_chunks mem_chunks;
} __packed;
struct wmi_init_cmd_10_4 {
struct wmi_resource_config_10_4 resource_config;
struct wmi_host_mem_chunks mem_chunks;
} __packed;
struct wmi_chan_list_entry {
__le16 freq;
u8 phy_mode;
u8 reserved;
} __packed;
struct wmi_chan_list {
__le32 tag;
__le32 num_chan;
struct wmi_chan_list_entry channel_list[];
} __packed;
struct wmi_bssid_list {
__le32 tag;
__le32 num_bssid;
struct wmi_mac_addr bssid_list[];
} __packed;
struct wmi_ie_data {
__le32 tag;
__le32 ie_len;
u8 ie_data[];
} __packed;
struct wmi_ssid {
__le32 ssid_len;
u8 ssid[32];
} __packed;
struct wmi_ssid_list {
__le32 tag;
__le32 num_ssids;
struct wmi_ssid ssids[];
} __packed;
#define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000
#define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000
#define WLAN_SCAN_PARAMS_MAX_SSID 16
#define WLAN_SCAN_PARAMS_MAX_BSSID 4
#define WLAN_SCAN_PARAMS_MAX_IE_LEN 256
#define WMI_SCAN_CHAN_MIN_TIME_MSEC 40
enum wmi_scan_priority {
WMI_SCAN_PRIORITY_VERY_LOW = 0,
WMI_SCAN_PRIORITY_LOW,
WMI_SCAN_PRIORITY_MEDIUM,
WMI_SCAN_PRIORITY_HIGH,
WMI_SCAN_PRIORITY_VERY_HIGH,
WMI_SCAN_PRIORITY_COUNT
};
struct wmi_start_scan_common {
__le32 scan_id;
__le32 scan_req_id;
__le32 vdev_id;
__le32 scan_priority;
__le32 notify_scan_events;
__le32 dwell_time_active;
__le32 dwell_time_passive;
__le32 min_rest_time;
__le32 max_rest_time;
__le32 repeat_probe_time;
__le32 probe_spacing_time;
__le32 idle_time;
__le32 max_scan_time;
__le32 probe_delay;
__le32 scan_ctrl_flags;
} __packed;
struct wmi_start_scan_cmd {
struct wmi_start_scan_common common;
__le32 burst_duration_ms;
u8 tlvs[];
} __packed;
struct wmi_10x_start_scan_cmd {
struct wmi_start_scan_common common;
u8 tlvs[];
} __packed;
struct wmi_ssid_arg {
int len;
const u8 *ssid;
};
struct wmi_bssid_arg {
const u8 *bssid;
};
struct wmi_start_scan_arg {
u32 scan_id;
u32 scan_req_id;
u32 vdev_id;
u32 scan_priority;
u32 notify_scan_events;
u32 dwell_time_active;
u32 dwell_time_passive;
u32 min_rest_time;
u32 max_rest_time;
u32 repeat_probe_time;
u32 probe_spacing_time;
u32 idle_time;
u32 max_scan_time;
u32 probe_delay;
u32 scan_ctrl_flags;
u32 burst_duration_ms;
u32 ie_len;
u32 n_channels;
u32 n_ssids;
u32 n_bssids;
u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
u16 channels[64];
struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
struct wmi_mac_addr mac_addr;
struct wmi_mac_addr mac_mask;
};
#define WMI_SCAN_FLAG_PASSIVE 0x1
#define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2
#define WMI_SCAN_ADD_CCK_RATES 0x4
#define WMI_SCAN_ADD_OFDM_RATES 0x8
#define WMI_SCAN_CHAN_STAT_EVENT 0x10
#define WMI_SCAN_FILTER_PROBE_REQ 0x20
#define WMI_SCAN_BYPASS_DFS_CHN 0x40
#define WMI_SCAN_CONTINUE_ON_ERROR 0x80
#define WMI_SCAN_ADD_SPOOFED_MAC_IN_PROBE_REQ 0x1000
#define WMI_SCAN_CLASS_MASK 0xFF000000
enum wmi_stop_scan_type {
WMI_SCAN_STOP_ONE = 0x00000000,
WMI_SCAN_STOP_VDEV_ALL = 0x01000000,
WMI_SCAN_STOP_ALL = 0x04000000,
};
struct wmi_stop_scan_cmd {
__le32 scan_req_id;
__le32 scan_id;
__le32 req_type;
__le32 vdev_id;
} __packed;
struct wmi_stop_scan_arg {
u32 req_id;
enum wmi_stop_scan_type req_type;
union {
u32 scan_id;
u32 vdev_id;
} u;
};
struct wmi_scan_chan_list_cmd {
__le32 num_scan_chans;
struct wmi_channel chan_info[];
} __packed;
struct wmi_scan_chan_list_arg {
u32 n_channels;
struct wmi_channel_arg *channels;
};
enum wmi_bss_filter {
WMI_BSS_FILTER_NONE = 0,
WMI_BSS_FILTER_ALL,
WMI_BSS_FILTER_PROFILE,
WMI_BSS_FILTER_ALL_BUT_PROFILE,
WMI_BSS_FILTER_CURRENT_BSS,
WMI_BSS_FILTER_ALL_BUT_BSS,
WMI_BSS_FILTER_PROBED_SSID,
WMI_BSS_FILTER_LAST_BSS,
};
enum wmi_scan_event_type {
WMI_SCAN_EVENT_STARTED = BIT(0),
WMI_SCAN_EVENT_COMPLETED = BIT(1),
WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2),
WMI_SCAN_EVENT_FOREIGN_CHANNEL = BIT(3),
WMI_SCAN_EVENT_DEQUEUED = BIT(4),
WMI_SCAN_EVENT_PREEMPTED = BIT(5),
WMI_SCAN_EVENT_START_FAILED = BIT(6),
WMI_SCAN_EVENT_RESTARTED = BIT(7),
WMI_SCAN_EVENT_FOREIGN_CHANNEL_EXIT = BIT(8),
WMI_SCAN_EVENT_MAX = BIT(15),
};
enum wmi_scan_completion_reason {
WMI_SCAN_REASON_COMPLETED,
WMI_SCAN_REASON_CANCELLED,
WMI_SCAN_REASON_PREEMPTED,
WMI_SCAN_REASON_TIMEDOUT,
WMI_SCAN_REASON_INTERNAL_FAILURE,
WMI_SCAN_REASON_MAX,
};
struct wmi_scan_event {
__le32 event_type;
__le32 reason;
__le32 channel_freq;
__le32 scan_req_id;
__le32 scan_id;
__le32 vdev_id;
} __packed;
#define WMI_MGMT_RX_HDR_HEADROOM 52
struct wmi_mgmt_rx_hdr_v1 {
__le32 channel;
__le32 snr;
__le32 rate;
__le32 phy_mode;
__le32 buf_len;
__le32 status;
} __packed;
struct wmi_mgmt_rx_hdr_v2 {
struct wmi_mgmt_rx_hdr_v1 v1;
__le32 rssi_ctl[4];
} __packed;
struct wmi_mgmt_rx_event_v1 {
struct wmi_mgmt_rx_hdr_v1 hdr;
u8 buf[];
} __packed;
struct wmi_mgmt_rx_event_v2 {
struct wmi_mgmt_rx_hdr_v2 hdr;
u8 buf[];
} __packed;
struct wmi_10_4_mgmt_rx_hdr {
__le32 channel;
__le32 snr;
u8 rssi_ctl[4];
__le32 rate;
__le32 phy_mode;
__le32 buf_len;
__le32 status;
} __packed;
struct wmi_10_4_mgmt_rx_event {
struct wmi_10_4_mgmt_rx_hdr hdr;
u8 buf[];
} __packed;
struct wmi_mgmt_rx_ext_info {
__le64 rx_mac_timestamp;
} __packed __aligned(4);
#define WMI_RX_STATUS_OK 0x00
#define WMI_RX_STATUS_ERR_CRC 0x01
#define WMI_RX_STATUS_ERR_DECRYPT 0x08
#define WMI_RX_STATUS_ERR_MIC 0x10
#define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20
#define WMI_RX_STATUS_EXT_INFO 0x40
#define PHY_ERROR_GEN_SPECTRAL_SCAN 0x26
#define PHY_ERROR_GEN_FALSE_RADAR_EXT 0x24
#define PHY_ERROR_GEN_RADAR 0x05
#define PHY_ERROR_10_4_RADAR_MASK 0x4
#define PHY_ERROR_10_4_SPECTRAL_SCAN_MASK 0x4000000
enum phy_err_type {
PHY_ERROR_UNKNOWN,
PHY_ERROR_SPECTRAL_SCAN,
PHY_ERROR_FALSE_RADAR_EXT,
PHY_ERROR_RADAR
};
struct wmi_phyerr {
__le32 tsf_timestamp;
__le16 freq1;
__le16 freq2;
u8 rssi_combined;
u8 chan_width_mhz;
u8 phy_err_code;
u8 rsvd0;
__le32 rssi_chains[4];
__le16 nf_chains[4];
__le32 buf_len;
u8 buf[];
} __packed;
struct wmi_phyerr_event {
__le32 num_phyerrs;
__le32 tsf_l32;
__le32 tsf_u32;
u8 phyerrs[];
} __packed;
struct wmi_10_4_phyerr_event {
__le32 tsf_l32;
__le32 tsf_u32;
__le16 freq1;
__le16 freq2;
u8 rssi_combined;
u8 chan_width_mhz;
u8 phy_err_code;
u8 rsvd0;
__le32 rssi_chains[4];
__le16 nf_chains[4];
__le32 phy_err_mask[2];
__le32 tsf_timestamp;
__le32 buf_len;
u8 buf[];
} __packed;
struct wmi_radar_found_info {
__le32 pri_min;
__le32 pri_max;
__le32 width_min;
__le32 width_max;
__le32 sidx_min;
__le32 sidx_max;
} __packed;
enum wmi_radar_confirmation_status {
WMI_SW_RADAR_DETECTED = 0,
WMI_RADAR_DETECTION_FAIL = 1,
WMI_HW_RADAR_DETECTED = 2,
};
#define PHYERR_TLV_SIG 0xBB
#define PHYERR_TLV_TAG_SEARCH_FFT_REPORT 0xFB
#define PHYERR_TLV_TAG_RADAR_PULSE_SUMMARY 0xF8
#define PHYERR_TLV_TAG_SPECTRAL_SUMMARY_REPORT 0xF9
struct phyerr_radar_report {
__le32 reg0;
__le32 reg1;
} __packed;
#define RADAR_REPORT_REG0_PULSE_IS_CHIRP_MASK 0x80000000
#define RADAR_REPORT_REG0_PULSE_IS_CHIRP_LSB 31
#define RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH_MASK 0x40000000
#define RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH_LSB 30
#define RADAR_REPORT_REG0_AGC_TOTAL_GAIN_MASK 0x3FF00000
#define RADAR_REPORT_REG0_AGC_TOTAL_GAIN_LSB 20
#define RADAR_REPORT_REG0_PULSE_DELTA_DIFF_MASK 0x000F0000
#define RADAR_REPORT_REG0_PULSE_DELTA_DIFF_LSB 16
#define RADAR_REPORT_REG0_PULSE_DELTA_PEAK_MASK 0x0000FC00
#define RADAR_REPORT_REG0_PULSE_DELTA_PEAK_LSB 10
#define RADAR_REPORT_REG0_PULSE_SIDX_MASK 0x000003FF
#define RADAR_REPORT_REG0_PULSE_SIDX_LSB 0
#define RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID_MASK 0x80000000
#define RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID_LSB 31
#define RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN_MASK 0x7F000000
#define RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN_LSB 24
#define RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK_MASK 0x00FF0000
#define RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK_LSB 16
#define RADAR_REPORT_REG1_PULSE_TSF_OFFSET_MASK 0x0000FF00
#define RADAR_REPORT_REG1_PULSE_TSF_OFFSET_LSB 8
#define RADAR_REPORT_REG1_PULSE_DUR_MASK 0x000000FF
#define RADAR_REPORT_REG1_PULSE_DUR_LSB 0
struct phyerr_fft_report {
__le32 reg0;
__le32 reg1;
} __packed;
#define SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB_MASK 0xFF800000
#define SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB_LSB 23
#define SEARCH_FFT_REPORT_REG0_BASE_PWR_DB_MASK 0x007FC000
#define SEARCH_FFT_REPORT_REG0_BASE_PWR_DB_LSB 14
#define SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX_MASK 0x00003000
#define SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX_LSB 12
#define SEARCH_FFT_REPORT_REG0_PEAK_SIDX_MASK 0x00000FFF
#define SEARCH_FFT_REPORT_REG0_PEAK_SIDX_LSB 0
#define SEARCH_FFT_REPORT_REG1_RELPWR_DB_MASK 0xFC000000
#define SEARCH_FFT_REPORT_REG1_RELPWR_DB_LSB 26
#define SEARCH_FFT_REPORT_REG1_AVGPWR_DB_MASK 0x03FC0000
#define SEARCH_FFT_REPORT_REG1_AVGPWR_DB_LSB 18
#define SEARCH_FFT_REPORT_REG1_PEAK_MAG_MASK 0x0003FF00
#define SEARCH_FFT_REPORT_REG1_PEAK_MAG_LSB 8
#define SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB_MASK 0x000000FF
#define SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB_LSB 0
struct phyerr_tlv {
__le16 len;
u8 tag;
u8 sig;
} __packed;
#define DFS_RSSI_POSSIBLY_FALSE 50
#define DFS_PEAK_MAG_THOLD_POSSIBLY_FALSE 40
struct wmi_mgmt_tx_hdr {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 tx_rate;
__le32 tx_power;
__le32 buf_len;
} __packed;
struct wmi_mgmt_tx_cmd {
struct wmi_mgmt_tx_hdr hdr;
u8 buf[];
} __packed;
struct wmi_echo_event {
__le32 value;
} __packed;
struct wmi_echo_cmd {
__le32 value;
} __packed;
struct wmi_pdev_set_regdomain_cmd {
__le32 reg_domain;
__le32 reg_domain_2G;
__le32 reg_domain_5G;
__le32 conformance_test_limit_2G;
__le32 conformance_test_limit_5G;
} __packed;
enum wmi_dfs_region {
WMI_UNINIT_DFS_DOMAIN = 0,
WMI_FCC_DFS_DOMAIN = 1,
WMI_ETSI_DFS_DOMAIN = 2,
WMI_MKK4_DFS_DOMAIN = 3,
};
struct wmi_pdev_set_regdomain_cmd_10x {
__le32 reg_domain;
__le32 reg_domain_2G;
__le32 reg_domain_5G;
__le32 conformance_test_limit_2G;
__le32 conformance_test_limit_5G;
__le32 dfs_domain;
} __packed;
struct wmi_pdev_set_quiet_cmd {
__le32 period;
__le32 duration;
__le32 next_start;
__le32 enabled;
} __packed;
enum ath10k_protmode {
ATH10K_PROT_NONE = 0,
ATH10K_PROT_CTSONLY = 1,
ATH10K_PROT_RTSCTS = 2,
};
enum wmi_rtscts_profile {
WMI_RTSCTS_FOR_NO_RATESERIES = 0,
WMI_RTSCTS_FOR_SECOND_RATESERIES,
WMI_RTSCTS_ACROSS_SW_RETRIES
};
#define WMI_RTSCTS_ENABLED 1
#define WMI_RTSCTS_SET_MASK 0x0f
#define WMI_RTSCTS_SET_LSB 0
#define WMI_RTSCTS_PROFILE_MASK 0xf0
#define WMI_RTSCTS_PROFILE_LSB 4
enum wmi_beacon_gen_mode {
WMI_BEACON_STAGGERED_MODE = 0,
WMI_BEACON_BURST_MODE = 1
};
enum wmi_csa_event_ies_present_flag {
WMI_CSA_IE_PRESENT = 0x00000001,
WMI_XCSA_IE_PRESENT = 0x00000002,
WMI_WBW_IE_PRESENT = 0x00000004,
WMI_CSWARP_IE_PRESENT = 0x00000008,
};
struct wmi_csa_event {
__le32 i_fc_dur;
struct wmi_mac_addr i_addr1;
struct wmi_mac_addr i_addr2;
__le32 csa_ie[2];
__le32 xcsa_ie[2];
__le32 wb_ie[2];
__le32 cswarp_ie;
__le32 ies_present_flag;
} __packed;
#define PDEV_DEFAULT_STATS_UPDATE_PERIOD 500
#define VDEV_DEFAULT_STATS_UPDATE_PERIOD 500
#define PEER_DEFAULT_STATS_UPDATE_PERIOD 500
struct wmi_pdev_param_map {
u32 tx_chain_mask;
u32 rx_chain_mask;
u32 txpower_limit2g;
u32 txpower_limit5g;
u32 txpower_scale;
u32 beacon_gen_mode;
u32 beacon_tx_mode;
u32 resmgr_offchan_mode;
u32 protection_mode;
u32 dynamic_bw;
u32 non_agg_sw_retry_th;
u32 agg_sw_retry_th;
u32 sta_kickout_th;
u32 ac_aggrsize_scaling;
u32 ltr_enable;
u32 ltr_ac_latency_be;
u32 ltr_ac_latency_bk;
u32 ltr_ac_latency_vi;
u32 ltr_ac_latency_vo;
u32 ltr_ac_latency_timeout;
u32 ltr_sleep_override;
u32 ltr_rx_override;
u32 ltr_tx_activity_timeout;
u32 l1ss_enable;
u32 dsleep_enable;
u32 pcielp_txbuf_flush;
u32 pcielp_txbuf_watermark;
u32 pcielp_txbuf_tmo_en;
u32 pcielp_txbuf_tmo_value;
u32 pdev_stats_update_period;
u32 vdev_stats_update_period;
u32 peer_stats_update_period;
u32 bcnflt_stats_update_period;
u32 pmf_qos;
u32 arp_ac_override;
u32 dcs;
u32 ani_enable;
u32 ani_poll_period;
u32 ani_listen_period;
u32 ani_ofdm_level;
u32 ani_cck_level;
u32 dyntxchain;
u32 proxy_sta;
u32 idle_ps_config;
u32 power_gating_sleep;
u32 fast_channel_reset;
u32 burst_dur;
u32 burst_enable;
u32 cal_period;
u32 aggr_burst;
u32 rx_decap_mode;
u32 smart_antenna_default_antenna;
u32 igmpmld_override;
u32 igmpmld_tid;
u32 antenna_gain;
u32 rx_filter;
u32 set_mcast_to_ucast_tid;
u32 proxy_sta_mode;
u32 set_mcast2ucast_mode;
u32 set_mcast2ucast_buffer;
u32 remove_mcast2ucast_buffer;
u32 peer_sta_ps_statechg_enable;
u32 igmpmld_ac_override;
u32 block_interbss;
u32 set_disable_reset_cmdid;
u32 set_msdu_ttl_cmdid;
u32 set_ppdu_duration_cmdid;
u32 txbf_sound_period_cmdid;
u32 set_promisc_mode_cmdid;
u32 set_burst_mode_cmdid;
u32 en_stats;
u32 mu_group_policy;
u32 noise_detection;
u32 noise_threshold;
u32 dpd_enable;
u32 set_mcast_bcast_echo;
u32 atf_strict_sch;
u32 atf_sched_duration;
u32 ant_plzn;
u32 mgmt_retry_limit;
u32 sensitivity_level;
u32 signed_txpower_2g;
u32 signed_txpower_5g;
u32 enable_per_tid_amsdu;
u32 enable_per_tid_ampdu;
u32 cca_threshold;
u32 rts_fixed_rate;
u32 pdev_reset;
u32 wapi_mbssid_offset;
u32 arp_srcaddr;
u32 arp_dstaddr;
u32 enable_btcoex;
u32 rfkill_config;
u32 rfkill_enable;
u32 peer_stats_info_enable;
};
#define WMI_PDEV_PARAM_UNSUPPORTED 0
enum wmi_pdev_param {
WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
WMI_PDEV_PARAM_RX_CHAIN_MASK,
WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
WMI_PDEV_PARAM_TXPOWER_SCALE,
WMI_PDEV_PARAM_BEACON_GEN_MODE,
WMI_PDEV_PARAM_BEACON_TX_MODE,
WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
WMI_PDEV_PARAM_PROTECTION_MODE,
WMI_PDEV_PARAM_DYNAMIC_BW,
WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
WMI_PDEV_PARAM_STA_KICKOUT_TH,
WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
WMI_PDEV_PARAM_LTR_ENABLE,
WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
WMI_PDEV_PARAM_L1SS_ENABLE,
WMI_PDEV_PARAM_DSLEEP_ENABLE,
WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
WMI_PDEV_PARAM_PMF_QOS,
WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
WMI_PDEV_PARAM_DCS,
WMI_PDEV_PARAM_ANI_ENABLE,
WMI_PDEV_PARAM_ANI_POLL_PERIOD,
WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
WMI_PDEV_PARAM_ANI_CCK_LEVEL,
WMI_PDEV_PARAM_DYNTXCHAIN,
WMI_PDEV_PARAM_PROXY_STA,
WMI_PDEV_PARAM_IDLE_PS_CONFIG,
WMI_PDEV_PARAM_POWER_GATING_SLEEP,
};
enum wmi_10x_pdev_param {
WMI_10X_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
WMI_10X_PDEV_PARAM_RX_CHAIN_MASK,
WMI_10X_PDEV_PARAM_TXPOWER_LIMIT2G,
WMI_10X_PDEV_PARAM_TXPOWER_LIMIT5G,
WMI_10X_PDEV_PARAM_TXPOWER_SCALE,
WMI_10X_PDEV_PARAM_BEACON_GEN_MODE,
WMI_10X_PDEV_PARAM_BEACON_TX_MODE,
WMI_10X_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
WMI_10X_PDEV_PARAM_PROTECTION_MODE,
WMI_10X_PDEV_PARAM_DYNAMIC_BW,
WMI_10X_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
WMI_10X_PDEV_PARAM_AGG_SW_RETRY_TH,
WMI_10X_PDEV_PARAM_STA_KICKOUT_TH,
WMI_10X_PDEV_PARAM_AC_AGGRSIZE_SCALING,
WMI_10X_PDEV_PARAM_LTR_ENABLE,
WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_BE,
WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_BK,
WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_VI,
WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_VO,
WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
WMI_10X_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
WMI_10X_PDEV_PARAM_LTR_RX_OVERRIDE,
WMI_10X_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
WMI_10X_PDEV_PARAM_L1SS_ENABLE,
WMI_10X_PDEV_PARAM_DSLEEP_ENABLE,
WMI_10X_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
WMI_10X_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
WMI_10X_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
WMI_10X_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
WMI_10X_PDEV_PARAM_PMF_QOS,
WMI_10X_PDEV_PARAM_ARPDHCP_AC_OVERRIDE,
WMI_10X_PDEV_PARAM_DCS,
WMI_10X_PDEV_PARAM_ANI_ENABLE,
WMI_10X_PDEV_PARAM_ANI_POLL_PERIOD,
WMI_10X_PDEV_PARAM_ANI_LISTEN_PERIOD,
WMI_10X_PDEV_PARAM_ANI_OFDM_LEVEL,
WMI_10X_PDEV_PARAM_ANI_CCK_LEVEL,
WMI_10X_PDEV_PARAM_DYNTXCHAIN,
WMI_10X_PDEV_PARAM_FAST_CHANNEL_RESET,
WMI_10X_PDEV_PARAM_BURST_DUR,
WMI_10X_PDEV_PARAM_BURST_ENABLE,
WMI_10X_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
WMI_10X_PDEV_PARAM_IGMPMLD_OVERRIDE,
WMI_10X_PDEV_PARAM_IGMPMLD_TID,
WMI_10X_PDEV_PARAM_ANTENNA_GAIN,
WMI_10X_PDEV_PARAM_RX_DECAP_MODE,
WMI_10X_PDEV_PARAM_RX_FILTER,
WMI_10X_PDEV_PARAM_SET_MCAST_TO_UCAST_TID,
WMI_10X_PDEV_PARAM_PROXY_STA_MODE,
WMI_10X_PDEV_PARAM_SET_MCAST2UCAST_MODE,
WMI_10X_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
WMI_10X_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
WMI_10X_PDEV_PARAM_PEER_STA_PS_STATECHG_ENABLE,
WMI_10X_PDEV_PARAM_RTS_FIXED_RATE,
WMI_10X_PDEV_PARAM_CAL_PERIOD,
WMI_10X_PDEV_PARAM_ATF_STRICT_SCH,
WMI_10X_PDEV_PARAM_ATF_SCHED_DURATION,
WMI_10X_PDEV_PARAM_SET_PROMISC_MODE_CMDID,
WMI_10X_PDEV_PARAM_PDEV_RESET
};
enum wmi_10_4_pdev_param {
WMI_10_4_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
WMI_10_4_PDEV_PARAM_RX_CHAIN_MASK,
WMI_10_4_PDEV_PARAM_TXPOWER_LIMIT2G,
WMI_10_4_PDEV_PARAM_TXPOWER_LIMIT5G,
WMI_10_4_PDEV_PARAM_TXPOWER_SCALE,
WMI_10_4_PDEV_PARAM_BEACON_GEN_MODE,
WMI_10_4_PDEV_PARAM_BEACON_TX_MODE,
WMI_10_4_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
WMI_10_4_PDEV_PARAM_PROTECTION_MODE,
WMI_10_4_PDEV_PARAM_DYNAMIC_BW,
WMI_10_4_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
WMI_10_4_PDEV_PARAM_AGG_SW_RETRY_TH,
WMI_10_4_PDEV_PARAM_STA_KICKOUT_TH,
WMI_10_4_PDEV_PARAM_AC_AGGRSIZE_SCALING,
WMI_10_4_PDEV_PARAM_LTR_ENABLE,
WMI_10_4_PDEV_PARAM_LTR_AC_LATENCY_BE,
WMI_10_4_PDEV_PARAM_LTR_AC_LATENCY_BK,
WMI_10_4_PDEV_PARAM_LTR_AC_LATENCY_VI,
WMI_10_4_PDEV_PARAM_LTR_AC_LATENCY_VO,
WMI_10_4_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
WMI_10_4_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
WMI_10_4_PDEV_PARAM_LTR_RX_OVERRIDE,
WMI_10_4_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
WMI_10_4_PDEV_PARAM_L1SS_ENABLE,
WMI_10_4_PDEV_PARAM_DSLEEP_ENABLE,
WMI_10_4_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
WMI_10_4_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
WMI_10_4_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
WMI_10_4_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
WMI_10_4_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
WMI_10_4_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
WMI_10_4_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
WMI_10_4_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
WMI_10_4_PDEV_PARAM_PMF_QOS,
WMI_10_4_PDEV_PARAM_ARP_AC_OVERRIDE,
WMI_10_4_PDEV_PARAM_DCS,
WMI_10_4_PDEV_PARAM_ANI_ENABLE,
WMI_10_4_PDEV_PARAM_ANI_POLL_PERIOD,
WMI_10_4_PDEV_PARAM_ANI_LISTEN_PERIOD,
WMI_10_4_PDEV_PARAM_ANI_OFDM_LEVEL,
WMI_10_4_PDEV_PARAM_ANI_CCK_LEVEL,
WMI_10_4_PDEV_PARAM_DYNTXCHAIN,
WMI_10_4_PDEV_PARAM_PROXY_STA,
WMI_10_4_PDEV_PARAM_IDLE_PS_CONFIG,
WMI_10_4_PDEV_PARAM_POWER_GATING_SLEEP,
WMI_10_4_PDEV_PARAM_AGGR_BURST,
WMI_10_4_PDEV_PARAM_RX_DECAP_MODE,
WMI_10_4_PDEV_PARAM_FAST_CHANNEL_RESET,
WMI_10_4_PDEV_PARAM_BURST_DUR,
WMI_10_4_PDEV_PARAM_BURST_ENABLE,
WMI_10_4_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
WMI_10_4_PDEV_PARAM_IGMPMLD_OVERRIDE,
WMI_10_4_PDEV_PARAM_IGMPMLD_TID,
WMI_10_4_PDEV_PARAM_ANTENNA_GAIN,
WMI_10_4_PDEV_PARAM_RX_FILTER,
WMI_10_4_PDEV_SET_MCAST_TO_UCAST_TID,
WMI_10_4_PDEV_PARAM_PROXY_STA_MODE,
WMI_10_4_PDEV_PARAM_SET_MCAST2UCAST_MODE,
WMI_10_4_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
WMI_10_4_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
WMI_10_4_PDEV_PEER_STA_PS_STATECHG_ENABLE,
WMI_10_4_PDEV_PARAM_IGMPMLD_AC_OVERRIDE,
WMI_10_4_PDEV_PARAM_BLOCK_INTERBSS,
WMI_10_4_PDEV_PARAM_SET_DISABLE_RESET_CMDID,
WMI_10_4_PDEV_PARAM_SET_MSDU_TTL_CMDID,
WMI_10_4_PDEV_PARAM_SET_PPDU_DURATION_CMDID,
WMI_10_4_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID,
WMI_10_4_PDEV_PARAM_SET_PROMISC_MODE_CMDID,
WMI_10_4_PDEV_PARAM_SET_BURST_MODE_CMDID,
WMI_10_4_PDEV_PARAM_EN_STATS,
WMI_10_4_PDEV_PARAM_MU_GROUP_POLICY,
WMI_10_4_PDEV_PARAM_NOISE_DETECTION,
WMI_10_4_PDEV_PARAM_NOISE_THRESHOLD,
WMI_10_4_PDEV_PARAM_DPD_ENABLE,
WMI_10_4_PDEV_PARAM_SET_MCAST_BCAST_ECHO,
WMI_10_4_PDEV_PARAM_ATF_STRICT_SCH,
WMI_10_4_PDEV_PARAM_ATF_SCHED_DURATION,
WMI_10_4_PDEV_PARAM_ANT_PLZN,
WMI_10_4_PDEV_PARAM_MGMT_RETRY_LIMIT,
WMI_10_4_PDEV_PARAM_SENSITIVITY_LEVEL,
WMI_10_4_PDEV_PARAM_SIGNED_TXPOWER_2G,
WMI_10_4_PDEV_PARAM_SIGNED_TXPOWER_5G,
WMI_10_4_PDEV_PARAM_ENABLE_PER_TID_AMSDU,
WMI_10_4_PDEV_PARAM_ENABLE_PER_TID_AMPDU,
WMI_10_4_PDEV_PARAM_CCA_THRESHOLD,
WMI_10_4_PDEV_PARAM_RTS_FIXED_RATE,
WMI_10_4_PDEV_PARAM_CAL_PERIOD,
WMI_10_4_PDEV_PARAM_PDEV_RESET,
WMI_10_4_PDEV_PARAM_WAPI_MBSSID_OFFSET,
WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
WMI_10_4_PDEV_PARAM_TXPOWER_DECR_DB,
WMI_10_4_PDEV_PARAM_RX_BATCHMODE,
WMI_10_4_PDEV_PARAM_PACKET_AGGR_DELAY,
WMI_10_4_PDEV_PARAM_ATF_OBSS_NOISE_SCH,
WMI_10_4_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR,
WMI_10_4_PDEV_PARAM_CUST_TXPOWER_SCALE,
WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
};
struct wmi_pdev_set_param_cmd {
__le32 param_id;
__le32 param_value;
} __packed;
struct wmi_pdev_set_base_macaddr_cmd {
struct wmi_mac_addr mac_addr;
} __packed;
#define WMI_PDEV_PARAM_CAL_PERIOD_MAX 60000
struct wmi_pdev_get_tpc_config_cmd {
__le32 param;
} __packed;
#define WMI_TPC_CONFIG_PARAM 1
#define WMI_TPC_FINAL_RATE_MAX 240
#define WMI_TPC_TX_N_CHAIN 4
#define WMI_TPC_RATE_MAX (WMI_TPC_TX_N_CHAIN * 65)
#define WMI_TPC_PREAM_TABLE_MAX 10
#define WMI_TPC_FLAG 3
#define WMI_TPC_BUF_SIZE 10
#define WMI_TPC_BEAMFORMING 2
enum wmi_tpc_table_type {
WMI_TPC_TABLE_TYPE_CDD = 0,
WMI_TPC_TABLE_TYPE_STBC = 1,
WMI_TPC_TABLE_TYPE_TXBF = 2,
};
enum wmi_tpc_config_event_flag {
WMI_TPC_CONFIG_EVENT_FLAG_TABLE_CDD = 0x1,
WMI_TPC_CONFIG_EVENT_FLAG_TABLE_STBC = 0x2,
WMI_TPC_CONFIG_EVENT_FLAG_TABLE_TXBF = 0x4,
};
struct wmi_pdev_tpc_config_event {
__le32 reg_domain;
__le32 chan_freq;
__le32 phy_mode;
__le32 twice_antenna_reduction;
__le32 twice_max_rd_power;
a_sle32 twice_antenna_gain;
__le32 power_limit;
__le32 rate_max;
__le32 num_tx_chain;
__le32 ctl;
__le32 flags;
s8 max_reg_allow_pow[WMI_TPC_TX_N_CHAIN];
s8 max_reg_allow_pow_agcdd[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
s8 max_reg_allow_pow_agstbc[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
s8 max_reg_allow_pow_agtxbf[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
u8 rates_array[WMI_TPC_RATE_MAX];
} __packed;
enum wmi_tp_scale {
WMI_TP_SCALE_MAX = 0,
WMI_TP_SCALE_50 = 1,
WMI_TP_SCALE_25 = 2,
WMI_TP_SCALE_12 = 3,
WMI_TP_SCALE_MIN = 4,
WMI_TP_SCALE_SIZE = 5,
};
struct wmi_pdev_tpc_final_table_event {
__le32 reg_domain;
__le32 chan_freq;
__le32 phy_mode;
__le32 twice_antenna_reduction;
__le32 twice_max_rd_power;
a_sle32 twice_antenna_gain;
__le32 power_limit;
__le32 rate_max;
__le32 num_tx_chain;
__le32 ctl;
__le32 flags;
s8 max_reg_allow_pow[WMI_TPC_TX_N_CHAIN];
s8 max_reg_allow_pow_agcdd[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
s8 max_reg_allow_pow_agstbc[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
s8 max_reg_allow_pow_agtxbf[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
u8 rates_array[WMI_TPC_FINAL_RATE_MAX];
u8 ctl_power_table[WMI_TPC_BEAMFORMING][WMI_TPC_TX_N_CHAIN]
[WMI_TPC_TX_N_CHAIN];
} __packed;
struct wmi_pdev_get_tpc_table_cmd {
__le32 param;
} __packed;
enum wmi_tpc_pream_2ghz {
WMI_TPC_PREAM_2GHZ_CCK = 0,
WMI_TPC_PREAM_2GHZ_OFDM,
WMI_TPC_PREAM_2GHZ_HT20,
WMI_TPC_PREAM_2GHZ_HT40,
WMI_TPC_PREAM_2GHZ_VHT20,
WMI_TPC_PREAM_2GHZ_VHT40,
WMI_TPC_PREAM_2GHZ_VHT80,
};
enum wmi_tpc_pream_5ghz {
WMI_TPC_PREAM_5GHZ_OFDM = 1,
WMI_TPC_PREAM_5GHZ_HT20,
WMI_TPC_PREAM_5GHZ_HT40,
WMI_TPC_PREAM_5GHZ_VHT20,
WMI_TPC_PREAM_5GHZ_VHT40,
WMI_TPC_PREAM_5GHZ_VHT80,
WMI_TPC_PREAM_5GHZ_HTCUP,
};
#define WMI_PEER_PS_STATE_DISABLED 2
struct wmi_peer_sta_ps_state_chg_event {
struct wmi_mac_addr peer_macaddr;
__le32 peer_ps_state;
} __packed;
#define WMI_MAX_DEBUG_MESG (sizeof(u32) * 32)
struct wmi_debug_mesg_event {
char bufp[WMI_MAX_DEBUG_MESG];
} __packed;
enum {
VDEV_SUBTYPE_P2PDEV = 0,
VDEV_SUBTYPE_P2PCLI,
VDEV_SUBTYPE_P2PGO,
VDEV_SUBTYPE_BT,
};
struct wmi_pdev_set_channel_cmd {
struct wmi_channel chan;
} __packed;
struct wmi_pdev_pktlog_enable_cmd {
__le32 ev_bitmap;
} __packed;
#define WMI_DSCP_MAP_MAX (64)
struct wmi_pdev_set_dscp_tid_map_cmd {
__le32 dscp_to_tid_map[WMI_DSCP_MAP_MAX];
} __packed;
enum mcast_bcast_rate_id {
WMI_SET_MCAST_RATE,
WMI_SET_BCAST_RATE
};
struct mcast_bcast_rate {
enum mcast_bcast_rate_id rate_id;
__le32 rate;
} __packed;
struct wmi_wmm_params {
__le32 cwmin;
__le32 cwmax;
__le32 aifs;
__le32 txop;
__le32 acm;
__le32 no_ack;
} __packed;
struct wmi_pdev_set_wmm_params {
struct wmi_wmm_params ac_be;
struct wmi_wmm_params ac_bk;
struct wmi_wmm_params ac_vi;
struct wmi_wmm_params ac_vo;
} __packed;
struct wmi_wmm_params_arg {
u32 cwmin;
u32 cwmax;
u32 aifs;
u32 txop;
u32 acm;
u32 no_ack;
};
struct wmi_wmm_params_all_arg {
struct wmi_wmm_params_arg ac_be;
struct wmi_wmm_params_arg ac_bk;
struct wmi_wmm_params_arg ac_vi;
struct wmi_wmm_params_arg ac_vo;
};
struct wmi_pdev_stats_tx {
__le32 comp_queued;
__le32 comp_delivered;
__le32 msdu_enqued;
__le32 mpdu_enqued;
__le32 wmm_drop;
__le32 local_enqued;
__le32 local_freed;
__le32 hw_queued;
__le32 hw_reaped;
__le32 underrun;
__le32 tx_abort;
__le32 mpdus_requeued;
__le32 tx_ko;
__le32 data_rc;
__le32 self_triggers;
__le32 sw_retry_failure;
__le32 illgl_rate_phy_err;
__le32 pdev_cont_xretry;
__le32 pdev_tx_timeout;
__le32 pdev_resets;
__le32 stateless_tid_alloc_failure;
__le32 phy_underrun;
__le32 txop_ovf;
} __packed;
struct wmi_10_4_pdev_stats_tx {
__le32 comp_queued;
__le32 comp_delivered;
__le32 msdu_enqued;
__le32 mpdu_enqued;
__le32 wmm_drop;
__le32 local_enqued;
__le32 local_freed;
__le32 hw_queued;
__le32 hw_reaped;
__le32 underrun;
__le32 hw_paused;
__le32 tx_abort;
__le32 mpdus_requeued;
__le32 tx_ko;
__le32 data_rc;
__le32 self_triggers;
__le32 sw_retry_failure;
__le32 illgl_rate_phy_err;
__le32 pdev_cont_xretry;
__le32 pdev_tx_timeout;
__le32 pdev_resets;
__le32 stateless_tid_alloc_failure;
__le32 phy_underrun;
__le32 txop_ovf;
__le32 seq_posted;
__le32 seq_failed_queueing;
__le32 seq_completed;
__le32 seq_restarted;
__le32 mu_seq_posted;
__le32 mpdus_sw_flush;
__le32 mpdus_hw_filter;
__le32 mpdus_truncated;
__le32 mpdus_ack_failed;
__le32 mpdus_expired;
} __packed;
struct wmi_pdev_stats_rx {
__le32 mid_ppdu_route_change;
__le32 status_rcvd;
__le32 r0_frags;
__le32 r1_frags;
__le32 r2_frags;
__le32 r3_frags;
__le32 htt_msdus;
__le32 htt_mpdus;
__le32 loc_msdus;
__le32 loc_mpdus;
__le32 oversize_amsdu;
__le32 phy_errs;
__le32 phy_err_drop;
__le32 mpdu_errs;
} __packed;
struct wmi_pdev_stats_peer {
__le32 dummy;
} __packed;
enum wmi_stats_id {
WMI_STAT_PEER = BIT(0),
WMI_STAT_AP = BIT(1),
WMI_STAT_PDEV = BIT(2),
WMI_STAT_VDEV = BIT(3),
WMI_STAT_BCNFLT = BIT(4),
WMI_STAT_VDEV_RATE = BIT(5),
};
enum wmi_10_4_stats_id {
WMI_10_4_STAT_PEER = BIT(0),
WMI_10_4_STAT_AP = BIT(1),
WMI_10_4_STAT_INST = BIT(2),
WMI_10_4_STAT_PEER_EXTD = BIT(3),
WMI_10_4_STAT_VDEV_EXTD = BIT(4),
};
enum wmi_tlv_stats_id {
WMI_TLV_STAT_PEER = BIT(0),
WMI_TLV_STAT_AP = BIT(1),
WMI_TLV_STAT_PDEV = BIT(2),
WMI_TLV_STAT_VDEV = BIT(3),
WMI_TLV_STAT_PEER_EXTD = BIT(10),
};
struct wlan_inst_rssi_args {
__le16 cfg_retry_count;
__le16 retry_count;
};
struct wmi_request_stats_cmd {
__le32 stats_id;
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
struct wlan_inst_rssi_args inst_rssi_args;
} __packed;
enum wmi_peer_stats_info_request_type {
WMI_REQUEST_ONE_PEER_STATS_INFO = 0x01,
WMI_REQUEST_VDEV_ALL_PEER_STATS_INFO = 0x02,
};
enum {
WMI_PDEV_SUSPEND,
WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
};
struct wmi_pdev_suspend_cmd {
__le32 suspend_opt;
} __packed;
struct wmi_stats_event {
__le32 stats_id;
__le32 num_pdev_stats;
__le32 num_vdev_stats;
__le32 num_peer_stats;
__le32 num_bcnflt_stats;
u8 data[];
} __packed;
struct wmi_10_2_stats_event {
__le32 stats_id;
__le32 num_pdev_stats;
__le32 num_pdev_ext_stats;
__le32 num_vdev_stats;
__le32 num_peer_stats;
__le32 num_bcnflt_stats;
u8 data[];
} __packed;
struct wmi_pdev_stats_base {
__le32 chan_nf;
__le32 tx_frame_count;
__le32 rx_frame_count;
__le32 rx_clear_count;
__le32 cycle_count;
__le32 phy_err_count;
__le32 chan_tx_pwr;
} __packed;
struct wmi_pdev_stats {
struct wmi_pdev_stats_base base;
struct wmi_pdev_stats_tx tx;
struct wmi_pdev_stats_rx rx;
struct wmi_pdev_stats_peer peer;
} __packed;
struct wmi_pdev_stats_extra {
__le32 ack_rx_bad;
__le32 rts_bad;
__le32 rts_good;
__le32 fcs_bad;
__le32 no_beacons;
__le32 mib_int_count;
} __packed;
struct wmi_10x_pdev_stats {
struct wmi_pdev_stats_base base;
struct wmi_pdev_stats_tx tx;
struct wmi_pdev_stats_rx rx;
struct wmi_pdev_stats_peer peer;
struct wmi_pdev_stats_extra extra;
} __packed;
struct wmi_pdev_stats_mem {
__le32 dram_free;
__le32 iram_free;
} __packed;
struct wmi_10_2_pdev_stats {
struct wmi_pdev_stats_base base;
struct wmi_pdev_stats_tx tx;
__le32 mc_drop;
struct wmi_pdev_stats_rx rx;
__le32 pdev_rx_timeout;
struct wmi_pdev_stats_mem mem;
struct wmi_pdev_stats_peer peer;
struct wmi_pdev_stats_extra extra;
} __packed;
struct wmi_10_4_pdev_stats {
struct wmi_pdev_stats_base base;
struct wmi_10_4_pdev_stats_tx tx;
struct wmi_pdev_stats_rx rx;
__le32 rx_ovfl_errs;
struct wmi_pdev_stats_mem mem;
__le32 sram_free_size;
struct wmi_pdev_stats_extra extra;
} __packed;
#define WMI_VDEV_STATS_FTM_COUNT_VALID BIT(31)
#define WMI_VDEV_STATS_FTM_COUNT_LSB 0
#define WMI_VDEV_STATS_FTM_COUNT_MASK 0x7fffffff
struct wmi_vdev_stats {
__le32 vdev_id;
} __packed;
struct wmi_vdev_stats_extd {
__le32 vdev_id;
__le32 ppdu_aggr_cnt;
__le32 ppdu_noack;
__le32 mpdu_queued;
__le32 ppdu_nonaggr_cnt;
__le32 mpdu_sw_requeued;
__le32 mpdu_suc_retry;
__le32 mpdu_suc_multitry;
__le32 mpdu_fail_retry;
__le32 tx_ftm_suc;
__le32 tx_ftm_suc_retry;
__le32 tx_ftm_fail;
__le32 rx_ftmr_cnt;
__le32 rx_ftmr_dup_cnt;
__le32 rx_iftmr_cnt;
__le32 rx_iftmr_dup_cnt;
__le32 reserved[6];
} __packed;
struct wmi_peer_stats {
struct wmi_mac_addr peer_macaddr;
__le32 peer_rssi;
__le32 peer_tx_rate;
} __packed;
struct wmi_10x_peer_stats {
struct wmi_peer_stats old;
__le32 peer_rx_rate;
} __packed;
struct wmi_10_2_peer_stats {
struct wmi_peer_stats old;
__le32 peer_rx_rate;
__le32 current_per;
__le32 retries;
__le32 tx_rate_count;
__le32 max_4ms_frame_len;
__le32 total_sub_frames;
__le32 tx_bytes;
__le32 num_pkt_loss_overflow[4];
__le32 num_pkt_loss_excess_retry[4];
} __packed;
struct wmi_10_2_4_peer_stats {
struct wmi_10_2_peer_stats common;
__le32 peer_rssi_changed;
} __packed;
struct wmi_10_2_4_ext_peer_stats {
struct wmi_10_2_peer_stats common;
__le32 peer_rssi_changed;
__le32 rx_duration;
} __packed;
struct wmi_10_4_peer_stats {
struct wmi_mac_addr peer_macaddr;
__le32 peer_rssi;
__le32 peer_rssi_seq_num;
__le32 peer_tx_rate;
__le32 peer_rx_rate;
__le32 current_per;
__le32 retries;
__le32 tx_rate_count;
__le32 max_4ms_frame_len;
__le32 total_sub_frames;
__le32 tx_bytes;
__le32 num_pkt_loss_overflow[4];
__le32 num_pkt_loss_excess_retry[4];
__le32 peer_rssi_changed;
} __packed;
struct wmi_10_4_peer_extd_stats {
struct wmi_mac_addr peer_macaddr;
__le32 inactive_time;
__le32 peer_chain_rssi;
__le32 rx_duration;
__le32 reserved[10];
} __packed;
struct wmi_10_4_bss_bcn_stats {
__le32 vdev_id;
__le32 bss_bcns_dropped;
__le32 bss_bcn_delivered;
} __packed;
struct wmi_10_4_bss_bcn_filter_stats {
__le32 bcns_dropped;
__le32 bcns_delivered;
__le32 active_filters;
struct wmi_10_4_bss_bcn_stats bss_stats;
} __packed;
struct wmi_10_2_pdev_ext_stats {
__le32 rx_rssi_comb;
__le32 rx_rssi[4];
__le32 rx_mcs[10];
__le32 tx_mcs[10];
__le32 ack_rssi;
} __packed;
struct wmi_vdev_create_cmd {
__le32 vdev_id;
__le32 vdev_type;
__le32 vdev_subtype;
struct wmi_mac_addr vdev_macaddr;
} __packed;
enum wmi_vdev_type {
WMI_VDEV_TYPE_AP = 1,
WMI_VDEV_TYPE_STA = 2,
WMI_VDEV_TYPE_IBSS = 3,
WMI_VDEV_TYPE_MONITOR = 4,
};
enum wmi_vdev_subtype {
WMI_VDEV_SUBTYPE_NONE,
WMI_VDEV_SUBTYPE_P2P_DEVICE,
WMI_VDEV_SUBTYPE_P2P_CLIENT,
WMI_VDEV_SUBTYPE_P2P_GO,
WMI_VDEV_SUBTYPE_PROXY_STA,
WMI_VDEV_SUBTYPE_MESH_11S,
WMI_VDEV_SUBTYPE_MESH_NON_11S,
};
enum wmi_vdev_subtype_legacy {
WMI_VDEV_SUBTYPE_LEGACY_NONE = 0,
WMI_VDEV_SUBTYPE_LEGACY_P2P_DEV = 1,
WMI_VDEV_SUBTYPE_LEGACY_P2P_CLI = 2,
WMI_VDEV_SUBTYPE_LEGACY_P2P_GO = 3,
WMI_VDEV_SUBTYPE_LEGACY_PROXY_STA = 4,
};
enum wmi_vdev_subtype_10_2_4 {
WMI_VDEV_SUBTYPE_10_2_4_NONE = 0,
WMI_VDEV_SUBTYPE_10_2_4_P2P_DEV = 1,
WMI_VDEV_SUBTYPE_10_2_4_P2P_CLI = 2,
WMI_VDEV_SUBTYPE_10_2_4_P2P_GO = 3,
WMI_VDEV_SUBTYPE_10_2_4_PROXY_STA = 4,
WMI_VDEV_SUBTYPE_10_2_4_MESH_11S = 5,
};
enum wmi_vdev_subtype_10_4 {
WMI_VDEV_SUBTYPE_10_4_NONE = 0,
WMI_VDEV_SUBTYPE_10_4_P2P_DEV = 1,
WMI_VDEV_SUBTYPE_10_4_P2P_CLI = 2,
WMI_VDEV_SUBTYPE_10_4_P2P_GO = 3,
WMI_VDEV_SUBTYPE_10_4_PROXY_STA = 4,
WMI_VDEV_SUBTYPE_10_4_MESH_NON_11S = 5,
WMI_VDEV_SUBTYPE_10_4_MESH_11S = 6,
};
#define WMI_VDEV_START_HIDDEN_SSID (1 << 0)
#define WMI_VDEV_START_PMF_ENABLED (1 << 1)
struct wmi_p2p_noa_descriptor {
__le32 type_count;
__le32 duration;
__le32 interval;
__le32 start_time;
} __packed;
struct wmi_vdev_start_request_cmd {
struct wmi_channel chan;
__le32 vdev_id;
__le32 requestor_id;
__le32 beacon_interval;
__le32 dtim_period;
__le32 flags;
struct wmi_ssid ssid;
__le32 bcn_tx_rate;
__le32 bcn_tx_power;
__le32 num_noa_descriptors;
__le32 disable_hw_ack;
struct wmi_p2p_noa_descriptor noa_descriptors[2];
} __packed;
struct wmi_vdev_restart_request_cmd {
struct wmi_vdev_start_request_cmd vdev_start_request_cmd;
} __packed;
struct wmi_vdev_start_request_arg {
u32 vdev_id;
struct wmi_channel_arg channel;
u32 bcn_intval;
u32 dtim_period;
u8 *ssid;
u32 ssid_len;
u32 bcn_tx_rate;
u32 bcn_tx_power;
bool disable_hw_ack;
bool hidden_ssid;
bool pmf_enabled;
};
struct wmi_vdev_delete_cmd {
__le32 vdev_id;
} __packed;
struct wmi_vdev_up_cmd {
__le32 vdev_id;
__le32 vdev_assoc_id;
struct wmi_mac_addr vdev_bssid;
} __packed;
struct wmi_vdev_stop_cmd {
__le32 vdev_id;
} __packed;
struct wmi_vdev_down_cmd {
__le32 vdev_id;
} __packed;
struct wmi_vdev_standby_response_cmd {
__le32 vdev_id;
} __packed;
struct wmi_vdev_resume_response_cmd {
__le32 vdev_id;
} __packed;
struct wmi_vdev_set_param_cmd {
__le32 vdev_id;
__le32 param_id;
__le32 param_value;
} __packed;
#define WMI_MAX_KEY_INDEX 3
#define WMI_MAX_KEY_LEN 32
#define WMI_KEY_PAIRWISE 0x00
#define WMI_KEY_GROUP 0x01
#define WMI_KEY_TX_USAGE 0x02
struct wmi_key_seq_counter {
__le32 key_seq_counter_l;
__le32 key_seq_counter_h;
} __packed;
enum wmi_cipher_suites {
WMI_CIPHER_NONE,
WMI_CIPHER_WEP,
WMI_CIPHER_TKIP,
WMI_CIPHER_AES_OCB,
WMI_CIPHER_AES_CCM,
WMI_CIPHER_WAPI,
WMI_CIPHER_CKIP,
WMI_CIPHER_AES_CMAC,
WMI_CIPHER_AES_GCM,
};
enum wmi_tlv_cipher_suites {
WMI_TLV_CIPHER_NONE,
WMI_TLV_CIPHER_WEP,
WMI_TLV_CIPHER_TKIP,
WMI_TLV_CIPHER_AES_OCB,
WMI_TLV_CIPHER_AES_CCM,
WMI_TLV_CIPHER_WAPI,
WMI_TLV_CIPHER_CKIP,
WMI_TLV_CIPHER_AES_CMAC,
WMI_TLV_CIPHER_ANY,
WMI_TLV_CIPHER_AES_GCM,
};
struct wmi_vdev_install_key_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 key_idx;
__le32 key_flags;
__le32 key_cipher;
struct wmi_key_seq_counter key_rsc_counter;
struct wmi_key_seq_counter key_global_rsc_counter;
struct wmi_key_seq_counter key_tsc_counter;
u8 wpi_key_rsc_counter[16];
u8 wpi_key_tsc_counter[16];
__le32 key_len;
__le32 key_txmic_len;
__le32 key_rxmic_len;
u8 key_data[];
} __packed;
struct wmi_vdev_install_key_arg {
u32 vdev_id;
const u8 *macaddr;
u32 key_idx;
u32 key_flags;
u32 key_cipher;
u32 key_len;
u32 key_txmic_len;
u32 key_rxmic_len;
const void *key_data;
};
enum wmi_rate_preamble {
WMI_RATE_PREAMBLE_OFDM,
WMI_RATE_PREAMBLE_CCK,
WMI_RATE_PREAMBLE_HT,
WMI_RATE_PREAMBLE_VHT,
};
#define ATH10K_HW_NSS(rate) (1 + (((rate) >> 4) & 0x3))
#define ATH10K_HW_PREAMBLE(rate) (((rate) >> 6) & 0x3)
#define ATH10K_HW_MCS_RATE(rate) ((rate) & 0xf)
#define ATH10K_HW_LEGACY_RATE(rate) ((rate) & 0x3f)
#define ATH10K_HW_BW(flags) (((flags) >> 3) & 0x3)
#define ATH10K_HW_GI(flags) (((flags) >> 5) & 0x1)
#define ATH10K_HW_RATECODE(rate, nss, preamble) \
(((preamble) << 6) | ((nss) << 4) | (rate))
#define ATH10K_HW_AMPDU(flags) ((flags) & 0x1)
#define ATH10K_HW_BA_FAIL(flags) (((flags) >> 1) & 0x3)
#define ATH10K_FW_SKIPPED_RATE_CTRL(flags) (((flags) >> 6) & 0x1)
#define ATH10K_VHT_MCS_NUM 10
#define ATH10K_BW_NUM 6
#define ATH10K_NSS_NUM 4
#define ATH10K_LEGACY_NUM 12
#define ATH10K_GI_NUM 2
#define ATH10K_HT_MCS_NUM 32
#define ATH10K_RATE_TABLE_NUM 320
#define ATH10K_RATE_INFO_FLAGS_SGI_BIT 2
#define WMI_FIXED_RATE_NONE (0xff)
struct wmi_peer_param_map {
u32 smps_state;
u32 ampdu;
u32 authorize;
u32 chan_width;
u32 nss;
u32 use_4addr;
u32 membership;
u32 use_fixed_power;
u32 user_pos;
u32 crit_proto_hint_enabled;
u32 tx_fail_cnt_thr;
u32 set_hw_retry_cts2s;
u32 ibss_atim_win_len;
u32 debug;
u32 phymode;
u32 dummy_var;
};
struct wmi_vdev_param_map {
u32 rts_threshold;
u32 fragmentation_threshold;
u32 beacon_interval;
u32 listen_interval;
u32 multicast_rate;
u32 mgmt_tx_rate;
u32 slot_time;
u32 preamble;
u32 swba_time;
u32 wmi_vdev_stats_update_period;
u32 wmi_vdev_pwrsave_ageout_time;
u32 wmi_vdev_host_swba_interval;
u32 dtim_period;
u32 wmi_vdev_oc_scheduler_air_time_limit;
u32 wds;
u32 atim_window;
u32 bmiss_count_max;
u32 bmiss_first_bcnt;
u32 bmiss_final_bcnt;
u32 feature_wmm;
u32 chwidth;
u32 chextoffset;
u32 disable_htprotection;
u32 sta_quickkickout;
u32 mgmt_rate;
u32 protection_mode;
u32 fixed_rate;
u32 sgi;
u32 ldpc;
u32 tx_stbc;
u32 rx_stbc;
u32 intra_bss_fwd;
u32 def_keyid;
u32 nss;
u32 bcast_data_rate;
u32 mcast_data_rate;
u32 mcast_indicate;
u32 dhcp_indicate;
u32 unknown_dest_indicate;
u32 ap_keepalive_min_idle_inactive_time_secs;
u32 ap_keepalive_max_idle_inactive_time_secs;
u32 ap_keepalive_max_unresponsive_time_secs;
u32 ap_enable_nawds;
u32 mcast2ucast_set;
u32 enable_rtscts;
u32 txbf;
u32 packet_powersave;
u32 drop_unencry;
u32 tx_encap_type;
u32 ap_detect_out_of_sync_sleeping_sta_time_secs;
u32 rc_num_retries;
u32 cabq_maxdur;
u32 mfptest_set;
u32 rts_fixed_rate;
u32 vht_sgimask;
u32 vht80_ratemask;
u32 early_rx_adjust_enable;
u32 early_rx_tgt_bmiss_num;
u32 early_rx_bmiss_sample_cycle;
u32 early_rx_slop_step;
u32 early_rx_init_slop;
u32 early_rx_adjust_pause;
u32 proxy_sta;
u32 meru_vc;
u32 rx_decap_type;
u32 bw_nss_ratemask;
u32 inc_tsf;
u32 dec_tsf;
u32 disable_4addr_src_lrn;
u32 rtt_responder_role;
};
#define WMI_VDEV_PARAM_UNSUPPORTED 0
enum wmi_vdev_param {
WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1,
WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
WMI_VDEV_PARAM_BEACON_INTERVAL,
WMI_VDEV_PARAM_LISTEN_INTERVAL,
WMI_VDEV_PARAM_MULTICAST_RATE,
WMI_VDEV_PARAM_MGMT_TX_RATE,
WMI_VDEV_PARAM_SLOT_TIME,
WMI_VDEV_PARAM_PREAMBLE,
WMI_VDEV_PARAM_SWBA_TIME,
WMI_VDEV_STATS_UPDATE_PERIOD,
WMI_VDEV_PWRSAVE_AGEOUT_TIME,
WMI_VDEV_HOST_SWBA_INTERVAL,
WMI_VDEV_PARAM_DTIM_PERIOD,
WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
WMI_VDEV_PARAM_WDS,
WMI_VDEV_PARAM_ATIM_WINDOW,
WMI_VDEV_PARAM_BMISS_COUNT_MAX,
WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
WMI_VDEV_PARAM_FEATURE_WMM,
WMI_VDEV_PARAM_CHWIDTH,
WMI_VDEV_PARAM_CHEXTOFFSET,
WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
WMI_VDEV_PARAM_STA_QUICKKICKOUT,
WMI_VDEV_PARAM_MGMT_RATE,
WMI_VDEV_PARAM_PROTECTION_MODE,
WMI_VDEV_PARAM_FIXED_RATE,
WMI_VDEV_PARAM_SGI,
WMI_VDEV_PARAM_LDPC,
WMI_VDEV_PARAM_TX_STBC,
WMI_VDEV_PARAM_RX_STBC,
WMI_VDEV_PARAM_INTRA_BSS_FWD,
WMI_VDEV_PARAM_DEF_KEYID,
WMI_VDEV_PARAM_NSS,
WMI_VDEV_PARAM_BCAST_DATA_RATE,
WMI_VDEV_PARAM_MCAST_DATA_RATE,
WMI_VDEV_PARAM_MCAST_INDICATE,
WMI_VDEV_PARAM_DHCP_INDICATE,
WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
WMI_VDEV_PARAM_ENABLE_RTSCTS,
WMI_VDEV_PARAM_TXBF,
WMI_VDEV_PARAM_PACKET_POWERSAVE,
WMI_VDEV_PARAM_DROP_UNENCRY,
WMI_VDEV_PARAM_TX_ENCAP_TYPE,
};
enum wmi_10x_vdev_param {
WMI_10X_VDEV_PARAM_RTS_THRESHOLD = 0x1,
WMI_10X_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
WMI_10X_VDEV_PARAM_BEACON_INTERVAL,
WMI_10X_VDEV_PARAM_LISTEN_INTERVAL,
WMI_10X_VDEV_PARAM_MULTICAST_RATE,
WMI_10X_VDEV_PARAM_MGMT_TX_RATE,
WMI_10X_VDEV_PARAM_SLOT_TIME,
WMI_10X_VDEV_PARAM_PREAMBLE,
WMI_10X_VDEV_PARAM_SWBA_TIME,
WMI_10X_VDEV_STATS_UPDATE_PERIOD,
WMI_10X_VDEV_PWRSAVE_AGEOUT_TIME,
WMI_10X_VDEV_HOST_SWBA_INTERVAL,
WMI_10X_VDEV_PARAM_DTIM_PERIOD,
WMI_10X_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
WMI_10X_VDEV_PARAM_WDS,
WMI_10X_VDEV_PARAM_ATIM_WINDOW,
WMI_10X_VDEV_PARAM_BMISS_COUNT_MAX,
WMI_10X_VDEV_PARAM_FEATURE_WMM,
WMI_10X_VDEV_PARAM_CHWIDTH,
WMI_10X_VDEV_PARAM_CHEXTOFFSET,
WMI_10X_VDEV_PARAM_DISABLE_HTPROTECTION,
WMI_10X_VDEV_PARAM_STA_QUICKKICKOUT,
WMI_10X_VDEV_PARAM_MGMT_RATE,
WMI_10X_VDEV_PARAM_PROTECTION_MODE,
WMI_10X_VDEV_PARAM_FIXED_RATE,
WMI_10X_VDEV_PARAM_SGI,
WMI_10X_VDEV_PARAM_LDPC,
WMI_10X_VDEV_PARAM_TX_STBC,
WMI_10X_VDEV_PARAM_RX_STBC,
WMI_10X_VDEV_PARAM_INTRA_BSS_FWD,
WMI_10X_VDEV_PARAM_DEF_KEYID,
WMI_10X_VDEV_PARAM_NSS,
WMI_10X_VDEV_PARAM_BCAST_DATA_RATE,
WMI_10X_VDEV_PARAM_MCAST_DATA_RATE,
WMI_10X_VDEV_PARAM_MCAST_INDICATE,
WMI_10X_VDEV_PARAM_DHCP_INDICATE,
WMI_10X_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
WMI_10X_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
WMI_10X_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
WMI_10X_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
WMI_10X_VDEV_PARAM_AP_ENABLE_NAWDS,
WMI_10X_VDEV_PARAM_MCAST2UCAST_SET,
WMI_10X_VDEV_PARAM_ENABLE_RTSCTS,
WMI_10X_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
WMI_10X_VDEV_PARAM_TX_ENCAP_TYPE,
WMI_10X_VDEV_PARAM_CABQ_MAXDUR,
WMI_10X_VDEV_PARAM_MFPTEST_SET,
WMI_10X_VDEV_PARAM_RTS_FIXED_RATE,
WMI_10X_VDEV_PARAM_VHT_SGIMASK,
WMI_10X_VDEV_PARAM_VHT80_RATEMASK,
WMI_10X_VDEV_PARAM_TSF_INCREMENT,
};
enum wmi_10_4_vdev_param {
WMI_10_4_VDEV_PARAM_RTS_THRESHOLD = 0x1,
WMI_10_4_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
WMI_10_4_VDEV_PARAM_BEACON_INTERVAL,
WMI_10_4_VDEV_PARAM_LISTEN_INTERVAL,
WMI_10_4_VDEV_PARAM_MULTICAST_RATE,
WMI_10_4_VDEV_PARAM_MGMT_TX_RATE,
WMI_10_4_VDEV_PARAM_SLOT_TIME,
WMI_10_4_VDEV_PARAM_PREAMBLE,
WMI_10_4_VDEV_PARAM_SWBA_TIME,
WMI_10_4_VDEV_STATS_UPDATE_PERIOD,
WMI_10_4_VDEV_PWRSAVE_AGEOUT_TIME,
WMI_10_4_VDEV_HOST_SWBA_INTERVAL,
WMI_10_4_VDEV_PARAM_DTIM_PERIOD,
WMI_10_4_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
WMI_10_4_VDEV_PARAM_WDS,
WMI_10_4_VDEV_PARAM_ATIM_WINDOW,
WMI_10_4_VDEV_PARAM_BMISS_COUNT_MAX,
WMI_10_4_VDEV_PARAM_BMISS_FIRST_BCNT,
WMI_10_4_VDEV_PARAM_BMISS_FINAL_BCNT,
WMI_10_4_VDEV_PARAM_FEATURE_WMM,
WMI_10_4_VDEV_PARAM_CHWIDTH,
WMI_10_4_VDEV_PARAM_CHEXTOFFSET,
WMI_10_4_VDEV_PARAM_DISABLE_HTPROTECTION,
WMI_10_4_VDEV_PARAM_STA_QUICKKICKOUT,
WMI_10_4_VDEV_PARAM_MGMT_RATE,
WMI_10_4_VDEV_PARAM_PROTECTION_MODE,
WMI_10_4_VDEV_PARAM_FIXED_RATE,
WMI_10_4_VDEV_PARAM_SGI,
WMI_10_4_VDEV_PARAM_LDPC,
WMI_10_4_VDEV_PARAM_TX_STBC,
WMI_10_4_VDEV_PARAM_RX_STBC,
WMI_10_4_VDEV_PARAM_INTRA_BSS_FWD,
WMI_10_4_VDEV_PARAM_DEF_KEYID,
WMI_10_4_VDEV_PARAM_NSS,
WMI_10_4_VDEV_PARAM_BCAST_DATA_RATE,
WMI_10_4_VDEV_PARAM_MCAST_DATA_RATE,
WMI_10_4_VDEV_PARAM_MCAST_INDICATE,
WMI_10_4_VDEV_PARAM_DHCP_INDICATE,
WMI_10_4_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
WMI_10_4_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
WMI_10_4_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
WMI_10_4_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
WMI_10_4_VDEV_PARAM_AP_ENABLE_NAWDS,
WMI_10_4_VDEV_PARAM_MCAST2UCAST_SET,
WMI_10_4_VDEV_PARAM_ENABLE_RTSCTS,
WMI_10_4_VDEV_PARAM_RC_NUM_RETRIES,
WMI_10_4_VDEV_PARAM_TXBF,
WMI_10_4_VDEV_PARAM_PACKET_POWERSAVE,
WMI_10_4_VDEV_PARAM_DROP_UNENCRY,
WMI_10_4_VDEV_PARAM_TX_ENCAP_TYPE,
WMI_10_4_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
WMI_10_4_VDEV_PARAM_CABQ_MAXDUR,
WMI_10_4_VDEV_PARAM_MFPTEST_SET,
WMI_10_4_VDEV_PARAM_RTS_FIXED_RATE,
WMI_10_4_VDEV_PARAM_VHT_SGIMASK,
WMI_10_4_VDEV_PARAM_VHT80_RATEMASK,
WMI_10_4_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE,
WMI_10_4_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM,
WMI_10_4_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE,
WMI_10_4_VDEV_PARAM_EARLY_RX_SLOP_STEP,
WMI_10_4_VDEV_PARAM_EARLY_RX_INIT_SLOP,
WMI_10_4_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE,
WMI_10_4_VDEV_PARAM_PROXY_STA,
WMI_10_4_VDEV_PARAM_MERU_VC,
WMI_10_4_VDEV_PARAM_RX_DECAP_TYPE,
WMI_10_4_VDEV_PARAM_BW_NSS_RATEMASK,
WMI_10_4_VDEV_PARAM_SENSOR_AP,
WMI_10_4_VDEV_PARAM_BEACON_RATE,
WMI_10_4_VDEV_PARAM_DTIM_ENABLE_CTS,
WMI_10_4_VDEV_PARAM_STA_KICKOUT,
WMI_10_4_VDEV_PARAM_CAPABILITIES,
WMI_10_4_VDEV_PARAM_TSF_INCREMENT,
WMI_10_4_VDEV_PARAM_RX_FILTER,
WMI_10_4_VDEV_PARAM_MGMT_TX_POWER,
WMI_10_4_VDEV_PARAM_ATF_SSID_SCHED_POLICY,
WMI_10_4_VDEV_PARAM_DISABLE_DYN_BW_RTS,
WMI_10_4_VDEV_PARAM_TSF_DECREMENT,
WMI_10_4_VDEV_PARAM_SELFGEN_FIXED_RATE,
WMI_10_4_VDEV_PARAM_AMPDU_SUBFRAME_SIZE_PER_AC,
WMI_10_4_VDEV_PARAM_NSS_VHT160,
WMI_10_4_VDEV_PARAM_NSS_VHT80_80,
WMI_10_4_VDEV_PARAM_AMSDU_SUBFRAME_SIZE_PER_AC,
WMI_10_4_VDEV_PARAM_DISABLE_CABQ,
WMI_10_4_VDEV_PARAM_SIFS_TRIGGER_RATE,
WMI_10_4_VDEV_PARAM_TX_POWER,
WMI_10_4_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE,
WMI_10_4_VDEV_PARAM_DISABLE_4_ADDR_SRC_LRN,
};
#define WMI_VDEV_DISABLE_4_ADDR_SRC_LRN 1
#define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
#define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
#define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
#define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
#define WMI_TXBF_STS_CAP_OFFSET_LSB 4
#define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70
#define WMI_TXBF_CONF_IMPLICIT_BF BIT(7)
#define WMI_BF_SOUND_DIM_OFFSET_LSB 8
#define WMI_BF_SOUND_DIM_OFFSET_MASK 0xf00
#define WMI_VDEV_SLOT_TIME_LONG 0x1
#define WMI_VDEV_SLOT_TIME_SHORT 0x2
#define WMI_VDEV_PREAMBLE_LONG 0x1
#define WMI_VDEV_PREAMBLE_SHORT 0x2
enum wmi_start_event_param {
WMI_VDEV_RESP_START_EVENT = 0,
WMI_VDEV_RESP_RESTART_EVENT,
};
struct wmi_vdev_start_response_event {
__le32 vdev_id;
__le32 req_id;
__le32 resp_type;
__le32 status;
} __packed;
struct wmi_vdev_standby_req_event {
__le32 vdev_id;
} __packed;
struct wmi_vdev_resume_req_event {
__le32 vdev_id;
} __packed;
struct wmi_vdev_stopped_event {
__le32 vdev_id;
} __packed;
struct wmi_vdev_simple_event {
__le32 vdev_id;
} __packed;
#define WMI_INIFIED_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0
#define WMI_INIFIED_VDEV_START_RESPONSE_INVALID_VDEVID 0x1
#define WMI_INIFIED_VDEV_START_RESPONSE_NOT_SUPPORTED 0x2
struct wmi_vdev_spectral_conf_cmd {
__le32 vdev_id;
__le32 scan_count;
__le32 scan_period;
__le32 scan_priority;
__le32 scan_fft_size;
__le32 scan_gc_ena;
__le32 scan_restart_ena;
__le32 scan_noise_floor_ref;
__le32 scan_init_delay;
__le32 scan_nb_tone_thr;
__le32 scan_str_bin_thr;
__le32 scan_wb_rpt_mode;
__le32 scan_rssi_rpt_mode;
__le32 scan_rssi_thr;
__le32 scan_pwr_format;
__le32 scan_rpt_mode;
__le32 scan_bin_scale;
__le32 scan_dbm_adj;
__le32 scan_chn_mask;
} __packed;
struct wmi_vdev_spectral_conf_arg {
u32 vdev_id;
u32 scan_count;
u32 scan_period;
u32 scan_priority;
u32 scan_fft_size;
u32 scan_gc_ena;
u32 scan_restart_ena;
u32 scan_noise_floor_ref;
u32 scan_init_delay;
u32 scan_nb_tone_thr;
u32 scan_str_bin_thr;
u32 scan_wb_rpt_mode;
u32 scan_rssi_rpt_mode;
u32 scan_rssi_thr;
u32 scan_pwr_format;
u32 scan_rpt_mode;
u32 scan_bin_scale;
u32 scan_dbm_adj;
u32 scan_chn_mask;
};
#define WMI_SPECTRAL_ENABLE_DEFAULT 0
#define WMI_SPECTRAL_COUNT_DEFAULT 0
#define WMI_SPECTRAL_PERIOD_DEFAULT 35
#define WMI_SPECTRAL_PRIORITY_DEFAULT 1
#define WMI_SPECTRAL_FFT_SIZE_DEFAULT 7
#define WMI_SPECTRAL_GC_ENA_DEFAULT 1
#define WMI_SPECTRAL_RESTART_ENA_DEFAULT 0
#define WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96
#define WMI_SPECTRAL_INIT_DELAY_DEFAULT 80
#define WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12
#define WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8
#define WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0
#define WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0
#define WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0
#define WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0
#define WMI_SPECTRAL_RPT_MODE_DEFAULT 2
#define WMI_SPECTRAL_BIN_SCALE_DEFAULT 1
#define WMI_SPECTRAL_DBM_ADJ_DEFAULT 1
#define WMI_SPECTRAL_CHN_MASK_DEFAULT 1
struct wmi_vdev_spectral_enable_cmd {
__le32 vdev_id;
__le32 trigger_cmd;
__le32 enable_cmd;
} __packed;
#define WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1
#define WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2
#define WMI_SPECTRAL_ENABLE_CMD_ENABLE 1
#define WMI_SPECTRAL_ENABLE_CMD_DISABLE 2
struct wmi_bcn_tx_hdr {
__le32 vdev_id;
__le32 tx_rate;
__le32 tx_power;
__le32 bcn_len;
} __packed;
struct wmi_bcn_tx_cmd {
struct wmi_bcn_tx_hdr hdr;
u8 *bcn[];
} __packed;
struct wmi_bcn_tx_arg {
u32 vdev_id;
u32 tx_rate;
u32 tx_power;
u32 bcn_len;
const void *bcn;
};
enum wmi_bcn_tx_ref_flags {
WMI_BCN_TX_REF_FLAG_DTIM_ZERO = 0x1,
WMI_BCN_TX_REF_FLAG_DELIVER_CAB = 0x2,
};
#define WMI_BCN_TX_REF_DEF_ANTENNA 0
struct wmi_bcn_tx_ref_cmd {
__le32 vdev_id;
__le32 data_len;
__le32 data_ptr;
__le32 msdu_id;
__le32 frame_control;
__le32 flags;
__le32 antenna_mask;
} __packed;
#define WMI_BCN_FILTER_ALL 0
#define WMI_BCN_FILTER_NONE 1
#define WMI_BCN_FILTER_RSSI 2
#define WMI_BCN_FILTER_BSSID 3
#define WMI_BCN_FILTER_SSID 4
struct wmi_bcn_filter_rx_cmd {
__le32 bcn_filter_id;
__le32 bcn_filter;
__le32 bcn_filter_len;
u8 *bcn_filter_buf;
} __packed;
struct wmi_bcn_prb_info {
__le32 caps;
__le32 erp;
} __packed;
enum wmi_sta_ps_mode {
WMI_STA_PS_MODE_DISABLED = 0,
WMI_STA_PS_MODE_ENABLED = 1,
};
struct wmi_sta_powersave_mode_cmd {
__le32 vdev_id;
__le32 sta_ps_mode;
} __packed;
enum wmi_csa_offload_en {
WMI_CSA_OFFLOAD_DISABLE = 0,
WMI_CSA_OFFLOAD_ENABLE = 1,
};
struct wmi_csa_offload_enable_cmd {
__le32 vdev_id;
__le32 csa_offload_enable;
} __packed;
struct wmi_csa_offload_chanswitch_cmd {
__le32 vdev_id;
struct wmi_channel chan;
} __packed;
enum wmi_sta_ps_param_rx_wake_policy {
WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0,
WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1,
};
enum wmi_sta_ps_param_tx_wake_threshold {
WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0,
WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1,
};
enum wmi_sta_ps_param_pspoll_count {
WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
WMI_STA_PS_PSPOLL_COUNT_UAPSD = 3,
};
#define WMI_UAPSD_AC_TYPE_DELI 0
#define WMI_UAPSD_AC_TYPE_TRIG 1
#define WMI_UAPSD_AC_BIT_MASK(ac, type) \
(type == WMI_UAPSD_AC_TYPE_DELI ? 1 << (ac << 1) : 1 << ((ac << 1) + 1))
enum wmi_sta_ps_param_uapsd {
WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
};
#define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX
struct wmi_sta_uapsd_auto_trig_param {
__le32 wmm_ac;
__le32 user_priority;
__le32 service_interval;
__le32 suspend_interval;
__le32 delay_interval;
};
struct wmi_sta_uapsd_auto_trig_cmd_fixed_param {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 num_ac;
};
struct wmi_sta_uapsd_auto_trig_arg {
u32 wmm_ac;
u32 user_priority;
u32 service_interval;
u32 suspend_interval;
u32 delay_interval;
};
enum wmi_sta_powersave_param {
WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0,
WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1,
WMI_STA_PS_PARAM_PSPOLL_COUNT = 2,
WMI_STA_PS_PARAM_INACTIVITY_TIME = 3,
WMI_STA_PS_PARAM_UAPSD = 4,
};
struct wmi_sta_powersave_param_cmd {
__le32 vdev_id;
__le32 param_id;
__le32 param_value;
} __packed;
#define WMI_STA_MIMO_PS_MODE_DISABLE
#define WMI_STA_MIMO_PS_MODE_STATIC
#define WMI_STA_MIMO_PS_MODE_DYNAMIC
struct wmi_sta_mimo_ps_mode_cmd {
__le32 vdev_id;
__le32 mimo_pwrsave_mode;
} __packed;
enum wmi_ap_ps_param_uapsd {
WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
};
enum wmi_ap_ps_peer_param_max_sp {
WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0,
WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1,
WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2,
WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3,
MAX_WMI_AP_PS_PEER_PARAM_MAX_SP,
};
enum wmi_ap_ps_peer_param {
WMI_AP_PS_PEER_PARAM_UAPSD = 0,
WMI_AP_PS_PEER_PARAM_MAX_SP = 1,
WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2,
};
struct wmi_ap_ps_peer_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 param_id;
__le32 param_value;
} __packed;
#define WMI_TIM_BITMAP_ARRAY_SIZE 4
struct wmi_tim_info {
__le32 tim_len;
__le32 tim_mcast;
__le32 tim_bitmap[WMI_TIM_BITMAP_ARRAY_SIZE];
__le32 tim_changed;
__le32 tim_num_ps_pending;
} __packed;
struct wmi_tim_info_arg {
__le32 tim_len;
__le32 tim_mcast;
const __le32 *tim_bitmap;
__le32 tim_changed;
__le32 tim_num_ps_pending;
} __packed;
#define WMI_P2P_MAX_NOA_DESCRIPTORS 4
#define WMI_P2P_OPPPS_ENABLE_BIT BIT(0)
#define WMI_P2P_OPPPS_CTWINDOW_OFFSET 1
#define WMI_P2P_NOA_CHANGED_BIT BIT(0)
struct wmi_p2p_noa_info {
u8 changed;
u8 index;
u8 ctwindow_oppps;
u8 num_descriptors;
struct wmi_p2p_noa_descriptor descriptors[WMI_P2P_MAX_NOA_DESCRIPTORS];
} __packed;
struct wmi_bcn_info {
struct wmi_tim_info tim_info;
struct wmi_p2p_noa_info p2p_noa_info;
} __packed;
struct wmi_host_swba_event {
__le32 vdev_map;
struct wmi_bcn_info bcn_info[];
} __packed;
struct wmi_10_2_4_bcn_info {
struct wmi_tim_info tim_info;
} __packed;
struct wmi_10_2_4_host_swba_event {
__le32 vdev_map;
struct wmi_10_2_4_bcn_info bcn_info[];
} __packed;
#define WMI_10_4_TIM_BITMAP_ARRAY_SIZE 17
struct wmi_10_4_tim_info {
__le32 tim_len;
__le32 tim_mcast;
__le32 tim_bitmap[WMI_10_4_TIM_BITMAP_ARRAY_SIZE];
__le32 tim_changed;
__le32 tim_num_ps_pending;
} __packed;
#define WMI_10_4_P2P_MAX_NOA_DESCRIPTORS 1
struct wmi_10_4_p2p_noa_info {
u8 changed;
u8 index;
u8 ctwindow_oppps;
u8 num_descriptors;
struct wmi_p2p_noa_descriptor
noa_descriptors[WMI_10_4_P2P_MAX_NOA_DESCRIPTORS];
} __packed;
struct wmi_10_4_bcn_info {
struct wmi_10_4_tim_info tim_info;
struct wmi_10_4_p2p_noa_info p2p_noa_info;
} __packed;
struct wmi_10_4_host_swba_event {
__le32 vdev_map;
struct wmi_10_4_bcn_info bcn_info[];
} __packed;
#define WMI_MAX_AP_VDEV 16
struct wmi_tbtt_offset_event {
__le32 vdev_map;
__le32 tbttoffset_list[WMI_MAX_AP_VDEV];
} __packed;
struct wmi_peer_create_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 peer_type;
} __packed;
enum wmi_peer_type {
WMI_PEER_TYPE_DEFAULT = 0,
WMI_PEER_TYPE_BSS = 1,
WMI_PEER_TYPE_TDLS = 2,
};
struct wmi_peer_delete_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
} __packed;
struct wmi_peer_flush_tids_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 peer_tid_bitmap;
} __packed;
struct wmi_fixed_rate {
__le32 rate_mode;
__le32 rate_series;
__le32 rate_retries;
} __packed;
struct wmi_peer_fixed_rate_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
struct wmi_fixed_rate peer_fixed_rate;
} __packed;
#define WMI_MGMT_TID 17
struct wmi_addba_clear_resp_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
} __packed;
struct wmi_addba_send_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 tid;
__le32 buffersize;
} __packed;
struct wmi_delba_send_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 tid;
__le32 initiator;
__le32 reasoncode;
} __packed;
struct wmi_addba_setresponse_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 tid;
__le32 statuscode;
} __packed;
struct wmi_send_singleamsdu_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 tid;
} __packed;
enum wmi_peer_smps_state {
WMI_PEER_SMPS_PS_NONE = 0x0,
WMI_PEER_SMPS_STATIC = 0x1,
WMI_PEER_SMPS_DYNAMIC = 0x2
};
enum wmi_peer_chwidth {
WMI_PEER_CHWIDTH_20MHZ = 0,
WMI_PEER_CHWIDTH_40MHZ = 1,
WMI_PEER_CHWIDTH_80MHZ = 2,
WMI_PEER_CHWIDTH_160MHZ = 3,
};
enum wmi_peer_param {
WMI_PEER_SMPS_STATE = 0x1,
WMI_PEER_AMPDU = 0x2,
WMI_PEER_AUTHORIZE = 0x3,
WMI_PEER_CHAN_WIDTH = 0x4,
WMI_PEER_NSS = 0x5,
WMI_PEER_USE_4ADDR = 0x6,
WMI_PEER_USE_FIXED_PWR = 0x8,
WMI_PEER_PARAM_FIXED_RATE = 0x9,
WMI_PEER_DEBUG = 0xa,
WMI_PEER_PHYMODE = 0xd,
WMI_PEER_DUMMY_VAR = 0xff,
};
struct wmi_peer_set_param_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 param_id;
__le32 param_value;
} __packed;
#define MAX_SUPPORTED_RATES 128
struct wmi_rate_set {
__le32 num_rates;
__le32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
} __packed;
struct wmi_rate_set_arg {
unsigned int num_rates;
u8 rates[MAX_SUPPORTED_RATES];
};
struct wmi_vht_rate_set {
__le32 rx_max_rate;
__le32 rx_mcs_set;
__le32 tx_max_rate;
__le32 tx_mcs_set;
} __packed;
struct wmi_vht_rate_set_arg {
u32 rx_max_rate;
u32 rx_mcs_set;
u32 tx_max_rate;
u32 tx_mcs_set;
};
struct wmi_peer_set_rates_cmd {
struct wmi_mac_addr peer_macaddr;
struct wmi_rate_set peer_legacy_rates;
struct wmi_rate_set peer_ht_rates;
} __packed;
struct wmi_peer_set_q_empty_callback_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 callback_enable;
} __packed;
struct wmi_peer_flags_map {
u32 auth;
u32 qos;
u32 need_ptk_4_way;
u32 need_gtk_2_way;
u32 apsd;
u32 ht;
u32 bw40;
u32 stbc;
u32 ldbc;
u32 dyn_mimops;
u32 static_mimops;
u32 spatial_mux;
u32 vht;
u32 bw80;
u32 vht_2g;
u32 pmf;
u32 bw160;
};
enum wmi_peer_flags {
WMI_PEER_AUTH = 0x00000001,
WMI_PEER_QOS = 0x00000002,
WMI_PEER_NEED_PTK_4_WAY = 0x00000004,
WMI_PEER_NEED_GTK_2_WAY = 0x00000010,
WMI_PEER_APSD = 0x00000800,
WMI_PEER_HT = 0x00001000,
WMI_PEER_40MHZ = 0x00002000,
WMI_PEER_STBC = 0x00008000,
WMI_PEER_LDPC = 0x00010000,
WMI_PEER_DYN_MIMOPS = 0x00020000,
WMI_PEER_STATIC_MIMOPS = 0x00040000,
WMI_PEER_SPATIAL_MUX = 0x00200000,
WMI_PEER_VHT = 0x02000000,
WMI_PEER_80MHZ = 0x04000000,
WMI_PEER_VHT_2G = 0x08000000,
WMI_PEER_PMF = 0x10000000,
WMI_PEER_160MHZ = 0x20000000
};
enum wmi_10x_peer_flags {
WMI_10X_PEER_AUTH = 0x00000001,
WMI_10X_PEER_QOS = 0x00000002,
WMI_10X_PEER_NEED_PTK_4_WAY = 0x00000004,
WMI_10X_PEER_NEED_GTK_2_WAY = 0x00000010,
WMI_10X_PEER_APSD = 0x00000800,
WMI_10X_PEER_HT = 0x00001000,
WMI_10X_PEER_40MHZ = 0x00002000,
WMI_10X_PEER_STBC = 0x00008000,
WMI_10X_PEER_LDPC = 0x00010000,
WMI_10X_PEER_DYN_MIMOPS = 0x00020000,
WMI_10X_PEER_STATIC_MIMOPS = 0x00040000,
WMI_10X_PEER_SPATIAL_MUX = 0x00200000,
WMI_10X_PEER_VHT = 0x02000000,
WMI_10X_PEER_80MHZ = 0x04000000,
WMI_10X_PEER_160MHZ = 0x20000000
};
enum wmi_10_2_peer_flags {
WMI_10_2_PEER_AUTH = 0x00000001,
WMI_10_2_PEER_QOS = 0x00000002,
WMI_10_2_PEER_NEED_PTK_4_WAY = 0x00000004,
WMI_10_2_PEER_NEED_GTK_2_WAY = 0x00000010,
WMI_10_2_PEER_APSD = 0x00000800,
WMI_10_2_PEER_HT = 0x00001000,
WMI_10_2_PEER_40MHZ = 0x00002000,
WMI_10_2_PEER_STBC = 0x00008000,
WMI_10_2_PEER_LDPC = 0x00010000,
WMI_10_2_PEER_DYN_MIMOPS = 0x00020000,
WMI_10_2_PEER_STATIC_MIMOPS = 0x00040000,
WMI_10_2_PEER_SPATIAL_MUX = 0x00200000,
WMI_10_2_PEER_VHT = 0x02000000,
WMI_10_2_PEER_80MHZ = 0x04000000,
WMI_10_2_PEER_VHT_2G = 0x08000000,
WMI_10_2_PEER_PMF = 0x10000000,
WMI_10_2_PEER_160MHZ = 0x20000000
};
#define WMI_RC_DS_FLAG 0x01
#define WMI_RC_CW40_FLAG 0x02
#define WMI_RC_SGI_FLAG 0x04
#define WMI_RC_HT_FLAG 0x08
#define WMI_RC_RTSCTS_FLAG 0x10
#define WMI_RC_TX_STBC_FLAG 0x20
#define WMI_RC_RX_STBC_FLAG 0xC0
#define WMI_RC_RX_STBC_FLAG_S 6
#define WMI_RC_WEP_TKIP_FLAG 0x100
#define WMI_RC_TS_FLAG 0x200
#define WMI_RC_UAPSD_FLAG 0x400
#define ATH10K_MAX_HW_LISTEN_INTERVAL 5
struct wmi_common_peer_assoc_complete_cmd {
struct wmi_mac_addr peer_macaddr;
__le32 vdev_id;
__le32 peer_new_assoc;
__le32 peer_associd;
__le32 peer_flags;
__le32 peer_caps;
__le32 peer_listen_intval;
__le32 peer_ht_caps;
__le32 peer_max_mpdu;
__le32 peer_mpdu_density;
__le32 peer_rate_caps;
struct wmi_rate_set peer_legacy_rates;
struct wmi_rate_set peer_ht_rates;
__le32 peer_nss;
__le32 peer_vht_caps;
__le32 peer_phymode;
struct wmi_vht_rate_set peer_vht_rates;
};
struct wmi_main_peer_assoc_complete_cmd {
struct wmi_common_peer_assoc_complete_cmd cmd;
__le32 peer_ht_info[2];
} __packed;
struct wmi_10_1_peer_assoc_complete_cmd {
struct wmi_common_peer_assoc_complete_cmd cmd;
} __packed;
#define WMI_PEER_ASSOC_INFO0_MAX_MCS_IDX_LSB 0
#define WMI_PEER_ASSOC_INFO0_MAX_MCS_IDX_MASK 0x0f
#define WMI_PEER_ASSOC_INFO0_MAX_NSS_LSB 4
#define WMI_PEER_ASSOC_INFO0_MAX_NSS_MASK 0xf0
struct wmi_10_2_peer_assoc_complete_cmd {
struct wmi_common_peer_assoc_complete_cmd cmd;
__le32 info0;
} __packed;
#define WMI_PEER_NSS_MAP_ENABLE BIT(31)
#define WMI_PEER_NSS_160MHZ_MASK GENMASK(2, 0)
#define WMI_PEER_NSS_80_80MHZ_MASK GENMASK(5, 3)
struct wmi_10_4_peer_assoc_complete_cmd {
struct wmi_10_2_peer_assoc_complete_cmd cmd;
__le32 peer_bw_rxnss_override;
} __packed;
struct wmi_peer_assoc_complete_arg {
u8 addr[ETH_ALEN];
u32 vdev_id;
bool peer_reassoc;
u16 peer_aid;
u32 peer_flags;
u16 peer_caps;
u32 peer_listen_intval;
u32 peer_ht_caps;
u32 peer_max_mpdu;
u32 peer_mpdu_density;
u32 peer_rate_caps;
struct wmi_rate_set_arg peer_legacy_rates;
struct wmi_rate_set_arg peer_ht_rates;
u32 peer_num_spatial_streams;
u32 peer_vht_caps;
enum wmi_phy_mode peer_phymode;
struct wmi_vht_rate_set_arg peer_vht_rates;
u32 peer_bw_rxnss_override;
};
struct wmi_peer_add_wds_entry_cmd {
struct wmi_mac_addr peer_macaddr;
struct wmi_mac_addr wds_macaddr;
} __packed;
struct wmi_peer_remove_wds_entry_cmd {
struct wmi_mac_addr wds_macaddr;
} __packed;
struct wmi_peer_q_empty_callback_event {
struct wmi_mac_addr peer_macaddr;
} __packed;
struct wmi_chan_info_event {
__le32 err_code;
__le32 freq;
__le32 cmd_flags;
__le32 noise_floor;
__le32 rx_clear_count;
__le32 cycle_count;
} __packed;
struct wmi_10_4_chan_info_event {
__le32 err_code;
__le32 freq;
__le32 cmd_flags;
__le32 noise_floor;
__le32 rx_clear_count;
__le32 cycle_count;
__le32 chan_tx_pwr_range;
__le32 chan_tx_pwr_tp;
__le32 rx_frame_count;
} __packed;
struct wmi_peer_sta_kickout_event {
struct wmi_mac_addr peer_macaddr;
} __packed;
#define WMI_CHAN_INFO_FLAG_COMPLETE BIT(0)
#define WMI_CHAN_INFO_FLAG_PRE_COMPLETE BIT(1)
#define BCN_FLT_MAX_SUPPORTED_IES 256
#define BCN_FLT_MAX_ELEMS_IE_LIST (BCN_FLT_MAX_SUPPORTED_IES / 32)
struct bss_bcn_stats {
__le32 vdev_id;
__le32 bss_bcnsdropped;
__le32 bss_bcnsdelivered;
} __packed;
struct bcn_filter_stats {
__le32 bcns_dropped;
__le32 bcns_delivered;
__le32 activefilters;
struct bss_bcn_stats bss_stats;
} __packed;
struct wmi_add_bcn_filter_cmd {
u32 vdev_id;
u32 ie_map[BCN_FLT_MAX_ELEMS_IE_LIST];
} __packed;
enum wmi_sta_keepalive_method {
WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1,
WMI_STA_KEEPALIVE_METHOD_UNSOLICITATED_ARP_RESPONSE = 2,
};
#define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0
#define WMI_STA_KEEPALIVE_INTERVAL_MAX_SECONDS 0xffff
struct wmi_sta_keepalive_arp_resp {
__be32 src_ip4_addr;
__be32 dest_ip4_addr;
struct wmi_mac_addr dest_mac_addr;
} __packed;
struct wmi_sta_keepalive_cmd {
__le32 vdev_id;
__le32 enabled;
__le32 method;
__le32 interval;
struct wmi_sta_keepalive_arp_resp arp_resp;
} __packed;
struct wmi_sta_keepalive_arg {
u32 vdev_id;
u32 enabled;
u32 method;
u32 interval;
__be32 src_ip4_addr;
__be32 dest_ip4_addr;
const u8 dest_mac_addr[ETH_ALEN];
};
enum wmi_force_fw_hang_type {
WMI_FORCE_FW_HANG_ASSERT = 1,
WMI_FORCE_FW_HANG_NO_DETECT,
WMI_FORCE_FW_HANG_CTRL_EP_FULL,
WMI_FORCE_FW_HANG_EMPTY_POINT,
WMI_FORCE_FW_HANG_STACK_OVERFLOW,
WMI_FORCE_FW_HANG_INFINITE_LOOP,
};
#define WMI_FORCE_FW_HANG_RANDOM_TIME 0xFFFFFFFF
struct wmi_force_fw_hang_cmd {
__le32 type;
__le32 delay_ms;
} __packed;
enum wmi_pdev_reset_mode_type {
WMI_RST_MODE_TX_FLUSH = 1,
WMI_RST_MODE_WARM_RESET,
WMI_RST_MODE_COLD_RESET,
WMI_RST_MODE_WARM_RESET_RESTORE_CAL,
WMI_RST_MODE_COLD_RESET_RESTORE_CAL,
WMI_RST_MODE_MAX,
};
enum ath10k_dbglog_level {
ATH10K_DBGLOG_LEVEL_VERBOSE = 0,
ATH10K_DBGLOG_LEVEL_INFO = 1,
ATH10K_DBGLOG_LEVEL_WARN = 2,
ATH10K_DBGLOG_LEVEL_ERR = 3,
};
#define ATH10K_DBGLOG_CFG_VAP_LOG_LSB 0
#define ATH10K_DBGLOG_CFG_VAP_LOG_MASK 0x0000ffff
#define ATH10K_DBGLOG_CFG_REPORTING_ENABLE_LSB 16
#define ATH10K_DBGLOG_CFG_REPORTING_ENABLE_MASK 0x00010000
#define ATH10K_DBGLOG_CFG_RESOLUTION_LSB 17
#define ATH10K_DBGLOG_CFG_RESOLUTION_MASK 0x000E0000
#define ATH10K_DBGLOG_CFG_REPORT_SIZE_LSB 20
#define ATH10K_DBGLOG_CFG_REPORT_SIZE_MASK 0x0ff00000
#define ATH10K_DBGLOG_CFG_LOG_LVL_LSB 28
#define ATH10K_DBGLOG_CFG_LOG_LVL_MASK 0x70000000
struct wmi_dbglog_cfg_cmd {
__le32 module_enable;
__le32 config_enable;
__le32 module_valid;
__le32 config_valid;
} __packed;
struct wmi_10_4_dbglog_cfg_cmd {
__le64 module_enable;
__le32 config_enable;
__le64 module_valid;
__le32 config_valid;
} __packed;
enum wmi_roam_reason {
WMI_ROAM_REASON_BETTER_AP = 1,
WMI_ROAM_REASON_BEACON_MISS = 2,
WMI_ROAM_REASON_LOW_RSSI = 3,
WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4,
WMI_ROAM_REASON_HO_FAILED = 5,
WMI_ROAM_REASON_MAX,
};
struct wmi_roam_ev {
__le32 vdev_id;
__le32 reason;
} __packed;
#define ATH10K_FRAGMT_THRESHOLD_MIN 540
#define ATH10K_FRAGMT_THRESHOLD_MAX 2346
#define WMI_MAX_EVENT 0x1000
#define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr)
#define ATH10K_DEFAULT_ATIM 0
#define WMI_MAX_MEM_REQS 16
struct wmi_scan_ev_arg {
__le32 event_type;
__le32 reason;
__le32 channel_freq;
__le32 scan_req_id;
__le32 scan_id;
__le32 vdev_id;
};
struct mgmt_tx_compl_params {
u32 desc_id;
u32 status;
u32 ppdu_id;
int ack_rssi;
};
struct wmi_tlv_mgmt_tx_compl_ev_arg {
__le32 desc_id;
__le32 status;
__le32 pdev_id;
__le32 ppdu_id;
__le32 ack_rssi;
};
struct wmi_tlv_mgmt_tx_bundle_compl_ev_arg {
__le32 num_reports;
const __le32 *desc_ids;
const __le32 *status;
const __le32 *ppdu_ids;
const __le32 *ack_rssi;
};
struct wmi_peer_delete_resp_ev_arg {
__le32 vdev_id;
struct wmi_mac_addr peer_addr;
};
#define WMI_MGMT_RX_NUM_RSSI 4
struct wmi_mgmt_rx_ev_arg {
__le32 channel;
__le32 snr;
__le32 rate;
__le32 phy_mode;
__le32 buf_len;
__le32 status;
struct wmi_mgmt_rx_ext_info ext_info;
__le32 rssi[WMI_MGMT_RX_NUM_RSSI];
};
struct wmi_ch_info_ev_arg {
__le32 err_code;
__le32 freq;
__le32 cmd_flags;
__le32 noise_floor;
__le32 rx_clear_count;
__le32 cycle_count;
__le32 chan_tx_pwr_range;
__le32 chan_tx_pwr_tp;
__le32 rx_frame_count;
__le32 my_bss_rx_cycle_count;
__le32 rx_11b_mode_data_duration;
__le32 tx_frame_cnt;
__le32 mac_clk_mhz;
};
enum wmi_vdev_start_status {
WMI_VDEV_START_OK = 0,
WMI_VDEV_START_CHAN_INVALID,
};
struct wmi_vdev_start_ev_arg {
__le32 vdev_id;
__le32 req_id;
__le32 resp_type;
__le32 status;
};
struct wmi_peer_kick_ev_arg {
const u8 *mac_addr;
};
struct wmi_swba_ev_arg {
__le32 vdev_map;
struct wmi_tim_info_arg tim_info[WMI_MAX_AP_VDEV];
const struct wmi_p2p_noa_info *noa_info[WMI_MAX_AP_VDEV];
};
struct wmi_phyerr_ev_arg {
u32 tsf_timestamp;
u16 freq1;
u16 freq2;
u8 rssi_combined;
u8 chan_width_mhz;
u8 phy_err_code;
u16 nf_chains[4];
u32 buf_len;
const u8 *buf;
u8 hdr_len;
};
struct wmi_phyerr_hdr_arg {
u32 num_phyerrs;
u32 tsf_l32;
u32 tsf_u32;
u32 buf_len;
const void *phyerrs;
};
struct wmi_dfs_status_ev_arg {
u32 status;
};
struct wmi_svc_rdy_ev_arg {
__le32 min_tx_power;
__le32 max_tx_power;
__le32 ht_cap;
__le32 vht_cap;
__le32 vht_supp_mcs;
__le32 sw_ver0;
__le32 sw_ver1;
__le32 fw_build;
__le32 phy_capab;
__le32 num_rf_chains;
__le32 eeprom_rd;
__le32 num_mem_reqs;
__le32 low_2ghz_chan;
__le32 high_2ghz_chan;
__le32 low_5ghz_chan;
__le32 high_5ghz_chan;
__le32 sys_cap_info;
const __le32 *service_map;
size_t service_map_len;
const struct wlan_host_mem_req *mem_reqs[WMI_MAX_MEM_REQS];
};
struct wmi_svc_avail_ev_arg {
bool service_map_ext_valid;
__le32 service_map_ext_len;
const __le32 *service_map_ext;
};
struct wmi_rdy_ev_arg {
__le32 sw_version;
__le32 abi_version;
__le32 status;
const u8 *mac_addr;
};
struct wmi_roam_ev_arg {
__le32 vdev_id;
__le32 reason;
__le32 rssi;
};
struct wmi_echo_ev_arg {
__le32 value;
};
struct wmi_pdev_temperature_event {
__le32 temperature;
} __packed;
struct wmi_pdev_bss_chan_info_event {
__le32 freq;
__le32 noise_floor;
__le64 cycle_busy;
__le64 cycle_total;
__le64 cycle_tx;
__le64 cycle_rx;
__le64 cycle_rx_bss;
__le32 reserved;
} __packed;
enum wmi_wow_wakeup_event {
WOW_BMISS_EVENT = 0,
WOW_BETTER_AP_EVENT,
WOW_DEAUTH_RECVD_EVENT,
WOW_MAGIC_PKT_RECVD_EVENT,
WOW_GTK_ERR_EVENT,
WOW_FOURWAY_HSHAKE_EVENT,
WOW_EAPOL_RECVD_EVENT,
WOW_NLO_DETECTED_EVENT,
WOW_DISASSOC_RECVD_EVENT,
WOW_PATTERN_MATCH_EVENT,
WOW_CSA_IE_EVENT,
WOW_PROBE_REQ_WPS_IE_EVENT,
WOW_AUTH_REQ_EVENT,
WOW_ASSOC_REQ_EVENT,
WOW_HTT_EVENT,
WOW_RA_MATCH_EVENT,
WOW_HOST_AUTO_SHUTDOWN_EVENT,
WOW_IOAC_MAGIC_EVENT,
WOW_IOAC_SHORT_EVENT,
WOW_IOAC_EXTEND_EVENT,
WOW_IOAC_TIMER_EVENT,
WOW_DFS_PHYERR_RADAR_EVENT,
WOW_BEACON_EVENT,
WOW_CLIENT_KICKOUT_EVENT,
WOW_EVENT_MAX,
};
#define C2S(x) case x: return #x
static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev)
{
switch (ev) {
C2S(WOW_BMISS_EVENT);
C2S(WOW_BETTER_AP_EVENT);
C2S(WOW_DEAUTH_RECVD_EVENT);
C2S(WOW_MAGIC_PKT_RECVD_EVENT);
C2S(WOW_GTK_ERR_EVENT);
C2S(WOW_FOURWAY_HSHAKE_EVENT);
C2S(WOW_EAPOL_RECVD_EVENT);
C2S(WOW_NLO_DETECTED_EVENT);
C2S(WOW_DISASSOC_RECVD_EVENT);
C2S(WOW_PATTERN_MATCH_EVENT);
C2S(WOW_CSA_IE_EVENT);
C2S(WOW_PROBE_REQ_WPS_IE_EVENT);
C2S(WOW_AUTH_REQ_EVENT);
C2S(WOW_ASSOC_REQ_EVENT);
C2S(WOW_HTT_EVENT);
C2S(WOW_RA_MATCH_EVENT);
C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT);
C2S(WOW_IOAC_MAGIC_EVENT);
C2S(WOW_IOAC_SHORT_EVENT);
C2S(WOW_IOAC_EXTEND_EVENT);
C2S(WOW_IOAC_TIMER_EVENT);
C2S(WOW_DFS_PHYERR_RADAR_EVENT);
C2S(WOW_BEACON_EVENT);
C2S(WOW_CLIENT_KICKOUT_EVENT);
C2S(WOW_EVENT_MAX);
default:
return NULL;
}
}
enum wmi_wow_wake_reason {
WOW_REASON_UNSPECIFIED = -1,
WOW_REASON_NLOD = 0,
WOW_REASON_AP_ASSOC_LOST,
WOW_REASON_LOW_RSSI,
WOW_REASON_DEAUTH_RECVD,
WOW_REASON_DISASSOC_RECVD,
WOW_REASON_GTK_HS_ERR,
WOW_REASON_EAP_REQ,
WOW_REASON_FOURWAY_HS_RECV,
WOW_REASON_TIMER_INTR_RECV,
WOW_REASON_PATTERN_MATCH_FOUND,
WOW_REASON_RECV_MAGIC_PATTERN,
WOW_REASON_P2P_DISC,
WOW_REASON_WLAN_HB,
WOW_REASON_CSA_EVENT,
WOW_REASON_PROBE_REQ_WPS_IE_RECV,
WOW_REASON_AUTH_REQ_RECV,
WOW_REASON_ASSOC_REQ_RECV,
WOW_REASON_HTT_EVENT,
WOW_REASON_RA_MATCH,
WOW_REASON_HOST_AUTO_SHUTDOWN,
WOW_REASON_IOAC_MAGIC_EVENT,
WOW_REASON_IOAC_SHORT_EVENT,
WOW_REASON_IOAC_EXTEND_EVENT,
WOW_REASON_IOAC_TIMER_EVENT,
WOW_REASON_ROAM_HO,
WOW_REASON_DFS_PHYERR_RADADR_EVENT,
WOW_REASON_BEACON_RECV,
WOW_REASON_CLIENT_KICKOUT_EVENT,
WOW_REASON_DEBUG_TEST = 0xFF,
};
static inline const char *wow_reason(enum wmi_wow_wake_reason reason)
{
switch (reason) {
C2S(WOW_REASON_UNSPECIFIED);
C2S(WOW_REASON_NLOD);
C2S(WOW_REASON_AP_ASSOC_LOST);
C2S(WOW_REASON_LOW_RSSI);
C2S(WOW_REASON_DEAUTH_RECVD);
C2S(WOW_REASON_DISASSOC_RECVD);
C2S(WOW_REASON_GTK_HS_ERR);
C2S(WOW_REASON_EAP_REQ);
C2S(WOW_REASON_FOURWAY_HS_RECV);
C2S(WOW_REASON_TIMER_INTR_RECV);
C2S(WOW_REASON_PATTERN_MATCH_FOUND);
C2S(WOW_REASON_RECV_MAGIC_PATTERN);
C2S(WOW_REASON_P2P_DISC);
C2S(WOW_REASON_WLAN_HB);
C2S(WOW_REASON_CSA_EVENT);
C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV);
C2S(WOW_REASON_AUTH_REQ_RECV);
C2S(WOW_REASON_ASSOC_REQ_RECV);
C2S(WOW_REASON_HTT_EVENT);
C2S(WOW_REASON_RA_MATCH);
C2S(WOW_REASON_HOST_AUTO_SHUTDOWN);
C2S(WOW_REASON_IOAC_MAGIC_EVENT);
C2S(WOW_REASON_IOAC_SHORT_EVENT);
C2S(WOW_REASON_IOAC_EXTEND_EVENT);
C2S(WOW_REASON_IOAC_TIMER_EVENT);
C2S(WOW_REASON_ROAM_HO);
C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT);
C2S(WOW_REASON_BEACON_RECV);
C2S(WOW_REASON_CLIENT_KICKOUT_EVENT);
C2S(WOW_REASON_DEBUG_TEST);
default:
return NULL;
}
}
#undef C2S
struct wmi_wow_ev_arg {
u32 vdev_id;
u32 flag;
enum wmi_wow_wake_reason wake_reason;
u32 data_len;
};
#define WOW_MIN_PATTERN_SIZE 1
#define WOW_MAX_PATTERN_SIZE 148
#define WOW_MAX_PKT_OFFSET 128
#define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \
sizeof(struct rfc1042_hdr))
#define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \
offsetof(struct ieee80211_hdr_3addr, addr1))
enum wmi_tdls_state {
WMI_TDLS_DISABLE,
WMI_TDLS_ENABLE_PASSIVE,
WMI_TDLS_ENABLE_ACTIVE,
WMI_TDLS_ENABLE_ACTIVE_EXTERNAL_CONTROL,
};
enum wmi_tdls_peer_state {
WMI_TDLS_PEER_STATE_PEERING,
WMI_TDLS_PEER_STATE_CONNECTED,
WMI_TDLS_PEER_STATE_TEARDOWN,
};
struct wmi_tdls_peer_update_cmd_arg {
u32 vdev_id;
enum wmi_tdls_peer_state peer_state;
u8 addr[ETH_ALEN];
};
#define WMI_TDLS_MAX_SUPP_OPER_CLASSES 32
#define WMI_TDLS_PEER_SP_MASK 0x60
#define WMI_TDLS_PEER_SP_LSB 5
enum wmi_tdls_options {
WMI_TDLS_OFFCHAN_EN = BIT(0),
WMI_TDLS_BUFFER_STA_EN = BIT(1),
WMI_TDLS_SLEEP_STA_EN = BIT(2),
};
enum {
WMI_TDLS_PEER_QOS_AC_VO = BIT(0),
WMI_TDLS_PEER_QOS_AC_VI = BIT(1),
WMI_TDLS_PEER_QOS_AC_BK = BIT(2),
WMI_TDLS_PEER_QOS_AC_BE = BIT(3),
};
struct wmi_tdls_peer_capab_arg {
u8 peer_uapsd_queues;
u8 peer_max_sp;
u32 buff_sta_support;
u32 off_chan_support;
u32 peer_curr_operclass;
u32 self_curr_operclass;
u32 peer_chan_len;
u32 peer_operclass_len;
u8 peer_operclass[WMI_TDLS_MAX_SUPP_OPER_CLASSES];
u32 is_peer_responder;
u32 pref_offchan_num;
u32 pref_offchan_bw;
};
struct wmi_10_4_tdls_set_state_cmd {
__le32 vdev_id;
__le32 state;
__le32 notification_interval_ms;
__le32 tx_discovery_threshold;
__le32 tx_teardown_threshold;
__le32 rssi_teardown_threshold;
__le32 rssi_delta;
__le32 tdls_options;
__le32 tdls_peer_traffic_ind_window;
__le32 tdls_peer_traffic_response_timeout_ms;
__le32 tdls_puapsd_mask;
__le32 tdls_puapsd_inactivity_time_ms;
__le32 tdls_puapsd_rx_frame_threshold;
__le32 teardown_notification_ms;
__le32 tdls_peer_kickout_threshold;
} __packed;
struct wmi_tdls_peer_capabilities {
__le32 peer_qos;
__le32 buff_sta_support;
__le32 off_chan_support;
__le32 peer_curr_operclass;
__le32 self_curr_operclass;
__le32 peer_chan_len;
__le32 peer_operclass_len;
u8 peer_operclass[WMI_TDLS_MAX_SUPP_OPER_CLASSES];
__le32 is_peer_responder;
__le32 pref_offchan_num;
__le32 pref_offchan_bw;
union {
struct wmi_channel peer_chan_min_allocation;
DECLARE_FLEX_ARRAY(struct wmi_channel, peer_chan_list);
};
} __packed;
struct wmi_10_4_tdls_peer_update_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 peer_state;
__le32 reserved[4];
struct wmi_tdls_peer_capabilities peer_capab;
} __packed;
enum wmi_tdls_peer_reason {
WMI_TDLS_TEARDOWN_REASON_TX,
WMI_TDLS_TEARDOWN_REASON_RSSI,
WMI_TDLS_TEARDOWN_REASON_SCAN,
WMI_TDLS_DISCONNECTED_REASON_PEER_DELETE,
WMI_TDLS_TEARDOWN_REASON_PTR_TIMEOUT,
WMI_TDLS_TEARDOWN_REASON_BAD_PTR,
WMI_TDLS_TEARDOWN_REASON_NO_RESPONSE,
WMI_TDLS_ENTER_BUF_STA,
WMI_TDLS_EXIT_BUF_STA,
WMI_TDLS_ENTER_BT_BUSY_MODE,
WMI_TDLS_EXIT_BT_BUSY_MODE,
WMI_TDLS_SCAN_STARTED_EVENT,
WMI_TDLS_SCAN_COMPLETED_EVENT,
};
enum wmi_tdls_peer_notification {
WMI_TDLS_SHOULD_DISCOVER,
WMI_TDLS_SHOULD_TEARDOWN,
WMI_TDLS_PEER_DISCONNECTED,
WMI_TDLS_CONNECTION_TRACKER_NOTIFICATION,
};
struct wmi_tdls_peer_event {
struct wmi_mac_addr peer_macaddr;
__le32 peer_status;
__le32 peer_reason;
__le32 vdev_id;
} __packed;
enum wmi_tid_aggr_control_conf {
WMI_TID_CONFIG_AGGR_CONTROL_IGNORE,
WMI_TID_CONFIG_AGGR_CONTROL_ENABLE,
WMI_TID_CONFIG_AGGR_CONTROL_DISABLE,
};
enum wmi_noack_tid_conf {
WMI_NOACK_TID_CONFIG_IGNORE_ACK_POLICY,
WMI_PEER_TID_CONFIG_ACK,
WMI_PEER_TID_CONFIG_NOACK,
};
enum wmi_tid_rate_ctrl_conf {
WMI_TID_CONFIG_RATE_CONTROL_IGNORE,
WMI_TID_CONFIG_RATE_CONTROL_AUTO,
WMI_TID_CONFIG_RATE_CONTROL_FIXED_RATE,
WMI_TID_CONFIG_RATE_CONTROL_DEFAULT_LOWEST_RATE,
WMI_PEER_TID_CONFIG_RATE_UPPER_CAP,
};
enum wmi_tid_rtscts_control_conf {
WMI_TID_CONFIG_RTSCTS_CONTROL_ENABLE,
WMI_TID_CONFIG_RTSCTS_CONTROL_DISABLE,
};
enum wmi_ext_tid_config_map {
WMI_EXT_TID_RTS_CTS_CONFIG = BIT(0),
};
struct wmi_per_peer_per_tid_cfg_arg {
u32 vdev_id;
struct wmi_mac_addr peer_macaddr;
u32 tid;
enum wmi_noack_tid_conf ack_policy;
enum wmi_tid_aggr_control_conf aggr_control;
u8 rate_ctrl;
u32 retry_count;
u32 rcode_flags;
u32 ext_tid_cfg_bitmap;
u32 rtscts_ctrl;
};
struct wmi_peer_per_tid_cfg_cmd {
__le32 vdev_id;
struct wmi_mac_addr peer_macaddr;
__le32 tid;
__le32 ack_policy;
__le32 aggr_control;
__le32 rate_control;
__le32 rcode_flags;
__le32 retry_count;
__le32 ext_tid_cfg_bitmap;
__le32 rtscts_ctrl;
} __packed;
enum wmi_txbf_conf {
WMI_TXBF_CONF_UNSUPPORTED,
WMI_TXBF_CONF_BEFORE_ASSOC,
WMI_TXBF_CONF_AFTER_ASSOC,
};
#define WMI_CCA_DETECT_LEVEL_AUTO 0
#define WMI_CCA_DETECT_MARGIN_AUTO 0
struct wmi_pdev_set_adaptive_cca_params {
__le32 enable;
__le32 cca_detect_level;
__le32 cca_detect_margin;
} __packed;
#define WMI_PNO_MAX_SCHED_SCAN_PLANS 2
#define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200
#define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100
#define WMI_PNO_MAX_NETW_CHANNELS 26
#define WMI_PNO_MAX_NETW_CHANNELS_EX 60
#define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID
#define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN
#define WMI_PNO_MAX_PB_REQ_SIZE 450
#define WMI_PNO_24G_DEFAULT_CH 1
#define WMI_PNO_5G_DEFAULT_CH 36
#define WMI_ACTIVE_MAX_CHANNEL_TIME 40
#define WMI_PASSIVE_MAX_CHANNEL_TIME 110
enum wmi_SSID_bcast_type {
BCAST_UNKNOWN = 0,
BCAST_NORMAL = 1,
BCAST_HIDDEN = 2,
};
struct wmi_network_type {
struct wmi_ssid ssid;
u32 authentication;
u32 encryption;
u32 bcast_nw_type;
u8 channel_count;
u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX];
s32 rssi_threshold;
} __packed;
struct wmi_pno_scan_req {
u8 enable;
u8 vdev_id;
u8 uc_networks_count;
struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS];
u32 fast_scan_period;
u32 slow_scan_period;
u8 fast_scan_max_cycles;
bool do_passive_scan;
u32 delay_start_time;
u32 active_min_time;
u32 active_max_time;
u32 passive_min_time;
u32 passive_max_time;
u32 enable_pno_scan_randomization;
u8 mac_addr[ETH_ALEN];
u8 mac_addr_mask[ETH_ALEN];
} __packed;
enum wmi_host_platform_type {
WMI_HOST_PLATFORM_HIGH_PERF,
WMI_HOST_PLATFORM_LOW_PERF,
};
enum wmi_bss_survey_req_type {
WMI_BSS_SURVEY_REQ_TYPE_READ = 1,
WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR,
};
struct wmi_pdev_chan_info_req_cmd {
__le32 type;
__le32 reserved;
} __packed;
struct wmi_bb_timing_cfg_arg {
u32 bb_tx_timing;
u32 bb_xpa_timing;
};
struct wmi_pdev_bb_timing_cfg_cmd {
__le32 bb_tx_timing;
__le32 bb_xpa_timing;
} __packed;
struct wmi_ftm_seg_hdr {
__le32 len;
__le32 msgref;
__le32 segmentinfo;
__le32 pdev_id;
} __packed;
struct wmi_ftm_cmd {
__le32 tlv_header;
struct wmi_ftm_seg_hdr seg_hdr;
u8 data[];
} __packed;
#define WMI_TLV_LEN GENMASK(15, 0)
#define WMI_TLV_TAG GENMASK(31, 16)
#define MAX_WMI_UTF_LEN 252
struct ath10k;
struct ath10k_vif;
struct ath10k_fw_stats_pdev;
struct ath10k_fw_stats_peer;
struct ath10k_fw_stats;
int ath10k_wmi_attach(struct ath10k *ar);
void ath10k_wmi_detach(struct ath10k *ar);
void ath10k_wmi_free_host_mem(struct ath10k *ar);
int ath10k_wmi_wait_for_service_ready(struct ath10k *ar);
int ath10k_wmi_wait_for_unified_ready(struct ath10k *ar);
struct sk_buff *ath10k_wmi_alloc_skb(struct ath10k *ar, u32 len);
int ath10k_wmi_connect(struct ath10k *ar);
int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id);
int ath10k_wmi_cmd_send_nowait(struct ath10k *ar, struct sk_buff *skb,
u32 cmd_id);
void ath10k_wmi_start_scan_init(struct ath10k *ar, struct wmi_start_scan_arg *arg);
void ath10k_wmi_pull_pdev_stats_base(const struct wmi_pdev_stats_base *src,
struct ath10k_fw_stats_pdev *dst);
void ath10k_wmi_pull_pdev_stats_tx(const struct wmi_pdev_stats_tx *src,
struct ath10k_fw_stats_pdev *dst);
void ath10k_wmi_pull_pdev_stats_rx(const struct wmi_pdev_stats_rx *src,
struct ath10k_fw_stats_pdev *dst);
void ath10k_wmi_pull_pdev_stats_extra(const struct wmi_pdev_stats_extra *src,
struct ath10k_fw_stats_pdev *dst);
void ath10k_wmi_pull_peer_stats(const struct wmi_peer_stats *src,
struct ath10k_fw_stats_peer *dst);
void ath10k_wmi_put_host_mem_chunks(struct ath10k *ar,
struct wmi_host_mem_chunks *chunks);
void ath10k_wmi_put_start_scan_common(struct wmi_start_scan_common *cmn,
const struct wmi_start_scan_arg *arg);
void ath10k_wmi_set_wmm_param(struct wmi_wmm_params *params,
const struct wmi_wmm_params_arg *arg);
void ath10k_wmi_put_wmi_channel(struct ath10k *ar, struct wmi_channel *ch,
const struct wmi_channel_arg *arg);
int ath10k_wmi_start_scan_verify(const struct wmi_start_scan_arg *arg);
int ath10k_wmi_event_scan(struct ath10k *ar, struct sk_buff *skb);
int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb);
int ath10k_wmi_event_mgmt_tx_compl(struct ath10k *ar, struct sk_buff *skb);
int ath10k_wmi_event_mgmt_tx_bundle_compl(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_chan_info(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_echo(struct ath10k *ar, struct sk_buff *skb);
int ath10k_wmi_event_debug_mesg(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_update_stats(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_vdev_start_resp(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_vdev_stopped(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_peer_sta_kickout(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_host_swba(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_tbttoffset_update(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_dfs(struct ath10k *ar,
struct wmi_phyerr_ev_arg *phyerr, u64 tsf);
void ath10k_wmi_event_spectral_scan(struct ath10k *ar,
struct wmi_phyerr_ev_arg *phyerr,
u64 tsf);
void ath10k_wmi_event_phyerr(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_roam(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_profile_match(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_debug_print(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_pdev_qvit(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_wlan_profile_data(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_rtt_measurement_report(struct ath10k *ar,
struct sk_buff *skb);
void ath10k_wmi_event_tsf_measurement_report(struct ath10k *ar,
struct sk_buff *skb);
void ath10k_wmi_event_rtt_error_report(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_wow_wakeup_host(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_dcs_interference(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_pdev_tpc_config(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_pdev_ftm_intg(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_gtk_offload_status(struct ath10k *ar,
struct sk_buff *skb);
void ath10k_wmi_event_gtk_rekey_fail(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_delba_complete(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_addba_complete(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_vdev_install_key_complete(struct ath10k *ar,
struct sk_buff *skb);
void ath10k_wmi_event_inst_rssi_stats(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_vdev_standby_req(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_vdev_resume_req(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_service_ready(struct ath10k *ar, struct sk_buff *skb);
int ath10k_wmi_event_ready(struct ath10k *ar, struct sk_buff *skb);
void ath10k_wmi_event_service_available(struct ath10k *ar, struct sk_buff *skb);
int ath10k_wmi_op_pull_phyerr_ev(struct ath10k *ar, const void *phyerr_buf,
int left_len, struct wmi_phyerr_ev_arg *arg);
void ath10k_wmi_main_op_fw_stats_fill(struct ath10k *ar,
struct ath10k_fw_stats *fw_stats,
char *buf);
void ath10k_wmi_10x_op_fw_stats_fill(struct ath10k *ar,
struct ath10k_fw_stats *fw_stats,
char *buf);
void ath10k_wmi_10_4_op_fw_stats_fill(struct ath10k *ar,
struct ath10k_fw_stats *fw_stats,
char *buf);
int ath10k_wmi_op_get_vdev_subtype(struct ath10k *ar,
enum wmi_vdev_subtype subtype);
int ath10k_wmi_barrier(struct ath10k *ar);
void ath10k_wmi_tpc_config_get_rate_code(u8 *rate_code, u16 *pream_table,
u32 num_tx_chain);
void ath10k_wmi_event_tpc_final_table(struct ath10k *ar, struct sk_buff *skb);
#endif
