drivers/accel/ethosu/ethosu_gem.c

208

int tile = 0;

drivers/accel/ethosu/ethosu_gem.c

221

tile += 1;

drivers/accel/ethosu/ethosu_gem.c

223

if (y >= fm->height[tile] + 1) {

drivers/accel/ethosu/ethosu_gem.c

224

y -= fm->height[tile] + 1;

drivers/accel/ethosu/ethosu_gem.c

225

tile += 2;

drivers/accel/ethosu/ethosu_gem.c

231

tile = 2;

drivers/accel/ethosu/ethosu_gem.c

234

tile = 1;

drivers/accel/ethosu/ethosu_gem.c

240

if (fm->base[tile] == U64_MAX)

drivers/accel/ethosu/ethosu_gem.c

243

addr = fm->base[tile] + y * fm->stride_y;

drivers/accel/ivpu/ivpu_hw_btrs.c

44

#define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio))

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1000

uint32_t *tile, *macrotile;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1002

tile = adev->gfx.config.tile_mode_array;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1019

tile[reg_offset] = 0;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1025

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1029

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1033

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1037

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1041

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1045

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1048

tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1052

tile[7] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1053

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1055

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1058

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1062

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1066

tile[12] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1067

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1070

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1074

tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1078

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1082

tile[17] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1083

tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1087

tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1090

tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1094

tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1098

tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1102

tile[23] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1103

tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1107

tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1111

tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1115

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1118

tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1122

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1126

tile[30] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1186

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1192

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1196

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1200

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1204

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1208

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1212

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1216

tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1220

tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1224

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1226

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1229

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1233

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1237

tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1241

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1244

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1248

tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1252

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1256

tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1260

tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1264

tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1267

tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1271

tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1275

tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1279

tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1283

tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1287

tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1291

tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1295

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1298

tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1302

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1306

tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1369

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1378

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1382

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1386

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1390

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1394

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1398

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1401

tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1405

tile[7] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1406

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1408

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1411

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1415

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1419

tile[12] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1420

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1423

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1427

tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1431

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1435

tile[17] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1436

tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1440

tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1443

tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1447

tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1451

tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1455

tile[23] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1456

tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1460

tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1464

tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1468

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1471

tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1475

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1479

tile[30] = (TILE_SPLIT(split_equal_to_row_size));

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1539

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

242

#define ISP_TILE_SEL(tile) (1<<tile)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

248

#define ISP_TILE_SEL(tile) (1<<tile)

drivers/gpu/drm/drm_connector.c

2776

char tile[256];

drivers/gpu/drm/drm_connector.c

2789

snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d",

drivers/gpu/drm/drm_connector.c

2797

strlen(tile) + 1,

drivers/gpu/drm/drm_connector.c

2798

tile,

drivers/gpu/drm/drm_edid.c

7572

const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;

drivers/gpu/drm/drm_edid.c

7586

w = tile->tile_size[0] | tile->tile_size[1] << 8;

drivers/gpu/drm/drm_edid.c

7587

h = tile->tile_size[2] | tile->tile_size[3] << 8;

drivers/gpu/drm/drm_edid.c

7589

num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);

drivers/gpu/drm/drm_edid.c

7590

num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);

drivers/gpu/drm/drm_edid.c

7591

tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);

drivers/gpu/drm/drm_edid.c

7592

tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);

drivers/gpu/drm/drm_edid.c

7595

if (tile->tile_cap & 0x80)

drivers/gpu/drm/drm_edid.c

7608

tile->tile_cap,

drivers/gpu/drm/drm_edid.c

7612

tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);

drivers/gpu/drm/drm_edid.c

7614

tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);

drivers/gpu/drm/drm_edid.c

7616

tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);

drivers/gpu/drm/exynos/exynos_drm_scaler.c

144

u32 src_fmt, u32 tile)

drivers/gpu/drm/exynos/exynos_drm_scaler.c

148

val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);

drivers/gpu/drm/i915/display/intel_fb.c

1816

unsigned int stride, tile;

drivers/gpu/drm/i915/display/intel_fb.c

1825

tile = intel_tile_height(fb, color_plane);

drivers/gpu/drm/i915/display/intel_fb.c

1827

tile = intel_tile_width_bytes(fb, color_plane);

drivers/gpu/drm/i915/display/intel_fb.c

1829

vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile));

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

110

err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

113

tile->tiling, tile->stride, err);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

117

GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

118

GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

153

offset = tiled_offset(tile, page << PAGE_SHIFT);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

168

tile->tiling ? tile_row_pages(obj) : 0,

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

169

vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

188

const struct tile *tile,

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

198

err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

201

tile->tiling, tile->stride, err);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

205

GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

206

GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

249

offset = tiled_offset(tile, page << PAGE_SHIFT);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

264

tile->tiling ? tile_row_pages(obj) : 0,

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

265

vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

284

__func__, tile->tiling, tile->stride))

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

292

setup_tile_size(struct tile *tile, struct drm_i915_private *i915)

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

295

tile->height = 16;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

296

tile->width = 128;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

297

tile->size = 11;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

298

} else if (tile->tiling == I915_TILING_Y &&

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

300

tile->height = 32;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

301

tile->width = 128;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

302

tile->size = 12;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

304

tile->height = 8;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

305

tile->width = 512;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

306

tile->size = 12;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

310

return 8192 / tile->width;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

312

return 128 * I965_FENCE_MAX_PITCH_VAL / tile->width;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

314

return 128 * GEN7_FENCE_MAX_PITCH_VAL / tile->width;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

354

struct tile tile;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

356

tile.height = 1;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

357

tile.width = 1;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

358

tile.size = 0;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

359

tile.stride = 0;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

360

tile.swizzle = I915_BIT_6_SWIZZLE_NONE;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

361

tile.tiling = I915_TILING_NONE;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

363

err = check_partial_mappings(obj, &tile, end);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

372

struct tile tile;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

382

tile.tiling = tiling;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

385

tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

388

tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

392

GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

393

if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

394

tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

397

max_pitch = setup_tile_size(&tile, i915);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

400

tile.stride = tile.width * pitch;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

401

err = check_partial_mappings(obj, &tile, end);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

408

tile.stride = tile.width * (pitch - 1);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

409

err = check_partial_mappings(obj, &tile, end);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

417

tile.stride = tile.width * (pitch + 1);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

418

err = check_partial_mappings(obj, &tile, end);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

428

tile.stride = tile.width * pitch;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

429

err = check_partial_mappings(obj, &tile, end);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

46

static u64 tiled_offset(const struct tile *tile, u64 v)

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

491

struct tile tile;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

493

tile.tiling =

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

495

switch (tile.tiling) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

497

tile.height = 1;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

498

tile.width = 1;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

499

tile.size = 0;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

50

if (tile->tiling == I915_TILING_NONE)

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

500

tile.stride = 0;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

501

tile.swizzle = I915_BIT_6_SWIZZLE_NONE;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

505

tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

508

tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

512

if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

513

tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

516

if (tile.tiling != I915_TILING_NONE) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

517

unsigned int max_pitch = setup_tile_size(&tile, i915);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

519

tile.stride =

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

521

tile.stride = (1 + tile.stride) * tile.width;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

523

tile.stride = rounddown_pow_of_two(tile.stride);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

526

err = check_partial_mapping(obj, &tile, &prng);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

53

y = div64_u64_rem(v, tile->stride, &x);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

54

v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

56

if (tile->tiling == I915_TILING_X) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

57

v += y * tile->width;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

58

v += div64_u64_rem(x, tile->width, &x) << tile->size;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

60

} else if (tile->width == 128) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

76

switch (tile->swizzle) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

95

const struct tile *tile,

drivers/gpu/drm/i915/gvt/cmd_parser.c

1402

u32 stride, tile;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1409

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

drivers/gpu/drm/i915/gvt/cmd_parser.c

1414

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1420

if (tile != info->tile_val)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

197

pix_in_64byte = pix_in_64byte_map[ch->pix_size][ch->tile];

drivers/gpu/drm/imx/dcss/dcss-dpr.c

466

ch->tile = TILE_LINEAR;

drivers/gpu/drm/imx/dcss/dcss-dpr.c

469

ch->tile = TILE_GPU_STANDARD;

drivers/gpu/drm/imx/dcss/dcss-dpr.c

472

ch->tile = TILE_GPU_SUPER;

drivers/gpu/drm/imx/dcss/dcss-dpr.c

481

ch->tile = TILE_LINEAR;

drivers/gpu/drm/imx/dcss/dcss-dpr.c

489

ch->mode_ctrl |= ((ch->tile << TILE_TYPE_POS) & TILE_TYPE_MASK);

drivers/gpu/drm/imx/dcss/dcss-dpr.c

98

enum dcss_tile_type tile;

drivers/gpu/drm/nouveau/include/nvkm/core/engine.h

27

void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *);

drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h

54

} tile;

drivers/gpu/drm/nouveau/nouveau_bo.c

100

spin_lock(&drm->tile.lock);

drivers/gpu/drm/nouveau/nouveau_bo.c

101

tile->fence = (struct nouveau_fence *)dma_fence_get(fence);

drivers/gpu/drm/nouveau/nouveau_bo.c

102

tile->used = false;

drivers/gpu/drm/nouveau/nouveau_bo.c

103

spin_unlock(&drm->tile.lock);

drivers/gpu/drm/nouveau/nouveau_bo.c

113

struct nouveau_drm_tile *tile, *found = NULL;

drivers/gpu/drm/nouveau/nouveau_bo.c

116

for (i = 0; i < fb->tile.regions; i++) {

drivers/gpu/drm/nouveau/nouveau_bo.c

117

tile = nv10_bo_get_tile_region(dev, i);

drivers/gpu/drm/nouveau/nouveau_bo.c

120

found = tile;

drivers/gpu/drm/nouveau/nouveau_bo.c

1222

nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);

drivers/gpu/drm/nouveau/nouveau_bo.c

123

} else if (tile && fb->tile.region[i].pitch) {

drivers/gpu/drm/nouveau/nouveau_bo.c

125

nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);

drivers/gpu/drm/nouveau/nouveau_bo.c

128

nv10_bo_put_tile_region(dev, tile, NULL);

drivers/gpu/drm/nouveau/nouveau_bo.c

145

nv10_bo_put_tile_region(dev, nvbo->tile, NULL);

drivers/gpu/drm/nouveau/nouveau_bo.c

60

int i = reg - drm->tile.reg;

drivers/gpu/drm/nouveau/nouveau_bo.c

62

struct nvkm_fb_tile *tile = &fb->tile.region[i];

drivers/gpu/drm/nouveau/nouveau_bo.c

66

if (tile->pitch)

drivers/gpu/drm/nouveau/nouveau_bo.c

67

nvkm_fb_tile_fini(fb, i, tile);

drivers/gpu/drm/nouveau/nouveau_bo.c

70

nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);

drivers/gpu/drm/nouveau/nouveau_bo.c

72

nvkm_fb_tile_prog(fb, i, tile);

drivers/gpu/drm/nouveau/nouveau_bo.c

79

struct nouveau_drm_tile *tile = &drm->tile.reg[i];

drivers/gpu/drm/nouveau/nouveau_bo.c

81

spin_lock(&drm->tile.lock);

drivers/gpu/drm/nouveau/nouveau_bo.c

83

if (!tile->used &&

drivers/gpu/drm/nouveau/nouveau_bo.c

84

(!tile->fence || nouveau_fence_done(tile->fence)))

drivers/gpu/drm/nouveau/nouveau_bo.c

85

tile->used = true;

drivers/gpu/drm/nouveau/nouveau_bo.c

87

tile = NULL;

drivers/gpu/drm/nouveau/nouveau_bo.c

89

spin_unlock(&drm->tile.lock);

drivers/gpu/drm/nouveau/nouveau_bo.c

90

return tile;

drivers/gpu/drm/nouveau/nouveau_bo.c

94

nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,

drivers/gpu/drm/nouveau/nouveau_bo.c

99

if (tile) {

drivers/gpu/drm/nouveau/nouveau_bo.h

48

struct nouveau_drm_tile *tile;

drivers/gpu/drm/nouveau/nouveau_drm.c

646

spin_lock_init(&drm->tile.lock);

drivers/gpu/drm/nouveau/nouveau_drv.h

283

} tile;

drivers/gpu/drm/nouveau/nvkm/core/engine.c

119

for (i = 0; fb && i < fb->tile.regions; i++)

drivers/gpu/drm/nouveau/nvkm/core/engine.c

77

if (engine->func->tile)

drivers/gpu/drm/nouveau/nvkm/core/engine.c

78

engine->func->tile(engine, region, &fb->tile.region[region]);

drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c

197

.tile = nvkm_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c

65

nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c

68

if (gr->func->tile)

drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c

69

gr->func->tile(gr, region, tile);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c

1102

data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c

207

data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c

127

data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1980

gr->tile[i++] = gpc_map[j];

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2058

memset(gr->tile, 0xff, sizeof(gr->tile));

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2298

data |= bank[gr->tile[i + j]] << (j * 4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2299

bank[gr->tile[i + j]]++;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

124

u8 tile[TPC_MAX];

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c

136

data |= bank[gr->tile[i + j]] << (j * 4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c

137

bank[gr->tile[i + j]]++;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

168

memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

172

memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

176

memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1049

nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1059

nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1060

nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1061

nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1192

.tile = nv10_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c

30

.tile = nv10_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c

30

.tile = nv10_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

149

nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

159

nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

160

nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

161

nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

164

nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

166

nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

168

nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

171

nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

173

nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

350

.tile = nv20_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c

109

.tile = nv20_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c

100

.tile = nv20_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c

171

.tile = nv20_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c

108

.tile = nv20_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c

108

.tile = nv20_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

173

nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

189

nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

190

nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

191

nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

192

nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

193

nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

194

nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

198

nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

199

nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

204

nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

205

nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

214

nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

215

nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

216

nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

217

nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

218

nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

219

nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

220

nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

221

nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

448

.tile = nv40_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

31

nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

44

nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

45

nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

46

nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

53

nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

54

nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

55

nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

56

nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

57

nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

58

nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

61

nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

62

nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

63

nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

64

nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

65

nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

66

nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

80

.tile = nv44_gr_tile,

drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h

23

void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *);

drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c

65

data |= bank[gr->tile[i + j]] << (j * 4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c

66

bank[gr->tile[i + j]]++;

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c

113

nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c

118

nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c

119

nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit);

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c

120

nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr);

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c

266

.tile = nv31_mpeg_tile,

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c

196

.tile = nv31_mpeg_tile,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

201

for (i = 0; i < fb->tile.regions; i++)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

202

fb->func->tile.prog(fb, i, &fb->tile.region[i]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

240

for (i = 0; i < fb->tile.regions; i++)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

241

fb->func->tile.fini(fb, i, &fb->tile.region[i]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

277

fb->tile.regions = fb->func->tile.regions;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

35

nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

37

fb->func->tile.fini(fb, region, tile);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

42

u32 pitch, u32 flags, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

44

fb->func->tile.init(fb, region, addr, size, pitch, flags, tile);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

48

nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

51

if (fb->func->tile.prog) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

52

fb->func->tile.prog(fb, region, tile);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

31

u32 flags, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

33

tile->addr = 0x80000000 | addr;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

34

tile->limit = max(1u, addr + size) - 1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

35

tile->pitch = pitch;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

39

nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

41

tile->addr = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

42

tile->limit = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

43

tile->pitch = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

44

tile->zcomp = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

48

nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

51

nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

52

nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

53

nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

59

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

60

.tile.init = nv10_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

61

.tile.fini = nv10_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

62

.tile.prog = nv10_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c

31

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c

32

.tile.init = nv10_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c

33

.tile.fini = nv10_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c

34

.tile.prog = nv10_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

31

u32 flags, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

33

tile->addr = 0x00000001 | addr;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

34

tile->limit = max(1u, addr + size) - 1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

35

tile->pitch = pitch;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

37

fb->func->tile.comp(fb, i, size, flags, tile);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

38

tile->addr |= 2;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

44

struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

48

if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

49

if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

50

else tile->zcomp = 0x04000000; /* Z24S8 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

51

tile->zcomp |= tile->tag->offset;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

52

tile->zcomp |= 0x80000000; /* enable */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

54

tile->zcomp |= 0x08000000;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

60

nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

62

tile->addr = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

63

tile->limit = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

64

tile->pitch = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

65

tile->zcomp = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

66

nvkm_mm_free(&fb->tags.mm, &tile->tag);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

70

nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

73

nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

74

nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

75

nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

77

nvkm_wr32(device, 0x100300 + (i * 0x04), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

90

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

91

.tile.init = nv20_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

92

.tile.comp = nv20_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

93

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

94

.tile.prog = nv20_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

31

struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

35

if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

36

if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

37

else tile->zcomp = 0x00200000; /* Z24S8 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

38

tile->zcomp |= tile->tag->offset;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

40

tile->zcomp |= 0x01000000;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

48

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

49

.tile.init = nv20_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

50

.tile.comp = nv25_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

51

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

52

.tile.prog = nv20_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

121

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

122

.tile.init = nv30_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

123

.tile.comp = nv30_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

124

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

125

.tile.prog = nv20_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

31

u32 flags, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

35

tile->addr = (0 << 4);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

37

if (fb->func->tile.comp) /* z compression */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

38

fb->func->tile.comp(fb, i, size, flags, tile);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

39

tile->addr = (1 << 4);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

42

tile->addr |= 0x00000001; /* enable */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

43

tile->addr |= addr;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

44

tile->limit = max(1u, addr + size) - 1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

45

tile->pitch = pitch;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

50

struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

54

if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

55

if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

56

else tile->zcomp |= 0x02000000; /* Z24S8 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

57

tile->zcomp |= ((tile->tag->offset ) >> 6);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

58

tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

60

tile->zcomp |= 0x10000000;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

31

struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

35

if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

36

if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

37

else tile->zcomp |= 0x08000000; /* Z24S8 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

38

tile->zcomp |= ((tile->tag->offset ) >> 6);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

39

tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

41

tile->zcomp |= 0x40000000;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

50

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

51

.tile.init = nv30_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

52

.tile.comp = nv35_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

53

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

54

.tile.prog = nv20_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

31

struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

35

if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

36

if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

37

else tile->zcomp |= 0x20000000; /* Z24S8 */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

38

tile->zcomp |= ((tile->tag->offset ) >> 6);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

39

tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

41

tile->zcomp |= 0x80000000;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

50

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

51

.tile.init = nv30_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

52

.tile.comp = nv36_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

53

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

54

.tile.prog = nv20_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

31

struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

36

!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

37

tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

38

tile->zcomp |= ((tile->tag->offset ) >> 8);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

39

tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

41

tile->zcomp |= 0x40000000;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

56

.tile.regions = 8,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

57

.tile.init = nv30_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

58

.tile.comp = nv40_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

59

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

60

.tile.prog = nv20_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

30

nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

33

nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

34

nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

35

nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

37

nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

50

.tile.regions = 12,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

51

.tile.init = nv30_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

52

.tile.comp = nv40_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

53

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

54

.tile.prog = nv41_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

31

u32 flags, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

33

tile->addr = 0x00000001; /* mode = vram */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

34

tile->addr |= addr;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

35

tile->limit = max(1u, addr + size) - 1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

36

tile->pitch = pitch;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

40

nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

43

nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

44

nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

45

nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

60

.tile.regions = 12,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

61

.tile.init = nv44_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

62

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

63

.tile.prog = nv44_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

31

u32 flags, struct nvkm_fb_tile *tile)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

34

if (!(flags & 4)) tile->addr = (0 << 3);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

35

else tile->addr = (1 << 3);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

37

tile->addr |= 0x00000001; /* mode = vram */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

38

tile->addr |= addr;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

39

tile->limit = max(1u, addr + size) - 1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

40

tile->pitch = pitch;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

46

.tile.regions = 15,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

47

.tile.init = nv46_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

48

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

49

.tile.prog = nv44_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c

33

.tile.regions = 15,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c

34

.tile.init = nv30_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c

35

.tile.comp = nv40_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c

36

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c

37

.tile.prog = nv41_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c

33

.tile.regions = 15,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c

34

.tile.init = nv30_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c

35

.tile.comp = nv40_fb_tile_comp,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c

36

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c

37

.tile.prog = nv41_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c

32

.tile.regions = 12,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c

33

.tile.init = nv46_fb_tile_init,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c

34

.tile.fini = nv20_fb_tile_fini,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c

35

.tile.prog = nv44_fb_tile_prog,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h

43

} tile;

drivers/gpu/drm/radeon/cik.c

2322

u32 *tile = rdev->config.cik.tile_mode_array;

drivers/gpu/drm/radeon/cik.c

2351

tile[reg_offset] = 0;

drivers/gpu/drm/radeon/cik.c

2357

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2361

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2365

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2369

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2373

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2377

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2380

tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2384

tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2388

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/radeon/cik.c

2390

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2393

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2397

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2401

tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2405

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2408

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2412

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2416

tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2420

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2423

tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2427

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2431

tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2494

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2500

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2504

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2508

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2512

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2516

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2520

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2523

tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2527

tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2531

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/radeon/cik.c

2533

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2536

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2540

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2544

tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2548

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2551

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2555

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2559

tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2563

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2566

tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2570

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2574

tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2637

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2644

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2648

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2652

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2656

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2660

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2664

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2667

tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2671

tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2675

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/radeon/cik.c

2677

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2680

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2684

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2688

tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2692

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2695

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2699

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2703

tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2707

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2710

tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2714

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2718

tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2724

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2728

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2732

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2736

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2740

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2744

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2747

tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2751

tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2755

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/radeon/cik.c

2757

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2760

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2764

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2768

tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2772

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2775

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2779

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2783

tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2787

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2790

tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2794

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2798

tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2862

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2868

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2872

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2876

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2880

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2884

tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2888

tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2891

tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2895

tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2899

tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/radeon/cik.c

2901

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2904

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2908

tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2912

tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2916

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2919

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2923

tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2927

tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2931

tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2934

tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2938

tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

2942

tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/cik.c

3005

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/si.c

2471

u32 *tile = rdev->config.si.tile_mode_array;

drivers/gpu/drm/radeon/si.c

2490

tile[reg_offset] = 0;

drivers/gpu/drm/radeon/si.c

2496

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2505

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2514

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2523

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2532

tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2541

tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2550

tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2559

tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2568

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/radeon/si.c

2577

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2586

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2595

tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2604

tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2613

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2622

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2631

tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2640

tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2649

tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2658

tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2667

tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2676

tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2685

tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2694

tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2704

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/si.c

2711

tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2720

tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2729

tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2738

tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2747

tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2756

tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2765

tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2774

tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2783

tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

drivers/gpu/drm/radeon/si.c

2792

tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2801

tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2810

tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2819

tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2828

tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2837

tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2846

tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2855

tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2864

tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2873

tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2882

tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2891

tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2900

tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2909

tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/si.c

2919

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/vc4/vc4_plane.c

1394

u32 tile_w, tile, x_off, pix_per_tile;

drivers/gpu/drm/vc4/vc4_plane.c

1432

tile = src_x / pix_per_tile;

drivers/gpu/drm/vc4/vc4_plane.c

1434

offsets[i] += param * tile_w * tile;

drivers/gpu/drm/vc4/vc4_plane.c

1857

u32 tile_w, tile, x_off, pix_per_tile;

drivers/gpu/drm/vc4/vc4_plane.c

1892

tile = src_x / pix_per_tile;

drivers/gpu/drm/vc4/vc4_plane.c

1894

offsets[i] += param * tile_w * tile;

drivers/gpu/drm/xe/display/xe_display_pcode.c

12

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/display/xe_display_pcode.c

14

return xe_pcode_read(tile, mbox, val, val1);

drivers/gpu/drm/xe/display/xe_display_pcode.c

20

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/display/xe_display_pcode.c

22

return xe_pcode_write_timeout(tile, mbox, val, timeout_ms);

drivers/gpu/drm/xe/display/xe_display_pcode.c

29

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/display/xe_display_pcode.c

31

return xe_pcode_request(tile, mbox, request, reply_mask, reply, timeout_base_ms);

drivers/gpu/drm/xe/display/xe_dsb_buffer.c

84

struct xe_device *xe = dsb_buf->bo->tile->xe;

drivers/gpu/drm/xe/display/xe_hdcp_gsc.c

138

struct xe_gt *gt = gsc_context->hdcp_bo->tile->media_gt;

drivers/gpu/drm/xe/display/xe_hdcp_gsc.c

38

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/display/xe_hdcp_gsc.c

39

struct xe_gt *gt = tile->media_gt;

drivers/gpu/drm/xe/tests/xe_bo.c

110

offset = xe_device_ccs_bytes(tile_to_xe(tile), xe_bo_size(bo));

drivers/gpu/drm/xe/tests/xe_bo.c

127

static void ccs_test_run_tile(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/tests/xe_bo.c

135

unsigned int bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile);

drivers/gpu/drm/xe/tests/xe_bo.c

139

kunit_info(test, "Testing vram id %u\n", tile->id);

drivers/gpu/drm/xe/tests/xe_bo.c

153

ret = ccs_test_migrate(tile, bo, false, 0ULL, 0xdeadbeefdeadbeefULL,

drivers/gpu/drm/xe/tests/xe_bo.c

159

ret = ccs_test_migrate(tile, bo, false, 0xdeadbeefdeadbeefULL,

drivers/gpu/drm/xe/tests/xe_bo.c

165

ret = ccs_test_migrate(tile, bo, true, 0ULL, 0ULL, test, exec);

drivers/gpu/drm/xe/tests/xe_bo.c

175

struct xe_tile *tile;

drivers/gpu/drm/xe/tests/xe_bo.c

190

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/tests/xe_bo.c

194

ccs_test_run_tile(xe, tile, test);

drivers/gpu/drm/xe/tests/xe_bo.c

207

static int evict_test_run_tile(struct xe_device *xe, struct xe_tile *tile, struct kunit *test)

drivers/gpu/drm/xe/tests/xe_bo.c

210

unsigned int bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile);

drivers/gpu/drm/xe/tests/xe_bo.c

217

dev_name(xe->drm.dev), tile->id);

drivers/gpu/drm/xe/tests/xe_bo.c

25

static int ccs_test_migrate(struct xe_tile *tile, struct xe_bo *bo,

drivers/gpu/drm/xe/tests/xe_bo.c

349

struct xe_tile *tile;

drivers/gpu/drm/xe/tests/xe_bo.c

358

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/tests/xe_bo.c

359

evict_test_run_tile(xe, tile, test);

drivers/gpu/drm/xe/tests/xe_bo.c

47

fence = xe_migrate_clear(tile->migrate, bo, bo->ttm.resource,

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

42

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

45

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, tile);

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

47

tile->mem.vram->usable_size = usable;

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

48

KUNIT_ASSERT_EQ(test, usable, xe_vram_region_usable_size(tile->mem.vram));

drivers/gpu/drm/xe/tests/xe_guc_buf_kunit.c

20

struct xe_tile *tile,

drivers/gpu/drm/xe/tests/xe_guc_buf_kunit.c

33

bo->tile = tile;

drivers/gpu/drm/xe/tests/xe_guc_buf_kunit.c

39

struct xe_ggtt *ggtt = tile->mem.ggtt;

drivers/gpu/drm/xe/tests/xe_guc_buf_kunit.c

41

bo->ggtt_node[tile->id] = xe_ggtt_insert_node(ggtt, xe_bo_size(bo), SZ_4K);

drivers/gpu/drm/xe/tests/xe_guc_buf_kunit.c

42

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, bo->ggtt_node[tile->id]);

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

362

u32 tile, dev;

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

367

tile = gt_to_tile(remote_gt)->id;

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

371

guc_g2g_deregister(guc, tile, dev, t);

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

459

static void g2g_alloc_tile(struct kunit *test, struct xe_device *xe, struct xe_tile *tile)

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

465

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, tile);

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

468

tile->id, xe->info.tile_count, xe->info.gt_count);

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

471

bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size,

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

472

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

477

kunit_info(test, "[%d.*] G2G buffer create: 0x%p\n", tile->id, bo);

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

640

u32 tile, dev;

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

645

tile = gt_to_tile(remote_gt)->id;

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

649

ret = g2g_register_flat(guc, tile, dev, t, have_dev);

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

655

static void g2g_reinit(struct kunit *test, struct xe_device *xe, int ctb_type, struct xe_tile *tile)

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

678

g2g_alloc_tile(test, xe, tile);

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

804

struct xe_tile *tile;

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

807

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

810

g2g_reinit(test, xe, G2G_CTB_TYPE_TILE, tile);

drivers/gpu/drm/xe/tests/xe_migrate.c

189

struct xe_tile *tile = m->tile;

drivers/gpu/drm/xe/tests/xe_migrate.c

190

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/tests/xe_migrate.c

197

u8 id = tile->id;

drivers/gpu/drm/xe/tests/xe_migrate.c

206

big = xe_bo_create_pin_map(xe, tile, m->q->vm, SZ_4M,

drivers/gpu/drm/xe/tests/xe_migrate.c

208

XE_BO_FLAG_VRAM_IF_DGFX(tile),

drivers/gpu/drm/xe/tests/xe_migrate.c

215

pt = xe_bo_create_pin_map(xe, tile, m->q->vm, XE_PAGE_SIZE,

drivers/gpu/drm/xe/tests/xe_migrate.c

217

XE_BO_FLAG_VRAM_IF_DGFX(tile),

drivers/gpu/drm/xe/tests/xe_migrate.c

225

tiny = xe_bo_create_pin_map(xe, tile, m->q->vm,

drivers/gpu/drm/xe/tests/xe_migrate.c

228

XE_BO_FLAG_VRAM_IF_DGFX(tile),

drivers/gpu/drm/xe/tests/xe_migrate.c

236

bb = xe_bb_new(tile->primary_gt, 32, xe->info.has_usm);

drivers/gpu/drm/xe/tests/xe_migrate.c

273

emit_clear(tile->primary_gt, bb, xe_migrate_vm_addr(NUM_KERNEL_PDE - 1, 0), 4, 4,

drivers/gpu/drm/xe/tests/xe_migrate.c

345

struct xe_tile *tile;

drivers/gpu/drm/xe/tests/xe_migrate.c

349

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/tests/xe_migrate.c

350

struct xe_migrate *m = tile->migrate;

drivers/gpu/drm/xe/tests/xe_migrate.c

369

static struct dma_fence *blt_copy(struct xe_tile *tile,

drivers/gpu/drm/xe/tests/xe_migrate.c

373

struct xe_gt *gt = tile->primary_gt;

drivers/gpu/drm/xe/tests/xe_migrate.c

374

struct xe_migrate *m = tile->migrate;

drivers/gpu/drm/xe/tests/xe_migrate.c

495

static void test_migrate(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/tests/xe_migrate.c

507

fence = blt_copy(tile, sys_bo, vram_bo, false, "Blit copy from sysmem to vram", test);

drivers/gpu/drm/xe/tests/xe_migrate.c

533

fence = blt_copy(tile, vram_bo, ccs_bo,

drivers/gpu/drm/xe/tests/xe_migrate.c

572

fence = blt_copy(tile, vram_bo, ccs_bo,

drivers/gpu/drm/xe/tests/xe_migrate.c

583

static void test_clear(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/tests/xe_migrate.c

592

fence = blt_copy(tile, sys_bo, vram_bo, false, "Blit copy from sysmem to vram", test);

drivers/gpu/drm/xe/tests/xe_migrate.c

600

fence = blt_copy(tile, vram_bo, sys_bo, false, "Blit copy from vram to sysmem", test);

drivers/gpu/drm/xe/tests/xe_migrate.c

611

fence = xe_migrate_clear(tile->migrate, vram_bo, vram_bo->ttm.resource,

drivers/gpu/drm/xe/tests/xe_migrate.c

617

fence = blt_copy(tile, vram_bo, sys_bo,

drivers/gpu/drm/xe/tests/xe_migrate.c

627

fence = blt_copy(tile, vram_bo, sys_bo,

drivers/gpu/drm/xe/tests/xe_migrate.c

638

static void validate_ccs_test_run_tile(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/tests/xe_migrate.c

642

unsigned int bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile);

drivers/gpu/drm/xe/tests/xe_migrate.c

721

test_clear(xe, tile, sys_bo, vram_bo, test);

drivers/gpu/drm/xe/tests/xe_migrate.c

722

test_migrate(xe, tile, sys_bo, vram_bo, ccs_bo, exec, test);

drivers/gpu/drm/xe/tests/xe_migrate.c

747

struct xe_tile *tile;

drivers/gpu/drm/xe/tests/xe_migrate.c

76

struct xe_device *xe = tile_to_xe(m->tile);

drivers/gpu/drm/xe/tests/xe_migrate.c

761

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/tests/xe_migrate.c

762

validate_ccs_test_run_tile(xe, tile, test);

drivers/gpu/drm/xe/tests/xe_migrate.c

83

struct xe_bo *remote = xe_bo_create_locked(xe, m->tile, NULL,

drivers/gpu/drm/xe/xe_assert.h

144

#define xe_tile_assert(tile, condition) xe_tile_assert_msg((tile), condition, "")

drivers/gpu/drm/xe/xe_assert.h

145

#define xe_tile_assert_msg(tile, condition, msg, arg...) ({ \

drivers/gpu/drm/xe/xe_assert.h

146

const struct xe_tile *__tile = (tile); \

drivers/gpu/drm/xe/xe_bb.c

33

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_bb.c

46

bb->bo = xe_sa_bo_new(!usm ? tile->mem.kernel_bb_pool : gt->usm.bb_pool,

drivers/gpu/drm/xe/xe_bo.c

1083

if (bo->tile)

drivers/gpu/drm/xe/xe_bo.c

1084

migrate = bo->tile->migrate;

drivers/gpu/drm/xe/xe_bo.c

1412

if (bo->tile)

drivers/gpu/drm/xe/xe_bo.c

1413

migrate = bo->tile->migrate;

drivers/gpu/drm/xe/xe_bo.c

1562

if (bo->tile)

drivers/gpu/drm/xe/xe_bo.c

1563

migrate = bo->tile->migrate;

drivers/gpu/drm/xe/xe_bo.c

169

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_bo.c

172

tile = &xe->tiles[mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0)];

drivers/gpu/drm/xe/xe_bo.c

173

return tile->migrate;

drivers/gpu/drm/xe/xe_bo.c

1836

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_bo.c

1847

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_bo.c

1849

xe_ggtt_remove_bo(tile->mem.ggtt, bo);

drivers/gpu/drm/xe/xe_bo.c

2310

struct xe_tile *tile, struct dma_resv *resv,

drivers/gpu/drm/xe/xe_bo.c

2327

xe_assert(xe, !tile || type == ttm_bo_type_kernel);

drivers/gpu/drm/xe/xe_bo.c

2369

bo->tile = tile;

drivers/gpu/drm/xe/xe_bo.c

2503

struct xe_tile *tile, struct xe_vm *vm,

drivers/gpu/drm/xe/xe_bo.c

2527

bo = xe_bo_init_locked(xe, bo, tile, vm ? xe_vm_resv(vm) : NULL,

drivers/gpu/drm/xe/xe_bo.c

2553

if (!tile && flags & XE_BO_FLAG_STOLEN)

drivers/gpu/drm/xe/xe_bo.c

2554

tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_bo.c

2556

xe_assert(xe, tile);

drivers/gpu/drm/xe/xe_bo.c

2560

if (t != tile && !(bo->flags & XE_BO_FLAG_GGTTx(t)))

drivers/gpu/drm/xe/xe_bo.c

2600

struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2605

return __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL, 0, type,

drivers/gpu/drm/xe/xe_bo.c

2609

static struct xe_bo *xe_bo_create_novm(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2621

bo = __xe_bo_create_locked(xe, tile, NULL, size, 0, ~0ULL,

drivers/gpu/drm/xe/xe_bo.c

2690

struct xe_bo *xe_bo_create_pin_range_novm(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2700

bo = __xe_bo_create_locked(xe, tile, NULL, size, start, end,

drivers/gpu/drm/xe/xe_bo.c

2723

struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2738

bo = __xe_bo_create_locked(xe, tile, vm, size, start, end, 0, type,

drivers/gpu/drm/xe/xe_bo.c

2784

xe_bo_create_pin_map_at_novm(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2795

bo = xe_bo_create_pin_map_at_aligned(xe, tile, NULL, size, offset,

drivers/gpu/drm/xe/xe_bo.c

2827

struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2832

return xe_bo_create_pin_map_at_aligned(xe, tile, vm, size, ~0ull, type, flags,

drivers/gpu/drm/xe/xe_bo.c

2853

struct xe_bo *xe_bo_create_pin_map_novm(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2857

return xe_bo_create_pin_map_at_novm(xe, tile, size, ~0ull, type, flags, 0, intr);

drivers/gpu/drm/xe/xe_bo.c

2865

struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2871

KUNIT_STATIC_STUB_REDIRECT(xe_managed_bo_create_pin_map, xe, tile, size, flags);

drivers/gpu/drm/xe/xe_bo.c

2872

bo = xe_bo_create_pin_map_novm(xe, tile, size, ttm_bo_type_kernel, flags, true);

drivers/gpu/drm/xe/xe_bo.c

2888

struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.c

2891

struct xe_bo *bo = xe_managed_bo_create_pin_map(xe, tile, ALIGN(size, PAGE_SIZE), flags);

drivers/gpu/drm/xe/xe_bo.c

2914

int xe_managed_bo_reinit_in_vram(struct xe_device *xe, struct xe_tile *tile, struct xe_bo **src)

drivers/gpu/drm/xe/xe_bo.c

2917

u32 dst_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT;

drivers/gpu/drm/xe/xe_bo.c

2925

bo = xe_managed_bo_create_from_data(xe, tile, (*src)->vmap.vaddr,

drivers/gpu/drm/xe/xe_bo.c

3549

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_bo.c

3573

decomp_fence = xe_migrate_resolve(tile->migrate,

drivers/gpu/drm/xe/xe_bo.c

3855

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_bo.c

3864

for_each_tile(tile, xe_bo_device(bo), id)

drivers/gpu/drm/xe/xe_bo.c

3866

xe_ggtt_might_lock(tile->mem.ggtt);

drivers/gpu/drm/xe/xe_bo.h

118

struct xe_tile *tile, struct dma_resv *resv,

drivers/gpu/drm/xe/xe_bo.h

123

struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.h

129

struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.h

133

struct xe_bo *xe_bo_create_pin_map_novm(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.h

136

struct xe_bo *xe_bo_create_pin_range_novm(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.h

140

xe_bo_create_pin_map_at_novm(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.h

143

struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.h

146

struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_bo.h

148

int xe_managed_bo_reinit_in_vram(struct xe_device *xe, struct xe_tile *tile, struct xe_bo **src);

drivers/gpu/drm/xe/xe_bo.h

30

#define XE_BO_FLAG_VRAM_IF_DGFX(tile) (IS_DGFX(tile_to_xe(tile)) ? \

drivers/gpu/drm/xe/xe_bo.h

31

XE_BO_FLAG_VRAM((tile)->mem.vram) : \

drivers/gpu/drm/xe/xe_bo.h

412

xe_assert(xe_bo_device(bo), bo->tile);

drivers/gpu/drm/xe/xe_bo.h

414

return __xe_bo_ggtt_addr(bo, bo->tile->id);

drivers/gpu/drm/xe/xe_bo.h

65

#define XE_BO_FLAG_GGTTx(tile) \

drivers/gpu/drm/xe/xe_bo.h

66

(XE_BO_FLAG_GGTT0 << (tile)->id)

drivers/gpu/drm/xe/xe_bo_evict.c

162

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_bo_evict.c

181

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_bo_evict.c

182

xe_tile_migrate_wait(tile);

drivers/gpu/drm/xe/xe_bo_evict.c

201

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_bo_evict.c

204

for_each_tile(tile, xe_bo_device(bo), id) {

drivers/gpu/drm/xe/xe_bo_evict.c

205

if (tile != bo->tile && !(bo->flags & XE_BO_FLAG_GGTTx(tile)))

drivers/gpu/drm/xe/xe_bo_evict.c

208

xe_ggtt_map_bo_unlocked(tile->mem.ggtt, bo);

drivers/gpu/drm/xe/xe_bo_evict.c

245

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_bo_evict.c

252

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_bo_evict.c

253

xe_tile_migrate_wait(tile);

drivers/gpu/drm/xe/xe_bo_evict.c

267

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_bo_evict.c

268

xe_tile_migrate_wait(tile);

drivers/gpu/drm/xe/xe_bo_evict.c

275

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_bo_evict.c

281

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_bo_evict.c

282

xe_tile_migrate_wait(tile);

drivers/gpu/drm/xe/xe_bo_types.h

46

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_debugfs.c

553

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_debugfs.c

603

for_each_tile(tile, xe, tile_id)

drivers/gpu/drm/xe/xe_debugfs.c

604

xe_tile_debugfs_register(tile);

drivers/gpu/drm/xe/xe_devcoredump.c

115

drm_printf(&p, "\tTile: %d\n", ss->gt->tile->id);

drivers/gpu/drm/xe/xe_device.c

1000

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_device.c

1001

err = xe_tile_init(tile);

drivers/gpu/drm/xe/xe_device.c

1315

drm_printf(p, "\tTile: %u\n", gt->tile->id);

drivers/gpu/drm/xe/xe_device.c

923

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_device.c

950

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_device.c

951

err = xe_ggtt_init_early(tile->mem.ggtt);

drivers/gpu/drm/xe/xe_device.c

971

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_device.c

972

err = xe_tile_init_noalloc(tile);

drivers/gpu/drm/xe/xe_device.h

140

for_each_if((gt__)->tile == (tile__))

drivers/gpu/drm/xe/xe_device.h

67

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_device.h

73

tile = &xe->tiles[gt_id / xe->info.max_gt_per_tile];

drivers/gpu/drm/xe/xe_device.h

79

gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_device.h

82

gt = tile->media_gt;

drivers/gpu/drm/xe/xe_eu_stall.c

656

struct xe_tile *tile = stream->gt->tile;

drivers/gpu/drm/xe/xe_eu_stall.c

666

bo = xe_bo_create_pin_map_at_novm(tile->xe, tile, size, ~0ull, ttm_bo_type_kernel,

drivers/gpu/drm/xe/xe_eu_stall.c

900

drm_dev_put(&gt->tile->xe->drm);

drivers/gpu/drm/xe/xe_eu_stall.c

953

drm_dev_get(&gt->tile->xe->drm);

drivers/gpu/drm/xe/xe_exec_queue.c

1270

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_exec_queue.c

1319

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_exec_queue.c

1326

new = xe_exec_queue_create_bind(xe, tile, vm, flags,

drivers/gpu/drm/xe/xe_exec_queue.c

169

struct xe_tile *tile = gt_to_tile(q->gt);

drivers/gpu/drm/xe/xe_exec_queue.c

178

gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_exec_queue.c

180

gt = tile->media_gt;

drivers/gpu/drm/xe/xe_exec_queue.c

523

struct xe_tile *tile,

drivers/gpu/drm/xe/xe_exec_queue.c

527

struct xe_gt *gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_exec_queue.c

531

migrate_vm = xe_migrate_get_vm(tile->migrate);

drivers/gpu/drm/xe/xe_exec_queue.c

819

struct xe_tile *tile = gt_to_tile(q->gt);

drivers/gpu/drm/xe/xe_exec_queue.c

827

bo = xe_bo_create_pin_map_novm(xe, tile, SZ_4K, ttm_bo_type_kernel,

drivers/gpu/drm/xe/xe_exec_queue.c

828

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_exec_queue.h

30

struct xe_tile *tile,

drivers/gpu/drm/xe/xe_ggtt.c

113

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_ggtt.c

185

struct xe_tile *tile = ggtt->tile;

drivers/gpu/drm/xe/xe_ggtt.c

189

if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) {

drivers/gpu/drm/xe/xe_ggtt.c

190

affected_gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_ggtt.c

194

xe_tile_assert(tile, IS_DGFX(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_ggtt.c

196

affected_gt = tile->media_gt;

drivers/gpu/drm/xe/xe_ggtt.c

200

xe_tile_assert(tile, !IS_DGFX(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_ggtt.c

240

xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK));

drivers/gpu/drm/xe/xe_ggtt.c

241

xe_tile_assert(ggtt->tile, addr < ggtt->start + ggtt->size);

drivers/gpu/drm/xe/xe_ggtt.c

254

xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK));

drivers/gpu/drm/xe/xe_ggtt.c

255

xe_tile_assert(ggtt->tile, addr < ggtt->start + ggtt->size);

drivers/gpu/drm/xe/xe_ggtt.c

262

u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), XE_CACHE_WB);

drivers/gpu/drm/xe/xe_ggtt.c

266

xe_tile_assert(ggtt->tile, start < end);

drivers/gpu/drm/xe/xe_ggtt.c

299

struct xe_ggtt *xe_ggtt_alloc(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_ggtt.c

301

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_ggtt.c

312

ggtt->tile = tile;

drivers/gpu/drm/xe/xe_ggtt.c

393

struct xe_device *xe = tile_to_xe(ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

405

xe_tile_err(ggtt->tile, "Hardware reported no preallocated GSM\n");

drivers/gpu/drm/xe/xe_ggtt.c

411

ggtt_start = xe_tile_sriov_vf_ggtt_base(ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

412

ggtt_size = xe_tile_sriov_vf_ggtt(ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

416

xe_tile_err(ggtt->tile, "Invalid GGTT configuration: %#llx-%#llx\n",

drivers/gpu/drm/xe/xe_ggtt.c

422

ggtt->gsm = ggtt->tile->mmio.regs + SZ_8M;

drivers/gpu/drm/xe/xe_ggtt.c

431

(ggtt->tile->media_gt && XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||

drivers/gpu/drm/xe/xe_ggtt.c

432

(ggtt->tile->primary_gt && XE_GT_WA(ggtt->tile->primary_gt, 22019338487)) ?

drivers/gpu/drm/xe/xe_ggtt.c

495

struct xe_device *xe = tile_to_xe(node->ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

515

xe = tile_to_xe(ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

535

struct xe_device *xe = tile_to_xe(ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

548

flags |= XE_BO_FLAG_VRAM_IF_DGFX(ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

550

ggtt->scratch = xe_managed_bo_create_pin_map(xe, ggtt->tile, XE_PAGE_SIZE, flags);

drivers/gpu/drm/xe/xe_ggtt.c

579

struct xe_device *xe = tile_to_xe(ggtt->tile);

drivers/gpu/drm/xe/xe_ggtt.c

590

ggtt_invalidate_gt_tlb(ggtt->tile->primary_gt);

drivers/gpu/drm/xe/xe_ggtt.c

591

ggtt_invalidate_gt_tlb(ggtt->tile->media_gt);

drivers/gpu/drm/xe/xe_ggtt.c

611

xe_tile_assert(ggtt->tile, new_start >= xe_wopcm_size(tile_to_xe(ggtt->tile)));

drivers/gpu/drm/xe/xe_ggtt.c

612

xe_tile_assert(ggtt->tile, new_start + ggtt->size <= GUC_GGTT_TOP);

drivers/gpu/drm/xe/xe_ggtt.c

727

u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), cache_mode);

drivers/gpu/drm/xe/xe_ggtt.c

732

xe_ggtt_map_bo(ggtt, bo->ggtt_node[ggtt->tile->id], bo, pte);

drivers/gpu/drm/xe/xe_ggtt.c

791

u8 tile_id = ggtt->tile->id;

drivers/gpu/drm/xe/xe_ggtt.c

799

xe_tile_assert(ggtt->tile, bo->ggtt_node[tile_id]->base.size == xe_bo_size(bo));

drivers/gpu/drm/xe/xe_ggtt.c

807

xe_pm_runtime_get_noresume(tile_to_xe(ggtt->tile));

drivers/gpu/drm/xe/xe_ggtt.c

835

xe_tile_assert(ggtt->tile, end >= start + xe_bo_size(bo));

drivers/gpu/drm/xe/xe_ggtt.c

844

u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), cache_mode);

drivers/gpu/drm/xe/xe_ggtt.c

855

xe_pm_runtime_put(tile_to_xe(ggtt->tile));

drivers/gpu/drm/xe/xe_ggtt.c

897

u8 tile_id = ggtt->tile->id;

drivers/gpu/drm/xe/xe_ggtt.c

903

xe_tile_assert(ggtt->tile, bo->ggtt_node[tile_id]->base.size == xe_bo_size(bo));

drivers/gpu/drm/xe/xe_ggtt.h

16

struct xe_ggtt *xe_ggtt_alloc(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_gsc.c

131

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gsc.c

139

bo = xe_bo_create_pin_map_novm(xe, tile, GSC_VER_PKT_SZ * 2,

drivers/gpu/drm/xe/xe_gsc.c

265

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gsc.c

269

if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 14018094691)) {

drivers/gpu/drm/xe/xe_gsc.c

270

fw_ref = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);

drivers/gpu/drm/xe/xe_gsc.c

277

xe_gt_mcr_multicast_write(tile->primary_gt,

drivers/gpu/drm/xe/xe_gsc.c

284

if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 14018094691))

drivers/gpu/drm/xe/xe_gsc.c

285

xe_force_wake_put(gt_to_fw(tile->primary_gt), fw_ref);

drivers/gpu/drm/xe/xe_gsc.c

403

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gsc.c

411

if (tile->media_gt && (gt != tile->media_gt)) {

drivers/gpu/drm/xe/xe_gsc.c

459

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gsc.c

473

bo = xe_managed_bo_create_pin_map(xe, tile, SZ_4M,

drivers/gpu/drm/xe/xe_gsc_proxy.c

414

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gsc_proxy.c

423

bo = xe_managed_bo_create_pin_map(xe, tile, GSC_PROXY_CHANNEL_SIZE,

drivers/gpu/drm/xe/xe_gsc_proxy.c

493

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gsc_proxy.c

494

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_gsc_proxy.c

504

if (!xe_tile_is_root(tile)) {

drivers/gpu/drm/xe/xe_gsc_proxy.c

505

xe_gt_err(gt, "unexpected GSC proxy init on tile %u\n", tile->id);

drivers/gpu/drm/xe/xe_gt.c

668

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt.c

670

err = xe_migrate_init(tile->migrate);

drivers/gpu/drm/xe/xe_gt.c

71

struct xe_gt *xe_gt_alloc(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_gt.c

73

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_gt.c

75

bool shared_wq = xe->info.needs_shared_vf_gt_wq && tile->primary_gt &&

drivers/gpu/drm/xe/xe_gt.c

774

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt.c

775

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_gt.c

777

xe_mmio_init(&gt->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);

drivers/gpu/drm/xe/xe_gt.c

84

gt->tile = tile;

drivers/gpu/drm/xe/xe_gt.c

85

if (shared_wq && tile->primary_gt->ordered_wq)

drivers/gpu/drm/xe/xe_gt.c

86

ordered_wq = tile->primary_gt->ordered_wq;

drivers/gpu/drm/xe/xe_gt.h

47

struct xe_gt *xe_gt_alloc(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_gt_debugfs.c

343

struct dentry *parent = gt->tile->debugfs;

drivers/gpu/drm/xe/xe_gt_debugfs.c

392

snprintf(symlink, sizeof(symlink), "tile%u/%s", gt->tile->id, name);

drivers/gpu/drm/xe/xe_gt_printk.h

15

xe_tile_printk((_gt)->tile, _level, __XE_GT_PRINTK_FMT((_gt), _fmt, ##__VA_ARGS__))

drivers/gpu/drm/xe/xe_gt_printk.h

39

xe_tile_WARN##_type((_gt)->tile, _condition, _fmt, ## __VA_ARGS__)

drivers/gpu/drm/xe/xe_gt_printk.h

76

dbg = xe_tile_dbg_printer((gt)->tile);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1513

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1517

for_each_tile(tile, xe, tid) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1518

if (tile->primary_gt == gt) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1521

u64 lmem = pf_get_vf_config_lmem(tile->primary_gt, vfid);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1536

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1542

for_each_tile(tile, xe, tid) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1543

lmtt = &tile->sriov.pf.lmtt;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1551

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1557

for_each_tile(tile, xe, tid) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1558

lmtt = &tile->sriov.pf.lmtt;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1566

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1579

for_each_tile(tile, xe, tid)

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1580

total += pf_get_vf_config_lmem(tile->primary_gt, vfid);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1582

for_each_tile(tile, xe, tid) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1583

lmtt = &tile->sriov.pf.lmtt;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1611

for_each_tile(tile, xe, tid) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1612

lmtt = &tile->sriov.pf.lmtt;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1637

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1664

bo = xe_bo_create_pin_range_novm(xe, tile,

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1667

XE_BO_FLAG_VRAM(tile->mem.vram) |

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1876

struct xe_tile *tile = gt->tile;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1878

return xe_ttm_vram_get_avail(&tile->mem.vram->ttm.manager);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1917

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1918

bool admin_only_pf = xe_sriov_pf_admin_only(tile->xe);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

1919

u64 usable = xe_vram_region_usable_size(tile->mem.vram);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

2902

static int pf_sanitize_lmem(struct xe_tile *tile, struct xe_bo *bo, long timeout)

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

2904

struct xe_migrate *m = tile->migrate;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

2923

xe_gt_sriov_dbg_verbose(tile->primary_gt, "LMEM cleared in %dms\n",

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

2934

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

2945

err = pf_sanitize_lmem(tile, config->lmem_obj, timeout);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

394

struct xe_gt *primary = gt->tile->primary_gt;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

485

static int pf_distribute_config_ggtt(struct xe_tile *tile, unsigned int vfid, u64 start, u64 size)

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

489

err = pf_push_vf_cfg_ggtt(tile->primary_gt, vfid, start, size);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

491

if (tile->media_gt && !err)

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

492

err2 = pf_push_vf_cfg_ggtt(tile->media_gt, vfid, start, size);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

507

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

508

struct xe_ggtt *ggtt = tile->mem.ggtt;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

519

err = pf_distribute_config_ggtt(tile, vfid, 0, 0);

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

542

err = pf_distribute_config_ggtt(gt->tile, vfid, xe_ggtt_node_addr(node), size);

drivers/gpu/drm/xe/xe_gt_sriov_pf_control.c

1658

if (xe_tile_is_root(gt->tile) && xe_gt_is_main_type(gt))

drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c

853

xe_gt_assert(gt, extract_priv(parent) == gt->tile);

drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c

896

name, gt->tile->id, gt->info.id);

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

258

ret = xe_sriov_packet_init(data, gt->tile->id, gt->info.id,

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

431

ret = xe_sriov_packet_init(data, gt->tile->id, gt->info.id,

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

566

ret = xe_sriov_packet_init(data, gt->tile->id, gt->info.id,

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

75

ret = xe_sriov_packet_init(data, gt->tile->id, gt->info.id,

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

952

xe_gt_assert(gt, data->hdr.tile_id == gt->tile->id);

drivers/gpu/drm/xe/xe_gt_sriov_printk.h

13

__XE_TILE_SRIOV_PRINTK_FMT((_gt)->tile, __XE_GT_PRINTK_FMT((_gt), _fmt, ##__VA_ARGS__))

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

490

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

508

xe_tile_sriov_vf_ggtt_base_store(tile, start);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

509

ggtt_size = xe_tile_sriov_vf_ggtt(tile);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

518

xe_tile_sriov_vf_ggtt_store(tile, size);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

537

xe_ggtt_shift_nodes(tile->mem.ggtt, start);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

544

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

556

lmem_size = xe_tile_sriov_vf_lmem(tile);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

566

xe_tile_sriov_vf_lmem_store(tile, size);

drivers/gpu/drm/xe/xe_gt_sysfs.c

34

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_gt_sysfs.c

46

err = kobject_add(&kg->base, tile->sysfs, "gt%d", gt->info.id);

drivers/gpu/drm/xe/xe_gt_types.h

120

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_gt_types.h

97

const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \

drivers/gpu/drm/xe/xe_gt_types.h

98

struct xe_gt * : (gt__)->tile)

drivers/gpu/drm/xe/xe_guc.c

1395

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc.c

1397

err = xe_memirq_init_guc(&tile->memirq, guc);

drivers/gpu/drm/xe/xe_guc.c

469

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc.c

491

bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size,

drivers/gpu/drm/xe/xe_guc.c

492

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_guc.c

564

u32 tile, dev;

drivers/gpu/drm/xe/xe_guc.c

572

tile = gt_to_tile(far_gt)->id;

drivers/gpu/drm/xe/xe_guc.c

576

guc_g2g_deregister(guc, tile, dev, t);

drivers/gpu/drm/xe/xe_guc.c

698

struct xe_tile *tile = gt_to_tile(guc_to_gt(guc));

drivers/gpu/drm/xe/xe_guc.c

705

ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo);

drivers/gpu/drm/xe/xe_guc.c

709

ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo);

drivers/gpu/drm/xe/xe_guc.c

713

ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo);

drivers/gpu/drm/xe/xe_guc_ads.c

394

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc_ads.c

402

bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,

drivers/gpu/drm/xe/xe_guc_ct.c

2250

drm_printf(&lp, "\tTile: %d\n", gt->tile->id);

drivers/gpu/drm/xe/xe_guc_ct.c

372

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc_ct.c

375

bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),

drivers/gpu/drm/xe/xe_guc_ct.c

385

bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),

drivers/gpu/drm/xe/xe_guc_ct.c

412

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc_ct.c

418

ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->ctbs.h2g.bo);

drivers/gpu/drm/xe/xe_guc_engine_activity.c

105

bo = xe_bo_create_pin_map_novm(gt_to_xe(gt), tile, PAGE_ALIGN(size),

drivers/gpu/drm/xe/xe_guc_engine_activity.c

106

ttm_bo_type_kernel, XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_guc_engine_activity.c

94

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc_engine_activity.c

97

metadata_bo = xe_bo_create_pin_map_novm(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),

drivers/gpu/drm/xe/xe_guc_hwconfig.c

56

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc_hwconfig.c

81

bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),

drivers/gpu/drm/xe/xe_guc_log.c

627

struct xe_tile *tile = gt_to_tile(log_to_gt(log));

drivers/gpu/drm/xe/xe_guc_log.c

630

bo = xe_managed_bo_create_pin_map(xe, tile, GUC_LOG_SIZE,

drivers/gpu/drm/xe/xe_guc_pc.c

1357

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_guc_pc.c

1370

bo = xe_managed_bo_create_pin_map(xe, tile, size,

drivers/gpu/drm/xe/xe_guc_pc.c

1371

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_huc.c

111

struct xe_tile *tile = gt_to_tile(huc_to_gt(huc));

drivers/gpu/drm/xe/xe_huc.c

121

ret = xe_managed_bo_reinit_in_vram(xe, tile, &huc->fw.bo);

drivers/gpu/drm/xe/xe_hw_engine.c

610

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_hw_engine.c

618

hwe->hwsp = xe_managed_bo_create_pin_map(xe, tile, SZ_4K,

drivers/gpu/drm/xe/xe_hw_engine.c

619

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_hw_error.c

177

struct xe_tile *tile = container_of(work, typeof(*tile), csc_hw_error_work);

drivers/gpu/drm/xe/xe_hw_error.c

178

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

183

static void csc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)

drivers/gpu/drm/xe/xe_hw_error.c

187

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

188

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_hw_error.c

200

tile->id, severity_str);

drivers/gpu/drm/xe/xe_hw_error.c

212

schedule_work(&tile->csc_hw_error_work);

drivers/gpu/drm/xe/xe_hw_error.c

219

static void log_hw_error(struct xe_tile *tile, const char *name,

drivers/gpu/drm/xe/xe_hw_error.c

223

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

231

static void log_gt_err(struct xe_tile *tile, const char *name, int i, u32 err,

drivers/gpu/drm/xe/xe_hw_error.c

235

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

245

static void log_soc_error(struct xe_tile *tile, const char * const *reg_info,

drivers/gpu/drm/xe/xe_hw_error.c

249

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

265

static void gt_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err,

drivers/gpu/drm/xe/xe_hw_error.c

269

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

272

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_hw_error.c

281

log_hw_error(tile, info[error_id].name, severity);

drivers/gpu/drm/xe/xe_hw_error.c

299

log_gt_err(tile, "Subslice", i, vector, severity);

drivers/gpu/drm/xe/xe_hw_error.c

321

log_gt_err(tile, "L3 BANK", i, vector, severity);

drivers/gpu/drm/xe/xe_hw_error.c

326

log_gt_err(tile, "TLB", i, vector, severity);

drivers/gpu/drm/xe/xe_hw_error.c

331

log_gt_err(tile, "L3 Fabric", i, vector, severity);

drivers/gpu/drm/xe/xe_hw_error.c

334

log_gt_err(tile, "Undefined", i, vector, severity);

drivers/gpu/drm/xe/xe_hw_error.c

341

static void soc_slave_ieh_handler(struct xe_tile *tile, const enum hardware_error hw_err, u32 error_id)

drivers/gpu/drm/xe/xe_hw_error.c

345

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_hw_error.c

356

log_soc_error(tile, pvc_slave_local_fatal_err_reg, severity,

drivers/gpu/drm/xe/xe_hw_error.c

365

log_soc_error(tile, pvc_slave_global_err_reg, severity, regbit, error_id);

drivers/gpu/drm/xe/xe_hw_error.c

370

static void soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err,

drivers/gpu/drm/xe/xe_hw_error.c

374

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

375

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_hw_error.c

405

soc_slave_ieh_handler(tile, hw_err, error_id);

drivers/gpu/drm/xe/xe_hw_error.c

411

log_soc_error(tile, PVC_MASTER_LOCAL_REG_INFO(hw_err), severity, regbit, error_id);

drivers/gpu/drm/xe/xe_hw_error.c

417

log_soc_error(tile, pvc_master_global_err_reg, severity, regbit, error_id);

drivers/gpu/drm/xe/xe_hw_error.c

427

static void hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)

drivers/gpu/drm/xe/xe_hw_error.c

431

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_hw_error.c

441

err_src = xe_mmio_read32(&tile->mmio, DEV_ERR_STAT_REG(hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

444

tile->id, severity_str);

drivers/gpu/drm/xe/xe_hw_error.c

455

csc_hw_error_handler(tile, hw_err);

drivers/gpu/drm/xe/xe_hw_error.c

477

tile->id, name, severity_str, err_bit);

drivers/gpu/drm/xe/xe_hw_error.c

481

tile->id, name, severity_str, err_bit);

drivers/gpu/drm/xe/xe_hw_error.c

485

gt_hw_error_handler(tile, hw_err, error_id);

drivers/gpu/drm/xe/xe_hw_error.c

487

soc_hw_error_handler(tile, hw_err, error_id);

drivers/gpu/drm/xe/xe_hw_error.c

491

xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), err_src);

drivers/gpu/drm/xe/xe_hw_error.c

506

void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)

drivers/gpu/drm/xe/xe_hw_error.c

511

schedule_work(&tile->csc_hw_error_work);

drivers/gpu/drm/xe/xe_hw_error.c

515

hw_error_source_handler(tile, hw_err);

drivers/gpu/drm/xe/xe_hw_error.c

532

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_hw_error.c

536

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_hw_error.c

537

master_ctl = xe_mmio_read32(&tile->mmio, GFX_MSTR_IRQ);

drivers/gpu/drm/xe/xe_hw_error.c

538

xe_hw_error_irq_handler(tile, master_ctl);

drivers/gpu/drm/xe/xe_hw_error.c

539

xe_mmio_write32(&tile->mmio, GFX_MSTR_IRQ, master_ctl);

drivers/gpu/drm/xe/xe_hw_error.c

552

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_hw_error.c

558

INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);

drivers/gpu/drm/xe/xe_hw_error.h

13

void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);

drivers/gpu/drm/xe/xe_irq.c

325

static struct xe_gt *pick_engine_gt(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_irq.c

329

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_irq.c

332

return tile->primary_gt;

drivers/gpu/drm/xe/xe_irq.c

337

return tile->media_gt;

drivers/gpu/drm/xe/xe_irq.c

343

return tile->media_gt;

drivers/gpu/drm/xe/xe_irq.c

349

return tile->primary_gt;

drivers/gpu/drm/xe/xe_irq.c

353

static void gt_irq_handler(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_irq.c

357

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_irq.c

358

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_irq.c

382

engine_gt = pick_engine_gt(tile, class, instance);

drivers/gpu/drm/xe/xe_irq.c

416

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_irq.c

430

gt_irq_handler(tile, master_ctl, intr_dw, identity);

drivers/gpu/drm/xe/xe_irq.c

478

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_irq.c

495

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_irq.c

496

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_irq.c

498

if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)

drivers/gpu/drm/xe/xe_irq.c

50

drm_WARN(&mmio->tile->xe->drm, 1,

drivers/gpu/drm/xe/xe_irq.c

509

drm_dbg(&tile_to_xe(tile)->drm,

drivers/gpu/drm/xe/xe_irq.c

516

gt_irq_handler(tile, master_ctl, intr_dw, identity);

drivers/gpu/drm/xe/xe_irq.c

517

xe_hw_error_irq_handler(tile, master_ctl);

drivers/gpu/drm/xe/xe_irq.c

541

static void gt_irq_reset(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_irq.c

543

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_irq.c

547

if (tile->primary_gt) {

drivers/gpu/drm/xe/xe_irq.c

548

ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,

drivers/gpu/drm/xe/xe_irq.c

550

bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,

drivers/gpu/drm/xe/xe_irq.c

579

if ((tile->media_gt &&

drivers/gpu/drm/xe/xe_irq.c

580

xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) ||

drivers/gpu/drm/xe/xe_irq.c

581

tile_to_xe(tile)->info.has_heci_gscfi) {

drivers/gpu/drm/xe/xe_irq.c

595

static void xelp_irq_reset(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_irq.c

597

xelp_intr_disable(tile_to_xe(tile));

drivers/gpu/drm/xe/xe_irq.c

599

gt_irq_reset(tile);

drivers/gpu/drm/xe/xe_irq.c

601

if (IS_SRIOV_VF(tile_to_xe(tile)))

drivers/gpu/drm/xe/xe_irq.c

604

mask_and_disable(tile, PCU_IRQ_OFFSET);

drivers/gpu/drm/xe/xe_irq.c

607

static void dg1_irq_reset(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_irq.c

609

if (xe_tile_is_root(tile))

drivers/gpu/drm/xe/xe_irq.c

610

dg1_intr_disable(tile_to_xe(tile));

drivers/gpu/drm/xe/xe_irq.c

612

gt_irq_reset(tile);

drivers/gpu/drm/xe/xe_irq.c

614

if (IS_SRIOV_VF(tile_to_xe(tile)))

drivers/gpu/drm/xe/xe_irq.c

617

mask_and_disable(tile, PCU_IRQ_OFFSET);

drivers/gpu/drm/xe/xe_irq.c

620

static void dg1_irq_reset_mstr(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_irq.c

622

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_irq.c

629

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_irq.c

63

static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)

drivers/gpu/drm/xe/xe_irq.c

639

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_irq.c

641

xe_memirq_reset(&tile->memirq);

drivers/gpu/drm/xe/xe_irq.c

643

gt_irq_reset(tile);

drivers/gpu/drm/xe/xe_irq.c

649

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_irq.c

65

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_irq.c

656

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_irq.c

657

xe_memirq_reset(&tile->memirq);

drivers/gpu/drm/xe/xe_irq.c

660

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_irq.c

662

dg1_irq_reset(tile);

drivers/gpu/drm/xe/xe_irq.c

664

xelp_irq_reset(tile);

drivers/gpu/drm/xe/xe_irq.c

667

tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_irq.c

668

mask_and_disable(tile, GU_MISC_IRQ_OFFSET);

drivers/gpu/drm/xe/xe_irq.c

678

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_irq.c

679

dg1_irq_reset_mstr(tile);

drivers/gpu/drm/xe/xe_irq.c

685

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_irq.c

688

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_irq.c

690

xe_memirq_postinstall(&tile->memirq);

drivers/gpu/drm/xe/xe_irq.c

704

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_irq.c

707

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_irq.c

708

xe_memirq_postinstall(&tile->memirq);

drivers/gpu/drm/xe/xe_irq.c

731

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_irq.c

737

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_irq.c

738

xe_memirq_handler(&tile->memirq);

drivers/gpu/drm/xe/xe_irq.c

81

static void mask_and_disable(struct xe_tile *tile, u32 irqregs)

drivers/gpu/drm/xe/xe_irq.c

83

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_irq.c

910

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_irq.c

916

for_each_tile(tile, xe, tile_id) {

drivers/gpu/drm/xe/xe_irq.c

917

memirq = &tile->memirq;

drivers/gpu/drm/xe/xe_irq.c

922

if (gt->tile != tile)

drivers/gpu/drm/xe/xe_lmtt.c

118

lmtt_debug(&pt->bo->tile->sriov.pf.lmtt, "level=%u addr=%llx\n",

drivers/gpu/drm/xe/xe_lmtt.c

215

struct xe_tile *tile = lmtt_to_tile(lmtt);

drivers/gpu/drm/xe/xe_lmtt.c

216

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_lmtt.c

228

for_each_gt_on_tile(gt, tile, id)

drivers/gpu/drm/xe/xe_lmtt.c

233

if (xe_device_has_mert(xe) && xe_tile_is_root(tile))

drivers/gpu/drm/xe/xe_lmtt.c

234

xe_mmio_write32(&tile->mmio, MERT_LMEM_CFG, config);

drivers/gpu/drm/xe/xe_lmtt.c

259

struct xe_tile *tile = lmtt_to_tile(lmtt);

drivers/gpu/drm/xe/xe_lmtt.c

265

for_each_gt_on_tile(gt, tile, id) {

drivers/gpu/drm/xe/xe_lmtt.c

280

for_each_gt_on_tile(gt, tile, id)

drivers/gpu/drm/xe/xe_lmtt.c

297

struct xe_tile *tile = lmtt_to_tile(lmtt);

drivers/gpu/drm/xe/xe_lmtt.c

305

xe_tile_sriov_err(tile, "LMTT invalidation failed (%pe)",

drivers/gpu/drm/xe/xe_lmtt.c

308

if (xe_device_has_mert(xe) && xe_tile_is_root(tile)) {

drivers/gpu/drm/xe/xe_lmtt.c

311

xe_tile_sriov_err(tile, "MERT LMTT invalidation failed (%pe)",

drivers/gpu/drm/xe/xe_lrc.c

1493

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_lrc.c

1531

xe_memirq_status_ptr(&tile->memirq, hwe));

drivers/gpu/drm/xe/xe_lrc.c

1533

xe_memirq_source_ptr(&tile->memirq, hwe));

drivers/gpu/drm/xe/xe_lrc.c

1638

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_lrc.c

1660

bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT |

drivers/gpu/drm/xe/xe_lrc.c

1666

bo = xe_bo_create_pin_map_novm(xe, tile, bo_size,

drivers/gpu/drm/xe/xe_lrc.c

1674

bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE,

drivers/gpu/drm/xe/xe_mem_pool.c

117

struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,

drivers/gpu/drm/xe/xe_mem_pool.c

120

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_mem_pool.c

126

xe_tile_assert(tile, size > guard);

drivers/gpu/drm/xe/xe_mem_pool.c

133

bo = xe_managed_bo_create_pin_map(xe, tile, size,

drivers/gpu/drm/xe/xe_mem_pool.c

134

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_mem_pool.c

139

xe_tile_err(tile, "Failed to prepare %uKiB BO for mem pool (%pe)\n",

drivers/gpu/drm/xe/xe_mem_pool.c

170

xe_tile_err(tile,

drivers/gpu/drm/xe/xe_mem_pool.c

192

struct xe_tile *tile = pool_to_tile(pool);

drivers/gpu/drm/xe/xe_mem_pool.c

193

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_mem_pool.c

195

xe_tile_assert(tile, pool->shadow);

drivers/gpu/drm/xe/xe_mem_pool.c

215

struct xe_tile *tile = pool_to_tile(pool);

drivers/gpu/drm/xe/xe_mem_pool.c

217

xe_tile_assert(tile, pool->shadow);

drivers/gpu/drm/xe/xe_mem_pool.c

238

struct xe_tile *tile = pool_to_tile(pool);

drivers/gpu/drm/xe/xe_mem_pool.c

239

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_mem_pool.c

242

xe_tile_assert(tile, pool->shadow);

drivers/gpu/drm/xe/xe_mem_pool.c

296

struct xe_tile *tile = pool_to_tile(pool);

drivers/gpu/drm/xe/xe_mem_pool.c

297

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_mem_pool.c

316

struct xe_tile *tile = pool_to_tile(pool);

drivers/gpu/drm/xe/xe_mem_pool.c

317

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_mem_pool.c

57

return pool->bo->tile;

drivers/gpu/drm/xe/xe_mem_pool.c

72

struct xe_tile *tile = pool->bo->tile;

drivers/gpu/drm/xe/xe_mem_pool.c

73

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_mem_pool.c

88

shadow = xe_managed_bo_create_pin_map(xe, tile,

drivers/gpu/drm/xe/xe_mem_pool.c

90

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_mem_pool.h

18

struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,

drivers/gpu/drm/xe/xe_memirq.c

175

static unsigned int hwe_max_count(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_memirq.c

182

for_each_gt_on_tile(gt, tile, gtid)

drivers/gpu/drm/xe/xe_memirq.c

192

struct xe_tile *tile = memirq_to_tile(memirq);

drivers/gpu/drm/xe/xe_memirq.c

201

num_pages = hw_reports_to_instance_zero(memirq) ? hwe_max_count(tile) : 1;

drivers/gpu/drm/xe/xe_memirq.c

204

bo = xe_managed_bo_create_pin_map(xe, tile, bo_size,

drivers/gpu/drm/xe/xe_memirq.c

554

struct xe_tile *tile = memirq_to_tile(memirq);

drivers/gpu/drm/xe/xe_memirq.c

568

if (gt->tile != tile)

drivers/gpu/drm/xe/xe_memirq.c

580

memirq_dispatch_guc(memirq, &map, &tile->primary_gt->uc.guc);

drivers/gpu/drm/xe/xe_memirq.c

583

if (!tile->media_gt)

drivers/gpu/drm/xe/xe_memirq.c

589

memirq_dispatch_guc(memirq, &map, &tile->media_gt->uc.guc);

drivers/gpu/drm/xe/xe_mert.c

100

struct xe_mert *mert = &tile->mert;

drivers/gpu/drm/xe/xe_mert.c

111

reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);

drivers/gpu/drm/xe/xe_mert.c

21

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_mert.c

22

struct xe_mert *mert = &tile->mert;

drivers/gpu/drm/xe/xe_mert.c

38

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_mert.c

39

struct xe_mert *mert = &tile->mert;

drivers/gpu/drm/xe/xe_mert.c

49

xe_mmio_write32(&tile->mmio, MERT_TLB_INV_DESC_A, MERT_TLB_INV_DESC_A_VALID);

drivers/gpu/drm/xe/xe_mert.c

61

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_mert.c

64

reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT);

drivers/gpu/drm/xe/xe_mert.c

67

xe_mmio_write32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT, 0);

drivers/gpu/drm/xe/xe_mert.c

99

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_migrate.c

1180

int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,

drivers/gpu/drm/xe/xe_migrate.c

1189

struct xe_migrate *m = tile->migrate;

drivers/gpu/drm/xe/xe_migrate.c

1190

struct xe_gt *gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.c

1391

struct xe_tile *tile = vram_bo->tile;

drivers/gpu/drm/xe/xe_migrate.c

1392

struct xe_gt *gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.c

1393

struct xe_migrate *m = tile->migrate;

drivers/gpu/drm/xe/xe_migrate.c

1610

struct xe_gt *gt = m->tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.c

1745

static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,

drivers/gpu/drm/xe/xe_migrate.c

1763

xe_tile_assert(tile, update->qwords < MAX_NUM_PTE);

drivers/gpu/drm/xe/xe_migrate.c

1765

ppgtt_ofs = xe_migrate_vram_ofs(tile_to_xe(tile),

drivers/gpu/drm/xe/xe_migrate.c

1782

ops->populate(pt_update, tile, NULL, bb->cs + bb->len,

drivers/gpu/drm/xe/xe_migrate.c

1785

ops->clear(pt_update, tile, NULL, bb->cs + bb->len,

drivers/gpu/drm/xe/xe_migrate.c

1842

ops->populate(pt_update, m->tile,

drivers/gpu/drm/xe/xe_migrate.c

1847

ops->clear(pt_update, m->tile,

drivers/gpu/drm/xe/xe_migrate.c

1865

struct xe_tile *tile = m->tile;

drivers/gpu/drm/xe/xe_migrate.c

1866

struct xe_gt *gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.c

1867

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_migrate.c

189

static int xe_migrate_pt_bo_alloc(struct xe_tile *tile, struct xe_migrate *m,

drivers/gpu/drm/xe/xe_migrate.c

192

struct xe_bo *bo, *batch = tile->mem.kernel_bb_pool->bo;

drivers/gpu/drm/xe/xe_migrate.c

1959

xe_tile_assert(tile, xe_bo_size(pt_bo) == SZ_4K);

drivers/gpu/drm/xe/xe_migrate.c

1992

write_pgtable(tile, bb, addr +

drivers/gpu/drm/xe/xe_migrate.c

2008

write_pgtable(tile, bb, 0, pt_op, &updates[j],

drivers/gpu/drm/xe/xe_migrate.c

203

xe_tile_assert(tile, m->batch_base_ofs + xe_bo_size(batch) < SZ_2M);

drivers/gpu/drm/xe/xe_migrate.c

205

bo = xe_bo_create_pin_map(vm->xe, tile, vm,

drivers/gpu/drm/xe/xe_migrate.c

208

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_migrate.c

2128

u16 pat_index = xe_cache_pat_idx(tile_to_xe(m->tile), XE_CACHE_WB);

drivers/gpu/drm/xe/xe_migrate.c

2133

xe_tile_assert(m->tile, PAGE_ALIGNED(size));

drivers/gpu/drm/xe/xe_migrate.c

2153

xe_tile_assert(m->tile, sram_addr[i].proto ==

drivers/gpu/drm/xe/xe_migrate.c

2156

xe_tile_assert(m->tile, addr);

drivers/gpu/drm/xe/xe_migrate.c

2157

xe_tile_assert(m->tile, PAGE_ALIGNED(addr));

drivers/gpu/drm/xe/xe_migrate.c

2160

pte = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe,

drivers/gpu/drm/xe/xe_migrate.c

217

static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,

drivers/gpu/drm/xe/xe_migrate.c

220

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_migrate.c

222

u8 id = tile->id;

drivers/gpu/drm/xe/xe_migrate.c

2223

struct xe_gt *gt = m->tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.c

228

struct xe_bo *bo = m->pt_bo, *batch = tile->mem.kernel_bb_pool->bo;

drivers/gpu/drm/xe/xe_migrate.c

2461

struct xe_tile *tile = m->tile;

drivers/gpu/drm/xe/xe_migrate.c

2462

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_migrate.c

265

xe_tile_assert(tile, xe_bo_size(batch) == SZ_1M);

drivers/gpu/drm/xe/xe_migrate.c

267

batch = tile->primary_gt->usm.bb_pool->bo;

drivers/gpu/drm/xe/xe_migrate.c

269

xe_tile_assert(tile, xe_bo_size(batch) == SZ_512K);

drivers/gpu/drm/xe/xe_migrate.c

288

batch = tile->primary_gt->usm.bb_pool->bo;

drivers/gpu/drm/xe/xe_migrate.c

420

struct xe_migrate *xe_migrate_alloc(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_migrate.c

422

struct xe_migrate *m = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*m), GFP_KERNEL);

drivers/gpu/drm/xe/xe_migrate.c

425

m->tile = tile;

drivers/gpu/drm/xe/xe_migrate.c

429

static int xe_migrate_lock_prepare_vm(struct xe_tile *tile, struct xe_migrate *m, struct xe_vm *vm)

drivers/gpu/drm/xe/xe_migrate.c

431

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_migrate.c

444

err = xe_migrate_pt_bo_alloc(tile, m, vm, &exec);

drivers/gpu/drm/xe/xe_migrate.c

448

xe_migrate_prepare_vm(tile, m, vm, &map_ofs);

drivers/gpu/drm/xe/xe_migrate.c

465

struct xe_tile *tile = m->tile;

drivers/gpu/drm/xe/xe_migrate.c

466

struct xe_gt *primary_gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.c

467

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_migrate.c

473

XE_VM_FLAG_SET_TILE_ID(tile), NULL);

drivers/gpu/drm/xe/xe_migrate.c

477

err = xe_migrate_lock_prepare_vm(tile, m, vm);

drivers/gpu/drm/xe/xe_migrate.c

55

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_migrate.c

555

struct xe_device *xe = tile_to_xe(m->tile);

drivers/gpu/drm/xe/xe_migrate.c

601

*L0_ofs = xe_migrate_vram_ofs(tile_to_xe(m->tile),

drivers/gpu/drm/xe/xe_migrate.c

632

struct xe_device *xe = tile_to_xe(m->tile);

drivers/gpu/drm/xe/xe_migrate.c

678

addr = vm->pt_ops->pte_encode_addr(m->tile->xe,

drivers/gpu/drm/xe/xe_migrate.c

849

struct xe_gt *gt = m->tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.c

893

struct xe_gt *gt = m->tile->primary_gt;

drivers/gpu/drm/xe/xe_migrate.h

113

struct xe_migrate *xe_migrate_alloc(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_migrate.h

139

int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,

drivers/gpu/drm/xe/xe_migrate.h

56

struct xe_tile *tile, struct iosys_map *map,

drivers/gpu/drm/xe/xe_migrate.h

74

struct xe_tile *tile, struct iosys_map *map,

drivers/gpu/drm/xe/xe_mmio.c

122

void xe_mmio_init(struct xe_mmio *mmio, struct xe_tile *tile, void __iomem *ptr, u32 size)

drivers/gpu/drm/xe/xe_mmio.c

124

xe_tile_assert(tile, size <= XE_REG_ADDR_MAX);

drivers/gpu/drm/xe/xe_mmio.c

128

mmio->tile = tile;

drivers/gpu/drm/xe/xe_mmio.c

136

if (!XE_DEVICE_WA(mmio->tile->xe, 15015404425))

drivers/gpu/drm/xe/xe_mmio.c

185

if (!reg.vf && IS_SRIOV_VF(mmio->tile->xe))

drivers/gpu/drm/xe/xe_mmio.c

187

mmio->tile->primary_gt, reg, val);

drivers/gpu/drm/xe/xe_mmio.c

199

if (!reg.vf && IS_SRIOV_VF(mmio->tile->xe))

drivers/gpu/drm/xe/xe_mmio.c

201

mmio->tile->primary_gt, reg);

drivers/gpu/drm/xe/xe_mmio.c

272

xe_tile_assert(mmio->tile, !in_range(mmio->adj_limit, reg.addr + 1, 7));

drivers/gpu/drm/xe/xe_mmio.c

28

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_mmio.c

285

drm_WARN(&mmio->tile->xe->drm, retries == 0,

drivers/gpu/drm/xe/xe_mmio.c

31

for_each_remote_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_mmio.c

32

tile->mmio.regs = NULL;

drivers/gpu/drm/xe/xe_mmio.c

402

struct xe_tile *tile = base->tile;

drivers/gpu/drm/xe/xe_mmio.c

403

struct xe_device *xe = tile->xe;

drivers/gpu/drm/xe/xe_mmio.c

56

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_mmio.c

66

for_each_remote_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_mmio.c

67

xe_mmio_init(&tile->mmio, tile, xe->mmio.regs + id * tile_mmio_size, SZ_4M);

drivers/gpu/drm/xe/xe_mmio.h

17

void xe_mmio_init(struct xe_mmio *mmio, struct xe_tile *tile, void __iomem *ptr, u32 size);

drivers/gpu/drm/xe/xe_mmio_types.h

24

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_oa.c

911

bo = xe_bo_create_pin_map_novm(stream->oa->xe, stream->gt->tile,

drivers/gpu/drm/xe/xe_page_reclaim.c

35

bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma)

drivers/gpu/drm/xe/xe_page_reclaim.c

42

l3_policy = xe_pat_index_get_l3_policy(tile->xe, vma->attr.pat_index);

drivers/gpu/drm/xe/xe_page_reclaim.c

71

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_page_reclaim.c

78

prl_sa = __xe_sa_bo_new(tile->mem.reclaim_pool,

drivers/gpu/drm/xe/xe_page_reclaim.h

75

bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma);

drivers/gpu/drm/xe/xe_pagefault.c

102

if (xe_vm_has_valid_gpu_mapping(tile, vma->tile_present,

drivers/gpu/drm/xe/xe_pagefault.c

119

err = xe_pagefault_begin(&exec, vma, tile->mem.vram,

drivers/gpu/drm/xe/xe_pagefault.c

129

fence = xe_vma_rebind(vm, vma, BIT(tile->id));

drivers/gpu/drm/xe/xe_pagefault.c

83

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_pci.c

1003

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_pci.c

1006

err = xe_tile_alloc_vram(tile);

drivers/gpu/drm/xe/xe_pci.c

1010

tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);

drivers/gpu/drm/xe/xe_pci.c

1011

if (IS_ERR(tile->primary_gt))

drivers/gpu/drm/xe/xe_pci.c

1012

return PTR_ERR(tile->primary_gt);

drivers/gpu/drm/xe/xe_pci.c

1021

if (!tile->primary_gt) {

drivers/gpu/drm/xe/xe_pci.c

1026

tile->media_gt = alloc_media_gt(tile, media_desc);

drivers/gpu/drm/xe/xe_pci.c

1027

if (IS_ERR(tile->media_gt))

drivers/gpu/drm/xe/xe_pci.c

1028

return PTR_ERR(tile->media_gt);

drivers/gpu/drm/xe/xe_pci.c

628

gt->tile = &xe->tiles[0];

drivers/gpu/drm/xe/xe_pci.c

844

static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pci.c

848

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_pci.c

856

gt = xe_gt_alloc(tile);

drivers/gpu/drm/xe/xe_pci.c

861

gt->info.id = tile->id * xe->info.max_gt_per_tile;

drivers/gpu/drm/xe/xe_pci.c

887

static struct xe_gt *alloc_media_gt(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pci.c

890

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_pci.c

901

gt = xe_gt_alloc(tile);

drivers/gpu/drm/xe/xe_pci.c

906

gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;

drivers/gpu/drm/xe/xe_pci.c

927

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_pci.c

994

for_each_remote_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_pci.c

997

err = xe_tile_init_early(tile, xe, id);

drivers/gpu/drm/xe/xe_pcode.c

101

static int pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1,

drivers/gpu/drm/xe/xe_pcode.c

105

if (tile_to_xe(tile)->info.skip_pcode)

drivers/gpu/drm/xe/xe_pcode.c

108

lockdep_assert_held(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

110

return __pcode_mailbox_rw(tile, mbox, data0, data1, timeout_ms, return_data, atomic);

drivers/gpu/drm/xe/xe_pcode.c

113

int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 data, int timeout)

drivers/gpu/drm/xe/xe_pcode.c

117

mutex_lock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

118

err = pcode_mailbox_rw(tile, mbox, &data, NULL, timeout, false, false);

drivers/gpu/drm/xe/xe_pcode.c

119

mutex_unlock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

124

int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, u32 data1, int timeout)

drivers/gpu/drm/xe/xe_pcode.c

128

mutex_lock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

129

err = pcode_mailbox_rw(tile, mbox, &data0, &data1, timeout, false, false);

drivers/gpu/drm/xe/xe_pcode.c

130

mutex_unlock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

135

int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1)

drivers/gpu/drm/xe/xe_pcode.c

139

mutex_lock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

140

err = pcode_mailbox_rw(tile, mbox, val, val1, 1, true, false);

drivers/gpu/drm/xe/xe_pcode.c

141

mutex_unlock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

146

static int pcode_try_request(struct xe_tile *tile, u32 mbox,

drivers/gpu/drm/xe/xe_pcode.c

152

xe_tile_assert(tile, timeout_us > 0);

drivers/gpu/drm/xe/xe_pcode.c

156

*status = pcode_mailbox_rw(tile, mbox, &request, NULL, 1, true,

drivers/gpu/drm/xe/xe_pcode.c

159

*status = __pcode_mailbox_rw(tile, mbox, &request, NULL, 1, true,

drivers/gpu/drm/xe/xe_pcode.c

193

int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,

drivers/gpu/drm/xe/xe_pcode.c

199

xe_tile_assert(tile, timeout_base_ms <= 3);

drivers/gpu/drm/xe/xe_pcode.c

201

mutex_lock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

203

ret = pcode_try_request(tile, mbox, request, reply_mask, reply, &status,

drivers/gpu/drm/xe/xe_pcode.c

218

drm_err(&tile_to_xe(tile)->drm,

drivers/gpu/drm/xe/xe_pcode.c

221

ret = pcode_try_request(tile, mbox, request, reply_mask, reply, &status,

drivers/gpu/drm/xe/xe_pcode.c

226

mutex_unlock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

254

int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,

drivers/gpu/drm/xe/xe_pcode.c

260

if (!tile_to_xe(tile)->info.has_llc)

drivers/gpu/drm/xe/xe_pcode.c

266

mutex_lock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

270

ret = pcode_mailbox_rw(tile, PCODE_WRITE_MIN_FREQ_TABLE,

drivers/gpu/drm/xe/xe_pcode.c

277

mutex_unlock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

297

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_pcode.c

308

mutex_lock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

310

ret = pcode_try_request(tile, DGFX_PCODE_STATUS, request,

drivers/gpu/drm/xe/xe_pcode.c

316

mutex_unlock(&tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

33

static int pcode_mailbox_status(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_pcode.c

332

void xe_pcode_init(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_pcode.c

334

drmm_mutex_init(&tile_to_xe(tile)->drm, &tile->pcode.lock);

drivers/gpu/drm/xe/xe_pcode.c

45

err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK;

drivers/gpu/drm/xe/xe_pcode.c

60

drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s",

drivers/gpu/drm/xe/xe_pcode.c

70

static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1,

drivers/gpu/drm/xe/xe_pcode.c

74

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_pcode.c

77

if (tile_to_xe(tile)->info.skip_pcode)

drivers/gpu/drm/xe/xe_pcode.c

98

return pcode_mailbox_status(tile);

drivers/gpu/drm/xe/xe_pcode.h

15

void xe_pcode_init(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_pcode.h

18

int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,

drivers/gpu/drm/xe/xe_pcode.h

20

int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);

drivers/gpu/drm/xe/xe_pcode.h

21

int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,

drivers/gpu/drm/xe/xe_pcode.h

23

int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,

drivers/gpu/drm/xe/xe_pcode.h

26

#define xe_pcode_write(tile, mbox, val) \

drivers/gpu/drm/xe/xe_pcode.h

27

xe_pcode_write_timeout(tile, mbox, val, 1)

drivers/gpu/drm/xe/xe_pcode.h

29

int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,

drivers/gpu/drm/xe/xe_pm.c

233

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_pm.c

245

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_pm.c

246

xe_wa_apply_tile_workarounds(tile);

drivers/gpu/drm/xe/xe_psmi.c

71

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_psmi.c

76

tile = &xe->tiles[id - 1];

drivers/gpu/drm/xe/xe_psmi.c

79

return xe_bo_create_pin_range_novm(xe, tile, bo_size, 0, ~0ull,

drivers/gpu/drm/xe/xe_psmi.c

81

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_pt.c

1013

if (!(pt_mask & BIT(tile->id)))

drivers/gpu/drm/xe/xe_pt.c

1023

xe_vm_populate_pgtable(struct xe_migrate_pt_update *pt_update, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

104

struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

1044

xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *

drivers/gpu/drm/xe/xe_pt.c

1207

xe_pt_prepare_bind(struct xe_tile *tile, struct xe_vma *vma,

drivers/gpu/drm/xe/xe_pt.c

1215

err = xe_pt_stage_bind(tile, vma, range, entries, num_entries,

drivers/gpu/drm/xe/xe_pt.c

1218

xe_tile_assert(tile, *num_entries);

drivers/gpu/drm/xe/xe_pt.c

122

bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_pt.c

131

bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K,

drivers/gpu/drm/xe/xe_pt.c

144

xe_tile_assert(tile, level <= XE_VM_MAX_LEVEL);

drivers/gpu/drm/xe/xe_pt.c

1609

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_pt.c

164

void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,

drivers/gpu/drm/xe/xe_pt.c

1660

static int generate_reclaim_entry(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

1664

struct xe_gt *gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_pt.c

1676

xe_tile_assert(tile, xe_child->level <= MAX_HUGEPTE_LEVEL);

drivers/gpu/drm/xe/xe_pt.c

1677

xe_tile_assert(tile, reclaim_entries);

drivers/gpu/drm/xe/xe_pt.c

1678

xe_tile_assert(tile, num_entries < XE_PAGE_RECLAIM_MAX_ENTRIES - 1);

drivers/gpu/drm/xe/xe_pt.c

1696

xe_page_reclaim_list_abort(tile->primary_gt, prl,

drivers/gpu/drm/xe/xe_pt.c

1708

vm_dbg(&tile_to_xe(tile)->drm,

drivers/gpu/drm/xe/xe_pt.c

1715

static int add_pte_to_prl(struct xe_tile *tile, struct xe_page_reclaim_list *prl,

drivers/gpu/drm/xe/xe_pt.c

1723

xe_page_reclaim_list_abort(tile->primary_gt, prl,

drivers/gpu/drm/xe/xe_pt.c

1729

xe_tile_assert(tile, xe_child->level == 0 ||

drivers/gpu/drm/xe/xe_pt.c

1734

xe_page_reclaim_list_abort(tile->primary_gt, prl,

drivers/gpu/drm/xe/xe_pt.c

1739

return generate_reclaim_entry(tile, prl, pte, xe_child);

drivers/gpu/drm/xe/xe_pt.c

1742

static bool add_compact_pt_prl(struct xe_tile *tile, struct xe_page_reclaim_list *prl,

drivers/gpu/drm/xe/xe_pt.c

1750

if (add_pte_to_prl(tile, prl, compact_pt, pte, addr + i * SZ_64K))

drivers/gpu/drm/xe/xe_pt.c

1767

struct xe_tile *tile = xe_walk->tile;

drivers/gpu/drm/xe/xe_pt.c

1768

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_pt.c

178

empty = __xe_pt_empty_pte(tile, vm, pt->level);

drivers/gpu/drm/xe/xe_pt.c

1802

if (!add_compact_pt_prl(tile, prl, xe, child_pt,

drivers/gpu/drm/xe/xe_pt.c

1806

xe_page_reclaim_list_abort(tile->primary_gt,

drivers/gpu/drm/xe/xe_pt.c

1817

if (add_pte_to_prl(tile, prl, xe_child, pte, addr))

drivers/gpu/drm/xe/xe_pt.c

1841

xe_page_reclaim_list_abort(tile->primary_gt, prl,

drivers/gpu/drm/xe/xe_pt.c

1907

static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

1924

.tile = tile,

drivers/gpu/drm/xe/xe_pt.c

1930

struct xe_pt *pt = vm->pt_root[tile->id];

drivers/gpu/drm/xe/xe_pt.c

1940

struct xe_tile *tile, struct iosys_map *map,

drivers/gpu/drm/xe/xe_pt.c

1945

u64 empty = __xe_pt_empty_pte(tile, vm, update->pt->level);

drivers/gpu/drm/xe/xe_pt.c

1950

xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *

drivers/gpu/drm/xe/xe_pt.c

2048

static int bind_op_prepare(struct xe_vm *vm, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2056

xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));

drivers/gpu/drm/xe/xe_pt.c

2065

pt_op->rebind = BIT(tile->id) & vma->tile_present;

drivers/gpu/drm/xe/xe_pt.c

2067

err = vma_reserve_fences(tile_to_xe(tile), vma);

drivers/gpu/drm/xe/xe_pt.c

2071

err = xe_pt_prepare_bind(tile, vma, NULL, pt_op->entries,

drivers/gpu/drm/xe/xe_pt.c

2074

xe_tile_assert(tile, pt_op->num_entries <=

drivers/gpu/drm/xe/xe_pt.c

2076

xe_vm_dbg_print_entries(tile_to_xe(tile), pt_op->entries,

drivers/gpu/drm/xe/xe_pt.c

2104

vma->tile_staged |= BIT(tile->id);

drivers/gpu/drm/xe/xe_pt.c

2115

static int bind_range_prepare(struct xe_vm *vm, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2123

xe_tile_assert(tile, xe_vma_is_cpu_addr_mirror(vma));

drivers/gpu/drm/xe/xe_pt.c

2131

pt_op->rebind = BIT(tile->id) & range->tile_present;

drivers/gpu/drm/xe/xe_pt.c

2133

err = xe_pt_prepare_bind(tile, vma, range, pt_op->entries,

drivers/gpu/drm/xe/xe_pt.c

2136

xe_tile_assert(tile, pt_op->num_entries <=

drivers/gpu/drm/xe/xe_pt.c

2138

xe_vm_dbg_print_entries(tile_to_xe(tile), pt_op->entries,

drivers/gpu/drm/xe/xe_pt.c

2157

static int unbind_op_prepare(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2161

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_pt.c

2166

if (!((vma->tile_present | vma->tile_staged) & BIT(tile->id)))

drivers/gpu/drm/xe/xe_pt.c

2169

xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));

drivers/gpu/drm/xe/xe_pt.c

2189

!xe_page_reclaim_skip(tile, vma)) ? &pt_update_ops->prl : NULL;

drivers/gpu/drm/xe/xe_pt.c

2191

err = vma_reserve_fences(tile_to_xe(tile), vma);

drivers/gpu/drm/xe/xe_pt.c

2195

pt_op->num_entries = xe_pt_stage_unbind(tile, xe_vma_vm(vma),

drivers/gpu/drm/xe/xe_pt.c

2198

xe_vm_dbg_print_entries(tile_to_xe(tile), pt_op->entries,

drivers/gpu/drm/xe/xe_pt.c

2238

struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2245

if (!(range->tile_present & BIT(tile->id)))

drivers/gpu/drm/xe/xe_pt.c

2257

pt_op->num_entries = xe_pt_stage_unbind(tile, vm, NULL, range,

drivers/gpu/drm/xe/xe_pt.c

2260

xe_vm_dbg_print_entries(tile_to_xe(tile), pt_op->entries,

drivers/gpu/drm/xe/xe_pt.c

2267

xe_vm_has_valid_gpu_mapping(tile, range->tile_present,

drivers/gpu/drm/xe/xe_pt.c

2278

struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2293

err = bind_op_prepare(vm, tile, pt_update_ops, op->map.vma,

drivers/gpu/drm/xe/xe_pt.c

2304

err = unbind_op_prepare(tile, pt_update_ops, old);

drivers/gpu/drm/xe/xe_pt.c

2307

err = bind_op_prepare(vm, tile, pt_update_ops,

drivers/gpu/drm/xe/xe_pt.c

2312

err = bind_op_prepare(vm, tile, pt_update_ops,

drivers/gpu/drm/xe/xe_pt.c

2325

err = unbind_op_prepare(tile, pt_update_ops, vma);

drivers/gpu/drm/xe/xe_pt.c

2337

err = bind_range_prepare(vm, tile, pt_update_ops,

drivers/gpu/drm/xe/xe_pt.c

2343

err = bind_op_prepare(vm, tile, pt_update_ops, vma, false);

drivers/gpu/drm/xe/xe_pt.c

2352

err = bind_range_prepare(vm, tile, pt_update_ops,

drivers/gpu/drm/xe/xe_pt.c

2356

err = unbind_range_prepare(vm, tile, pt_update_ops,

drivers/gpu/drm/xe/xe_pt.c

2390

int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops)

drivers/gpu/drm/xe/xe_pt.c

2393

&vops->pt_update_ops[tile->id];

drivers/gpu/drm/xe/xe_pt.c

2395

int shift = tile->media_gt ? 1 : 0;

drivers/gpu/drm/xe/xe_pt.c

2404

tile_to_xe(tile)->info.tile_count << shift);

drivers/gpu/drm/xe/xe_pt.c

2409

err = op_prepare(vops->vm, tile, pt_update_ops, op);

drivers/gpu/drm/xe/xe_pt.c

2415

xe_tile_assert(tile, pt_update_ops->current_op <=

drivers/gpu/drm/xe/xe_pt.c

2428

static void bind_op_commit(struct xe_vm *vm, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2433

xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));

drivers/gpu/drm/xe/xe_pt.c

2447

WRITE_ONCE(vma->tile_present, vma->tile_present | BIT(tile->id));

drivers/gpu/drm/xe/xe_pt.c

2450

vma->tile_invalidated | BIT(tile->id));

drivers/gpu/drm/xe/xe_pt.c

2453

vma->tile_invalidated & ~BIT(tile->id));

drivers/gpu/drm/xe/xe_pt.c

2454

vma->tile_staged &= ~BIT(tile->id);

drivers/gpu/drm/xe/xe_pt.c

2470

static void unbind_op_commit(struct xe_vm *vm, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2475

xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));

drivers/gpu/drm/xe/xe_pt.c

2488

vma->tile_present &= ~BIT(tile->id);

drivers/gpu/drm/xe/xe_pt.c

2514

struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.c

2527

bind_op_commit(vm, tile, pt_update_ops, op->map.vma, fence,

drivers/gpu/drm/xe/xe_pt.c

2537

unbind_op_commit(vm, tile, pt_update_ops, old, fence, fence2);

drivers/gpu/drm/xe/xe_pt.c

2540

bind_op_commit(vm, tile, pt_update_ops, op->remap.prev,

drivers/gpu/drm/xe/xe_pt.c

2543

bind_op_commit(vm, tile, pt_update_ops, op->remap.next,

drivers/gpu/drm/xe/xe_pt.c

2552

unbind_op_commit(vm, tile, pt_update_ops, vma, fence,

drivers/gpu/drm/xe/xe_pt.c

2565

range_present_and_invalidated_tile(vm, range, tile->id);

drivers/gpu/drm/xe/xe_pt.c

2567

bind_op_commit(vm, tile, pt_update_ops, vma, fence,

drivers/gpu/drm/xe/xe_pt.c

2576

range_present_and_invalidated_tile(vm, op->map_range.range, tile->id);

drivers/gpu/drm/xe/xe_pt.c

2580

~BIT(tile->id));

drivers/gpu/drm/xe/xe_pt.c

2626

xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)

drivers/gpu/drm/xe/xe_pt.c

2630

&vops->pt_update_ops[tile->id];

drivers/gpu/drm/xe/xe_pt.c

2642

.tile_id = tile->id,

drivers/gpu/drm/xe/xe_pt.c

2649

xe_tile_assert(tile, xe_vm_in_fault_mode(vm));

drivers/gpu/drm/xe/xe_pt.c

2662

to_dep_scheduler(q, tile->primary_gt);

drivers/gpu/drm/xe/xe_pt.c

2664

ijob = xe_tlb_inval_job_create(q, &tile->primary_gt->tlb_inval,

drivers/gpu/drm/xe/xe_pt.c

2686

if (tile->media_gt) {

drivers/gpu/drm/xe/xe_pt.c

2687

dep_scheduler = to_dep_scheduler(q, tile->media_gt);

drivers/gpu/drm/xe/xe_pt.c

2690

&tile->media_gt->tlb_inval,

drivers/gpu/drm/xe/xe_pt.c

2709

fence = xe_migrate_update_pgtables(tile->migrate, &update);

drivers/gpu/drm/xe/xe_pt.c

2724

if (xe_range_fence_insert(&vm->rftree[tile->id], rfence,

drivers/gpu/drm/xe/xe_pt.c

2731

ifence = xe_tlb_inval_job_push(ijob, tile->migrate, fence);

drivers/gpu/drm/xe/xe_pt.c

2733

mfence = xe_tlb_inval_job_push(mjob, tile->migrate, fence);

drivers/gpu/drm/xe/xe_pt.c

2742

op_commit(vops->vm, tile, pt_update_ops, op, fence, NULL);

drivers/gpu/drm/xe/xe_pt.c

2750

op_commit(vops->vm, tile, pt_update_ops, op, ifence, NULL);

drivers/gpu/drm/xe/xe_pt.c

2763

op_commit(vops->vm, tile, pt_update_ops, op, ifence,

drivers/gpu/drm/xe/xe_pt.c

2790

if (err != -EAGAIN && err != -ENODATA && tile->id)

drivers/gpu/drm/xe/xe_pt.c

2804

void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops)

drivers/gpu/drm/xe/xe_pt.c

2807

&vops->pt_update_ops[tile->id];

drivers/gpu/drm/xe/xe_pt.c

2820

xe_bo_put_commit(&vops->pt_update_ops[tile->id].deferred);

drivers/gpu/drm/xe/xe_pt.c

2830

void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops)

drivers/gpu/drm/xe/xe_pt.c

2833

&vops->pt_update_ops[tile->id];

drivers/gpu/drm/xe/xe_pt.c

2855

xe_pt_update_ops_fini(tile, vops);

drivers/gpu/drm/xe/xe_pt.c

291

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_pt.c

603

xe_child = xe_pt_create(xe_walk->vm, xe_walk->tile, level - 1,

drivers/gpu/drm/xe/xe_pt.c

612

xe_pt_populate_empty(xe_walk->tile, xe_walk->vm, xe_child);

drivers/gpu/drm/xe/xe_pt.c

62

static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm,

drivers/gpu/drm/xe/xe_pt.c

623

if (GRAPHICS_VERx100(tile_to_xe(xe_walk->tile)) >= 1250 && level == 1 &&

drivers/gpu/drm/xe/xe_pt.c

65

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_pt.c

67

u8 id = tile->id;

drivers/gpu/drm/xe/xe_pt.c

706

xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,

drivers/gpu/drm/xe/xe_pt.c

711

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_pt.c

723

.tile = tile,

drivers/gpu/drm/xe/xe_pt.c

731

struct xe_pt *pt = vm->pt_root[tile->id];

drivers/gpu/drm/xe/xe_pt.c

878

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_pt.c

914

xe_map_memset(tile_to_xe(xe_walk->tile), &xe_child->bo->vmap,

drivers/gpu/drm/xe/xe_pt.c

943

bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma)

drivers/gpu/drm/xe/xe_pt.c

951

.tile = tile,

drivers/gpu/drm/xe/xe_pt.c

953

struct xe_pt *pt = xe_vma_vm(vma)->pt_root[tile->id];

drivers/gpu/drm/xe/xe_pt.c

961

if (!(pt_mask & BIT(tile->id)))

drivers/gpu/drm/xe/xe_pt.c

985

bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,

drivers/gpu/drm/xe/xe_pt.c

994

.tile = tile,

drivers/gpu/drm/xe/xe_pt.c

996

struct xe_pt *pt = vm->pt_root[tile->id];

drivers/gpu/drm/xe/xe_pt.h

32

struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.h

35

void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,

drivers/gpu/drm/xe/xe_pt.h

42

int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops);

drivers/gpu/drm/xe/xe_pt.h

43

struct dma_fence *xe_pt_update_ops_run(struct xe_tile *tile,

drivers/gpu/drm/xe/xe_pt.h

45

void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops);

drivers/gpu/drm/xe/xe_pt.h

46

void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops);

drivers/gpu/drm/xe/xe_pt.h

48

bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);

drivers/gpu/drm/xe/xe_pt.h

49

bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,

drivers/gpu/drm/xe/xe_pxp_submit.c

119

bo = xe_bo_create_pin_map(xe, tile, vm, PXP_BB_SIZE + inout_size * 2,

drivers/gpu/drm/xe/xe_pxp_submit.c

38

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_pxp_submit.c

57

bo = xe_bo_create_pin_map_novm(xe, tile, SZ_4K, ttm_bo_type_kernel,

drivers/gpu/drm/xe/xe_pxp_submit.c

89

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_pxp_submit.c

90

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_query.c

602

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_query.c

605

for_each_tile(tile, xe, gt_id) {

drivers/gpu/drm/xe/xe_query.c

606

if (tile->media_gt) {

drivers/gpu/drm/xe/xe_query.c

607

media_gt = tile->media_gt;

drivers/gpu/drm/xe/xe_ras_types.h

28

u8 tile;

drivers/gpu/drm/xe/xe_sa.c

130

struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);

drivers/gpu/drm/xe/xe_sa.c

151

struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);

drivers/gpu/drm/xe/xe_sa.c

221

struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);

drivers/gpu/drm/xe/xe_sa.c

238

struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);

drivers/gpu/drm/xe/xe_sa.c

47

struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size,

drivers/gpu/drm/xe/xe_sa.c

50

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_sa.c

56

xe_tile_assert(tile, size > guard);

drivers/gpu/drm/xe/xe_sa.c

63

bo = xe_managed_bo_create_pin_map(xe, tile, size,

drivers/gpu/drm/xe/xe_sa.c

64

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_sa.c

98

shadow = xe_managed_bo_create_pin_map(xe, tile, size,

drivers/gpu/drm/xe/xe_sa.c

99

XE_BO_FLAG_VRAM_IF_DGFX(tile) |

drivers/gpu/drm/xe/xe_sa.h

18

struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size,

drivers/gpu/drm/xe/xe_sa.h

22

static inline struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align)

drivers/gpu/drm/xe/xe_sa.h

24

return __xe_sa_bo_manager_init(tile, size, SZ_4K, align, 0);

drivers/gpu/drm/xe/xe_sched_job.c

321

struct xe_device *xe = q->gt->tile->xe;

drivers/gpu/drm/xe/xe_sriov_packet.c

132

bo = xe_bo_create_pin_map_novm(data->xe, gt->tile, PAGE_ALIGN(data->hdr.size),

drivers/gpu/drm/xe/xe_sriov_pf_debugfs.c

325

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_sriov_pf_debugfs.c

328

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_sriov_pf_debugfs.c

329

xe_tile_sriov_pf_debugfs_populate(tile, dent, vfid);

drivers/gpu/drm/xe/xe_sriov_pf_migration.c

262

if (!gt || data->hdr.tile_id != gt->tile->id || data->hdr.type == 0) {

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

469

static u64 vram_per_tile(struct xe_tile *tile, u64 total)

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

471

struct xe_device *xe = tile->xe;

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

473

u64 alignment = xe_lmtt_page_size(&tile->sriov.pf.lmtt);

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

493

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

502

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

503

err = xe_gt_sriov_pf_config_bulk_set_lmem_locked(tile->primary_gt,

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

505

vram_per_tile(tile, size));

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

526

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

536

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

537

err = xe_gt_sriov_pf_config_set_lmem_locked(tile->primary_gt, vfid,

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

538

vram_per_tile(tile, size));

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

559

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

567

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_sriov_pf_provision.c

568

total += xe_gt_sriov_pf_config_get_lmem_locked(tile->primary_gt, vfid);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

144

static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

147

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

156

pool = xe_mem_pool_init(tile, bb_pool_size, sizeof(u32),

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

338

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

359

q = xe_exec_queue_create_bind(xe, tile, NULL, flags, 0);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

366

err = alloc_bb_pool(tile, ctx);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

424

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

429

tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

437

err = xe_migrate_ccs_rw_copy(tile, ctx->mig_q, bo, new_mem, ctx_id);

drivers/gpu/drm/xe/xe_svm.c

1225

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_svm.c

1241

dpagemap = ctx.devmem_only ? xe_tile_local_pagemap(tile) :

drivers/gpu/drm/xe/xe_svm.c

1242

xe_vma_resolve_pagemap(vma, tile);

drivers/gpu/drm/xe/xe_svm.c

1254

if (xe_svm_range_is_valid(range, tile, ctx.devmem_only, dpagemap)) {

drivers/gpu/drm/xe/xe_svm.c

1333

fence = xe_vm_range_rebind(vm, vma, range, BIT(tile->id));

drivers/gpu/drm/xe/xe_svm.c

1533

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_svm.c

1547

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_svm.c

1548

if (xe_pt_zap_ptes_range(tile, vm, range)) {

drivers/gpu/drm/xe/xe_svm.c

1586

struct drm_pagemap *xe_vma_resolve_pagemap(struct xe_vma *vma, struct xe_tile *tile)

drivers/gpu/drm/xe/xe_svm.c

160

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_svm.c

1600

return IS_DGFX(tile_to_xe(tile)) ? xe_tile_local_pagemap(tile) : NULL;

drivers/gpu/drm/xe/xe_svm.c

183

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_svm.c

184

if (xe_pt_zap_ptes_range(tile, vm, range)) {

drivers/gpu/drm/xe/xe_svm.c

1874

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_svm.c

1877

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_svm.c

1883

vr = xe_tile_to_vr(tile);

drivers/gpu/drm/xe/xe_svm.c

1920

int xe_pagemap_cache_create(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_svm.c

1922

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_svm.c

193

xe_svm_tlb_inval_count_stats_incr(tile->primary_gt);

drivers/gpu/drm/xe/xe_svm.c

1931

tile->mem.vram->dpagemap_cache = cache;

drivers/gpu/drm/xe/xe_svm.c

194

if (tile->media_gt)

drivers/gpu/drm/xe/xe_svm.c

195

xe_svm_tlb_inval_count_stats_incr(tile->media_gt);

drivers/gpu/drm/xe/xe_svm.c

2013

int xe_pagemap_cache_create(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_svm.c

2025

struct drm_pagemap *xe_vma_resolve_pagemap(struct xe_vma *vma, struct xe_tile *tile)

drivers/gpu/drm/xe/xe_svm.c

232

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_svm.c

290

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_svm.c

292

xe_svm_tlb_inval_us_stats_incr(tile->primary_gt, start);

drivers/gpu/drm/xe/xe_svm.c

293

if (tile->media_gt)

drivers/gpu/drm/xe/xe_svm.c

294

xe_svm_tlb_inval_us_stats_incr(tile->media_gt, start);

drivers/gpu/drm/xe/xe_svm.c

840

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_svm.c

843

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_svm.c

972

struct xe_tile *tile,

drivers/gpu/drm/xe/xe_svm.c

977

return (xe_vm_has_valid_gpu_mapping(tile, range->tile_present,

drivers/gpu/drm/xe/xe_svm.h

122

struct drm_pagemap *xe_vma_resolve_pagemap(struct xe_vma *vma, struct xe_tile *tile);

drivers/gpu/drm/xe/xe_svm.h

189

int xe_pagemap_cache_create(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_svm.h

227

int xe_devm_add(struct xe_tile *tile, struct xe_vram_region *vr)

drivers/gpu/drm/xe/xe_svm.h

361

struct drm_pagemap *xe_vma_resolve_pagemap(struct xe_vma *vma, struct xe_tile *tile)

drivers/gpu/drm/xe/xe_svm.h

380

static inline int xe_pagemap_cache_create(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_svm.h

80

int xe_devm_add(struct xe_tile *tile, struct xe_vram_region *vr);

drivers/gpu/drm/xe/xe_sync.c

349

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_sync.c

352

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_sysctrl.c

61

struct xe_tile *tile = xe_device_get_root_tile(xe);

drivers/gpu/drm/xe/xe_sysctrl.c

75

xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);

drivers/gpu/drm/xe/xe_tile.c

114

int xe_tile_alloc_vram(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.c

116

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_tile.c

122

vram = xe_vram_region_alloc(xe, tile->id, XE_PL_VRAM0 + tile->id);

drivers/gpu/drm/xe/xe_tile.c

125

tile->mem.vram = vram;

drivers/gpu/drm/xe/xe_tile.c

132

if (!tile->mem.kernel_vram)

drivers/gpu/drm/xe/xe_tile.c

133

tile->mem.kernel_vram = tile->mem.vram;

drivers/gpu/drm/xe/xe_tile.c

149

int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id)

drivers/gpu/drm/xe/xe_tile.c

153

tile->xe = xe;

drivers/gpu/drm/xe/xe_tile.c

154

tile->id = id;

drivers/gpu/drm/xe/xe_tile.c

156

err = xe_tile_alloc(tile);

drivers/gpu/drm/xe/xe_tile.c

160

xe_pcode_init(tile);

drivers/gpu/drm/xe/xe_tile.c

180

int xe_tile_init_noalloc(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.c

182

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_tile.c

185

xe_wa_apply_tile_workarounds(tile);

drivers/gpu/drm/xe/xe_tile.c

187

err = xe_pagemap_cache_create(tile);

drivers/gpu/drm/xe/xe_tile.c

191

if (IS_DGFX(xe) && !ttm_resource_manager_used(&tile->mem.vram->ttm.manager)) {

drivers/gpu/drm/xe/xe_tile.c

192

err = xe_ttm_vram_mgr_init(xe, tile->mem.vram);

drivers/gpu/drm/xe/xe_tile.c

196

xe->info.mem_region_mask |= BIT(tile->mem.vram->id) << 1;

drivers/gpu/drm/xe/xe_tile.c

199

return xe_tile_sysfs_init(tile);

drivers/gpu/drm/xe/xe_tile.c

202

int xe_tile_init(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.c

206

err = xe_memirq_init(&tile->memirq);

drivers/gpu/drm/xe/xe_tile.c

210

tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);

drivers/gpu/drm/xe/xe_tile.c

211

if (IS_ERR(tile->mem.kernel_bb_pool))

drivers/gpu/drm/xe/xe_tile.c

212

return PTR_ERR(tile->mem.kernel_bb_pool);

drivers/gpu/drm/xe/xe_tile.c

215

tile->mem.reclaim_pool = xe_sa_bo_manager_init(tile, SZ_1M, XE_PAGE_RECLAIM_LIST_MAX_SIZE);

drivers/gpu/drm/xe/xe_tile.c

216

if (IS_ERR(tile->mem.reclaim_pool))

drivers/gpu/drm/xe/xe_tile.c

217

return PTR_ERR(tile->mem.reclaim_pool);

drivers/gpu/drm/xe/xe_tile.c

221

void xe_tile_migrate_wait(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.c

223

xe_migrate_wait(tile->migrate);

drivers/gpu/drm/xe/xe_tile.c

234

struct drm_pagemap *xe_tile_local_pagemap(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.c

237

drm_pagemap_get_from_cache_if_active(xe_tile_to_vr(tile)->dpagemap_cache);

drivers/gpu/drm/xe/xe_tile.c

240

xe_assert(tile_to_xe(tile), kref_read(&dpagemap->ref) >= 2);

drivers/gpu/drm/xe/xe_tile.c

92

static int xe_tile_alloc(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.c

94

tile->mem.ggtt = xe_ggtt_alloc(tile);

drivers/gpu/drm/xe/xe_tile.c

95

if (!tile->mem.ggtt)

drivers/gpu/drm/xe/xe_tile.c

98

tile->migrate = xe_migrate_alloc(tile);

drivers/gpu/drm/xe/xe_tile.c

99

if (!tile->migrate)

drivers/gpu/drm/xe/xe_tile.h

14

int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id);

drivers/gpu/drm/xe/xe_tile.h

15

int xe_tile_init_noalloc(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile.h

16

int xe_tile_init(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile.h

18

int xe_tile_alloc_vram(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile.h

20

void xe_tile_migrate_wait(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile.h

22

static inline bool xe_tile_is_root(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.h

24

return tile->id == 0;

drivers/gpu/drm/xe/xe_tile.h

34

static inline struct xe_vram_region *xe_tile_to_vr(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile.h

36

return tile->mem.vram;

drivers/gpu/drm/xe/xe_tile.h

40

struct drm_pagemap *xe_tile_local_pagemap(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile.h

42

static inline struct drm_pagemap *xe_tile_local_pagemap(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_debugfs.c

109

static void tile_debugfs_create_vram_mm(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_debugfs.c

111

if (tile->mem.vram)

drivers/gpu/drm/xe/xe_tile_debugfs.c

112

ttm_resource_manager_create_debugfs(&tile->mem.vram->ttm.manager, tile->debugfs,

drivers/gpu/drm/xe/xe_tile_debugfs.c

123

void xe_tile_debugfs_register(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_debugfs.c

125

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_tile_debugfs.c

130

snprintf(name, sizeof(name), "tile%u", tile->id);

drivers/gpu/drm/xe/xe_tile_debugfs.c

131

tile->debugfs = debugfs_create_dir(name, root);

drivers/gpu/drm/xe/xe_tile_debugfs.c

132

if (IS_ERR(tile->debugfs))

drivers/gpu/drm/xe/xe_tile_debugfs.c

140

tile->debugfs->d_inode->i_private = tile;

drivers/gpu/drm/xe/xe_tile_debugfs.c

144

tile->debugfs, minor);

drivers/gpu/drm/xe/xe_tile_debugfs.c

146

tile_debugfs_create_vram_mm(tile);

drivers/gpu/drm/xe/xe_tile_debugfs.c

65

struct xe_tile *tile = node_to_tile(node);

drivers/gpu/drm/xe/xe_tile_debugfs.c

68

return print(tile, &p);

drivers/gpu/drm/xe/xe_tile_debugfs.c

83

struct xe_tile *tile = node_to_tile(node);

drivers/gpu/drm/xe/xe_tile_debugfs.c

84

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_tile_debugfs.c

90

static int ggtt(struct xe_tile *tile, struct drm_printer *p)

drivers/gpu/drm/xe/xe_tile_debugfs.c

92

return xe_ggtt_dump(tile->mem.ggtt, p);

drivers/gpu/drm/xe/xe_tile_debugfs.c

95

static int sa_info(struct xe_tile *tile, struct drm_printer *p)

drivers/gpu/drm/xe/xe_tile_debugfs.c

97

drm_suballoc_dump_debug_info(&tile->mem.kernel_bb_pool->base, p,

drivers/gpu/drm/xe/xe_tile_debugfs.c

98

xe_sa_manager_gpu_addr(tile->mem.kernel_bb_pool));

drivers/gpu/drm/xe/xe_tile_debugfs.h

12

void xe_tile_debugfs_register(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile_printk.h

102

static inline struct drm_printer xe_tile_info_printer(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_printk.h

106

.arg = tile,

drivers/gpu/drm/xe/xe_tile_printk.h

117

static inline struct drm_printer xe_tile_dbg_printer(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_printk.h

121

.arg = tile,

drivers/gpu/drm/xe/xe_tile_printk.h

54

struct xe_tile *tile = p->arg;

drivers/gpu/drm/xe/xe_tile_printk.h

56

xe_tile_err(tile, "%pV", vaf);

drivers/gpu/drm/xe/xe_tile_printk.h

61

struct xe_tile *tile = p->arg;

drivers/gpu/drm/xe/xe_tile_printk.h

63

xe_tile_info(tile, "%pV", vaf);

drivers/gpu/drm/xe/xe_tile_printk.h

68

struct xe_tile *tile = p->arg;

drivers/gpu/drm/xe/xe_tile_printk.h

75

dbg = xe_dbg_printer(tile->xe);

drivers/gpu/drm/xe/xe_tile_printk.h

78

drm_printf(&dbg, __XE_TILE_PRINTK_FMT(tile, "%pV", vaf));

drivers/gpu/drm/xe/xe_tile_printk.h

87

static inline struct drm_printer xe_tile_err_printer(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_printk.h

91

.arg = tile,

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

101

static int pf_config_print_vram(struct xe_tile *tile, struct drm_printer *p)

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

103

return xe_gt_sriov_pf_config_print_lmem(tile->primary_gt, p);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

135

struct xe_tile *tile = extract_tile(data); \

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

137

struct xe_gt *gt = tile->primary_gt; \

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

138

struct xe_device *xe = tile->xe; \

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

155

struct xe_tile *tile = extract_tile(data); \

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

157

struct xe_gt *gt = tile->primary_gt; \

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

168

static void pf_add_config_attrs(struct xe_tile *tile, struct dentry *dent, unsigned int vfid)

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

170

struct xe_device *xe = tile->xe;

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

172

xe_tile_assert(tile, tile == extract_tile(dent));

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

173

xe_tile_assert(tile, vfid == extract_vfid(dent));

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

183

static void pf_populate_tile(struct xe_tile *tile, struct dentry *dent, unsigned int vfid)

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

185

struct xe_device *xe = tile->xe;

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

190

pf_add_config_attrs(tile, dent, vfid);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

202

for_each_gt_on_tile(gt, tile, id)

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

217

void xe_tile_sriov_pf_debugfs_populate(struct xe_tile *tile, struct dentry *parent,

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

220

struct xe_device *xe = tile->xe;

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

224

xe_tile_assert(tile, IS_SRIOV_PF(xe));

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

225

xe_tile_assert(tile, extract_priv(parent->d_parent) == xe);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

226

xe_tile_assert(tile, extract_priv(parent) == tile->xe ||

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

241

snprintf(name, sizeof(name), "tile%u", tile->id);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

245

dent->d_inode->i_private = tile;

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

247

xe_tile_assert(tile, extract_tile(dent) == tile);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

248

xe_tile_assert(tile, extract_vfid(dent) == vfid);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

249

xe_tile_assert(tile, extract_xe(dent) == xe);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

251

pf_populate_tile(tile, dent, vfid);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

70

static int pf_config_print_available_ggtt(struct xe_tile *tile, struct drm_printer *p)

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

72

return xe_gt_sriov_pf_config_print_available_ggtt(tile->primary_gt, p);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

75

static int pf_config_print_ggtt(struct xe_tile *tile, struct drm_printer *p)

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.c

77

return xe_gt_sriov_pf_config_print_ggtt(tile->primary_gt, p);

drivers/gpu/drm/xe/xe_tile_sriov_pf_debugfs.h

12

void xe_tile_sriov_pf_debugfs_populate(struct xe_tile *tile, struct dentry *parent,

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

104

u64 xe_tile_sriov_vf_ggtt(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

106

struct xe_tile_sriov_vf_selfconfig *config = &tile->sriov.vf.self_config;

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

108

xe_tile_assert(tile, IS_SRIOV_VF(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

120

void xe_tile_sriov_vf_ggtt_store(struct xe_tile *tile, u64 ggtt_size)

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

122

struct xe_tile_sriov_vf_selfconfig *config = &tile->sriov.vf.self_config;

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

124

xe_tile_assert(tile, IS_SRIOV_VF(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

137

u64 xe_tile_sriov_vf_ggtt_base(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

139

struct xe_tile_sriov_vf_selfconfig *config = &tile->sriov.vf.self_config;

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

141

xe_tile_assert(tile, IS_SRIOV_VF(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

153

void xe_tile_sriov_vf_ggtt_base_store(struct xe_tile *tile, u64 ggtt_base)

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

155

struct xe_tile_sriov_vf_selfconfig *config = &tile->sriov.vf.self_config;

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

157

xe_tile_assert(tile, IS_SRIOV_VF(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

71

u64 xe_tile_sriov_vf_lmem(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

73

struct xe_tile_sriov_vf_selfconfig *config = &tile->sriov.vf.self_config;

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

75

xe_tile_assert(tile, IS_SRIOV_VF(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

87

void xe_tile_sriov_vf_lmem_store(struct xe_tile *tile, u64 lmem_size)

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

89

struct xe_tile_sriov_vf_selfconfig *config = &tile->sriov.vf.self_config;

drivers/gpu/drm/xe/xe_tile_sriov_vf.c

91

xe_tile_assert(tile, IS_SRIOV_VF(tile_to_xe(tile)));

drivers/gpu/drm/xe/xe_tile_sriov_vf.h

13

u64 xe_tile_sriov_vf_ggtt(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile_sriov_vf.h

14

void xe_tile_sriov_vf_ggtt_store(struct xe_tile *tile, u64 ggtt_size);

drivers/gpu/drm/xe/xe_tile_sriov_vf.h

15

u64 xe_tile_sriov_vf_ggtt_base(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile_sriov_vf.h

16

void xe_tile_sriov_vf_ggtt_base_store(struct xe_tile *tile, u64 ggtt_size);

drivers/gpu/drm/xe/xe_tile_sriov_vf.h

17

u64 xe_tile_sriov_vf_lmem(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile_sriov_vf.h

18

void xe_tile_sriov_vf_lmem_store(struct xe_tile *tile, u64 lmem_size);

drivers/gpu/drm/xe/xe_tile_sysfs.c

27

struct xe_tile *tile = arg;

drivers/gpu/drm/xe/xe_tile_sysfs.c

29

kobject_put(tile->sysfs);

drivers/gpu/drm/xe/xe_tile_sysfs.c

32

int xe_tile_sysfs_init(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_tile_sysfs.c

34

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_tile_sysfs.c

44

kt->tile = tile;

drivers/gpu/drm/xe/xe_tile_sysfs.c

46

err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id);

drivers/gpu/drm/xe/xe_tile_sysfs.c

50

tile->sysfs = &kt->base;

drivers/gpu/drm/xe/xe_tile_sysfs.c

52

err = xe_vram_freq_sysfs_init(tile);

drivers/gpu/drm/xe/xe_tile_sysfs.c

56

return devm_add_action_or_reset(xe->drm.dev, tile_sysfs_fini, tile);

drivers/gpu/drm/xe/xe_tile_sysfs.h

11

int xe_tile_sysfs_init(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_tile_sysfs.h

16

return container_of(kobj, struct kobj_tile, base)->tile;

drivers/gpu/drm/xe/xe_tile_sysfs_types.h

24

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_tlb_inval.c

529

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_tlb_inval.c

538

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_tlb_inval.c

542

xe_tlb_inval_fence_init(&tile->primary_gt->tlb_inval,

drivers/gpu/drm/xe/xe_tlb_inval.c

545

err = xe_tlb_inval_range(&tile->primary_gt->tlb_inval,

drivers/gpu/drm/xe/xe_tlb_inval.c

552

if (!tile->media_gt)

drivers/gpu/drm/xe/xe_tlb_inval.c

555

xe_tlb_inval_fence_init(&tile->media_gt->tlb_inval,

drivers/gpu/drm/xe/xe_tlb_inval.c

558

err = xe_tlb_inval_range(&tile->media_gt->tlb_inval,

drivers/gpu/drm/xe/xe_trace.h

25

#define __dev_name_tile(tile) __dev_name_xe(tile_to_xe((tile)))

drivers/gpu/drm/xe/xe_trace.h

381

__string(dev, __dev_name_tile(mmio->tile))

drivers/gpu/drm/xe/xe_ttm_vram_mgr.c

355

struct xe_tile *tile = &xe->tiles[res->mem_type - XE_PL_VRAM0];

drivers/gpu/drm/xe/xe_ttm_vram_mgr.c

393

phys_addr_t phys = cursor.start + xe_vram_region_io_start(tile->mem.vram);

drivers/gpu/drm/xe/xe_uc_fw.c

805

struct xe_tile *tile = gt_to_tile(gt);

drivers/gpu/drm/xe/xe_uc_fw.c

809

obj = xe_managed_bo_create_from_data(xe, tile, data, size, flags);

drivers/gpu/drm/xe/xe_vm.c

1007

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1009

vops.pt_update_ops[tile->id].q =

drivers/gpu/drm/xe/xe_vm.c

1010

xe_migrate_exec_queue(tile->migrate);

drivers/gpu/drm/xe/xe_vm.c

1074

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

1110

for_each_tile(tile, vm->xe, id)

drivers/gpu/drm/xe/xe_vm.c

1535

static int xe_vm_create_scratch(struct xe_device *xe, struct xe_tile *tile,

drivers/gpu/drm/xe/xe_vm.c

1538

u8 id = tile->id;

drivers/gpu/drm/xe/xe_vm.c

1542

vm->scratch_pt[id][i] = xe_pt_create(vm, tile, i, exec);

drivers/gpu/drm/xe/xe_vm.c

1549

xe_pt_populate_empty(tile, vm, vm->scratch_pt[id][i]);

drivers/gpu/drm/xe/xe_vm.c

1558

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

1564

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1578

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

1583

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1612

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

1673

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.c

1714

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1716

tile->id != XE_VM_FLAG_TILE_ID(flags))

drivers/gpu/drm/xe/xe_vm.c

1719

vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level,

drivers/gpu/drm/xe/xe_vm.c

1734

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1738

err = xe_vm_create_scratch(xe, tile, vm, &exec);

drivers/gpu/drm/xe/xe_vm.c

1758

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1762

xe_pt_populate_empty(tile, vm, vm->pt_root[id]);

drivers/gpu/drm/xe/xe_vm.c

1770

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1780

q = xe_exec_queue_create_bind(xe, tile, vm, create_flags, 0);

drivers/gpu/drm/xe/xe_vm.c

1818

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.c

1844

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

1854

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.c

1875

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

1893

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1904

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vm.c

1976

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.c

1987

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

2001

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.c

2035

u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)

drivers/gpu/drm/xe/xe_vm.c

2037

return vm->pt_ops->pde_encode_bo(vm->pt_root[tile->id]->bo, 0);

drivers/gpu/drm/xe/xe_vm.c

2490

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

2506

for_each_tile(tile, vm->xe, id)

drivers/gpu/drm/xe/xe_vm.c

2516

tile = &vm->xe->tiles[region_to_mem_type[prefetch_region] -

drivers/gpu/drm/xe/xe_vm.c

2518

dpagemap = xe_tile_local_pagemap(tile);

drivers/gpu/drm/xe/xe_vm.c

2770

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

2776

for_each_tile(tile, vm->xe, id)

drivers/gpu/drm/xe/xe_vm.c

3369

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

3373

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

3395

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

3406

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

3426

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

3430

err = xe_pt_update_ops_prepare(tile, vops);

drivers/gpu/drm/xe/xe_vm.c

3439

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

3440

struct xe_exec_queue *q = vops->pt_update_ops[tile->id].q;

drivers/gpu/drm/xe/xe_vm.c

3446

fence = xe_pt_update_ops_run(tile, vops);

drivers/gpu/drm/xe/xe_vm.c

3455

xe_migrate_job_lock(tile->migrate, q);

drivers/gpu/drm/xe/xe_vm.c

3459

xe_migrate_job_unlock(tile->migrate, q);

drivers/gpu/drm/xe/xe_vm.c

3467

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

3471

xe_pt_update_ops_fini(tile, vops);

drivers/gpu/drm/xe/xe_vm.c

3477

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

3481

xe_pt_update_ops_abort(tile, vops);

drivers/gpu/drm/xe/xe_vm.c

4347

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

4381

for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.c

4382

if (xe_pt_zap_ptes(tile, vma))

drivers/gpu/drm/xe/xe_vm.c

823

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

833

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

835

vops.pt_update_ops[tile->id].q =

drivers/gpu/drm/xe/xe_vm.c

836

xe_migrate_exec_queue(tile->migrate);

drivers/gpu/drm/xe/xe_vm.c

913

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.c

924

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm.c

926

vops.pt_update_ops[tile->id].q =

drivers/gpu/drm/xe/xe_vm.c

927

xe_migrate_exec_queue(tile->migrate);

drivers/gpu/drm/xe/xe_vm.c

995

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm.h

204

u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile);

drivers/gpu/drm/xe/xe_vm.h

435

#define xe_vm_has_valid_gpu_mapping(tile, tile_present, tile_invalidated) \

drivers/gpu/drm/xe/xe_vm.h

436

((READ_ONCE(tile_present) & ~READ_ONCE(tile_invalidated)) & BIT((tile)->id))

drivers/gpu/drm/xe/xe_vm_madvise.c

277

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vm_madvise.c

298

for_each_tile(tile, vm->xe, id) {

drivers/gpu/drm/xe/xe_vm_madvise.c

299

if (xe_pt_zap_ptes(tile, vma)) {

drivers/gpu/drm/xe/xe_vm_types.h

264

#define XE_VM_FLAG_SET_TILE_ID(tile) FIELD_PREP(GENMASK(7, 6), (tile)->id)

drivers/gpu/drm/xe/xe_vram.c

127

static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,

drivers/gpu/drm/xe/xe_vram.c

130

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_vram.c

131

struct xe_gt *gt = tile->primary_gt;

drivers/gpu/drm/xe/xe_vram.c

141

for_each_if(t->id < tile->id)

drivers/gpu/drm/xe/xe_vram.c

144

*tile_size = xe_tile_sriov_vf_lmem(tile);

drivers/gpu/drm/xe/xe_vram.c

156

reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));

drivers/gpu/drm/xe/xe_vram.c

168

offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);

drivers/gpu/drm/xe/xe_vram.c

180

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vram.c

185

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vram.c

186

tile->mem.vram->mapping = NULL;

drivers/gpu/drm/xe/xe_vram.c

187

if (tile->mem.kernel_vram)

drivers/gpu/drm/xe/xe_vram.c

188

tile->mem.kernel_vram->mapping = NULL;

drivers/gpu/drm/xe/xe_vram.c

284

struct xe_tile *tile;

drivers/gpu/drm/xe/xe_vram.c

302

for_each_tile(tile, xe, id) {

drivers/gpu/drm/xe/xe_vram.c

307

err = tile_vram_size(tile, &usable_size, &region_size, &tile_offset);

drivers/gpu/drm/xe/xe_vram.c

314

err = vram_region_init(xe, tile->mem.vram, &lmem_bar, tile_offset, usable_size,

drivers/gpu/drm/xe/xe_vram.c

324

remain_io_size -= min_t(u64, tile->mem.vram->actual_physical_size, remain_io_size);

drivers/gpu/drm/xe/xe_vram_freq.c

103

int xe_vram_freq_sysfs_init(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_vram_freq.c

105

struct xe_device *xe = tile_to_xe(tile);

drivers/gpu/drm/xe/xe_vram_freq.c

112

kobj = kobject_create_and_add("memory", tile->sysfs);

drivers/gpu/drm/xe/xe_vram_freq.c

35

struct xe_tile *tile = dev_to_tile(dev);

drivers/gpu/drm/xe/xe_vram_freq.c

43

err = xe_pcode_read(tile, mbox, &val, NULL);

drivers/gpu/drm/xe/xe_vram_freq.c

57

struct xe_tile *tile = dev_to_tile(dev);

drivers/gpu/drm/xe/xe_vram_freq.c

65

err = xe_pcode_read(tile, mbox, &val, NULL);

drivers/gpu/drm/xe/xe_vram_freq.h

11

int xe_vram_freq_sysfs_init(struct xe_tile *tile);

drivers/gpu/drm/xe/xe_wa.c

1020

void xe_wa_apply_tile_workarounds(struct xe_tile *tile)

drivers/gpu/drm/xe/xe_wa.c

1022

struct xe_mmio *mmio = &tile->mmio;

drivers/gpu/drm/xe/xe_wa.c

1024

if (IS_SRIOV_VF(tile->xe))

drivers/gpu/drm/xe/xe_wa.c

1027

if (XE_DEVICE_WA(tile->xe, 22010954014))

drivers/gpu/drm/xe/xe_wa.h

23

void xe_wa_apply_tile_workarounds(struct xe_tile *tile);

drivers/gpu/ipu-v3/ipu-image-convert.c

1012

image->tile[tile].offset = y_off;

drivers/gpu/ipu-v3/ipu-image-convert.c

1013

image->tile[tile].u_off = u_off;

drivers/gpu/ipu-v3/ipu-image-convert.c

1014

image->tile[tile++].v_off = v_off;

drivers/gpu/ipu-v3/ipu-image-convert.c

1038

unsigned int row, col, tile = 0;

drivers/gpu/ipu-v3/ipu-image-convert.c

1047

row_off = image->tile[tile].top * stride;

drivers/gpu/ipu-v3/ipu-image-convert.c

1050

col_off = (image->tile[tile].left * bpp) >> 3;

drivers/gpu/ipu-v3/ipu-image-convert.c

1054

image->tile[tile].offset = offset;

drivers/gpu/ipu-v3/ipu-image-convert.c

1055

image->tile[tile].u_off = 0;

drivers/gpu/ipu-v3/ipu-image-convert.c

1056

image->tile[tile++].v_off = 0;

drivers/gpu/ipu-v3/ipu-image-convert.c

1125

in_tile = &ctx->in.tile[tile_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

1126

out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]];

drivers/gpu/ipu-v3/ipu-image-convert.c

1160

in_tile = &ctx->in.tile[tile_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

1161

out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]];

drivers/gpu/ipu-v3/ipu-image-convert.c

1182

in_tile = &ctx->in.tile[tile_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

1183

out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]];

drivers/gpu/ipu-v3/ipu-image-convert.c

1217

in_tile = &ctx->in.tile[tile_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

1218

out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]];

drivers/gpu/ipu-v3/ipu-image-convert.c

126

struct ipu_image_tile tile[MAX_TILES];

drivers/gpu/ipu-v3/ipu-image-convert.c

1280

unsigned int tile)

drivers/gpu/ipu-v3/ipu-image-convert.c

1290

tile_idx[0] = ctx->out_tile_map[tile];

drivers/gpu/ipu-v3/ipu-image-convert.c

1293

tile_idx[0] = tile;

drivers/gpu/ipu-v3/ipu-image-convert.c

1298

width = image->tile[tile_idx[0]].height;

drivers/gpu/ipu-v3/ipu-image-convert.c

1299

height = image->tile[tile_idx[0]].width;

drivers/gpu/ipu-v3/ipu-image-convert.c

1300

stride = image->tile[tile_idx[0]].rot_stride;

drivers/gpu/ipu-v3/ipu-image-convert.c

1305

width = image->tile[tile_idx[0]].width;

drivers/gpu/ipu-v3/ipu-image-convert.c

1306

height = image->tile[tile_idx[0]].height;

drivers/gpu/ipu-v3/ipu-image-convert.c

1309

image->tile[tile_idx[0]].offset;

drivers/gpu/ipu-v3/ipu-image-convert.c

1312

image->tile[tile_idx[1]].offset;

drivers/gpu/ipu-v3/ipu-image-convert.c

1325

tile_image.u_offset = image->tile[tile_idx[0]].u_off;

drivers/gpu/ipu-v3/ipu-image-convert.c

1326

tile_image.v_offset = image->tile[tile_idx[0]].v_off;

drivers/gpu/ipu-v3/ipu-image-convert.c

1365

static int convert_start(struct ipu_image_convert_run *run, unsigned int tile)

drivers/gpu/ipu-v3/ipu-image-convert.c

1372

unsigned int dst_tile = ctx->out_tile_map[tile];

drivers/gpu/ipu-v3/ipu-image-convert.c

1379

__func__, chan->ic_task, ctx, run, tile, dst_tile);

drivers/gpu/ipu-v3/ipu-image-convert.c

1386

dest_width = d_image->tile[dst_tile].height;

drivers/gpu/ipu-v3/ipu-image-convert.c

1387

dest_height = d_image->tile[dst_tile].width;

drivers/gpu/ipu-v3/ipu-image-convert.c

1389

dest_width = d_image->tile[dst_tile].width;

drivers/gpu/ipu-v3/ipu-image-convert.c

1390

dest_height = d_image->tile[dst_tile].height;

drivers/gpu/ipu-v3/ipu-image-convert.c

1393

row = tile / s_image->num_cols;

drivers/gpu/ipu-v3/ipu-image-convert.c

1394

col = tile % s_image->num_cols;

drivers/gpu/ipu-v3/ipu-image-convert.c

1402

__func__, s_image->tile[tile].width,

drivers/gpu/ipu-v3/ipu-image-convert.c

1403

s_image->tile[tile].height, dest_width, dest_height, rsc);

drivers/gpu/ipu-v3/ipu-image-convert.c

1407

s_image->tile[tile].width,

drivers/gpu/ipu-v3/ipu-image-convert.c

1408

s_image->tile[tile].height,

drivers/gpu/ipu-v3/ipu-image-convert.c

1419

IPU_ROTATE_NONE, false, tile);

drivers/gpu/ipu-v3/ipu-image-convert.c

1424

IPU_ROTATE_NONE, true, tile);

drivers/gpu/ipu-v3/ipu-image-convert.c

1428

ctx->rot_mode, true, tile);

drivers/gpu/ipu-v3/ipu-image-convert.c

1432

IPU_ROTATE_NONE, false, tile);

drivers/gpu/ipu-v3/ipu-image-convert.c

1439

ctx->rot_mode, false, tile);

drivers/gpu/ipu-v3/ipu-image-convert.c

1609

ctx->in.tile[cur_tile].width != ctx->in.tile[next_tile].width ||

drivers/gpu/ipu-v3/ipu-image-convert.c

1610

ctx->in.tile[cur_tile].height != ctx->in.tile[next_tile].height ||

drivers/gpu/ipu-v3/ipu-image-convert.c

1611

ctx->out.tile[cur_tile].width != ctx->out.tile[next_tile].width ||

drivers/gpu/ipu-v3/ipu-image-convert.c

1612

ctx->out.tile[cur_tile].height != ctx->out.tile[next_tile].height)

drivers/gpu/ipu-v3/ipu-image-convert.c

1665

src_tile = &s_image->tile[ctx->next_tile];

drivers/gpu/ipu-v3/ipu-image-convert.c

1667

dst_tile = &d_image->tile[dst_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

1689

src_tile = &s_image->tile[ctx->next_tile + 1];

drivers/gpu/ipu-v3/ipu-image-convert.c

1691

dst_tile = &d_image->tile[dst_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

2175

if (ctx->in.tile[i].width != ctx->in.tile[0].width ||

drivers/gpu/ipu-v3/ipu-image-convert.c

2176

ctx->in.tile[i].height != ctx->in.tile[0].height ||

drivers/gpu/ipu-v3/ipu-image-convert.c

2177

ctx->out.tile[i].width != ctx->out.tile[0].width ||

drivers/gpu/ipu-v3/ipu-image-convert.c

2178

ctx->out.tile[i].height != ctx->out.tile[0].height) {

drivers/gpu/ipu-v3/ipu-image-convert.c

2197

unsigned long intermediate_size = d_image->tile[0].size;

drivers/gpu/ipu-v3/ipu-image-convert.c

2200

if (d_image->tile[i].size > intermediate_size)

drivers/gpu/ipu-v3/ipu-image-convert.c

2201

intermediate_size = d_image->tile[i].size;

drivers/gpu/ipu-v3/ipu-image-convert.c

663

in_tile = &in->tile[tile_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

664

out_tile = &out->tile[ctx->out_tile_map[tile_idx]];

drivers/gpu/ipu-v3/ipu-image-convert.c

695

in_tile = &in->tile[tile_idx];

drivers/gpu/ipu-v3/ipu-image-convert.c

696

out_tile = &out->tile[ctx->out_tile_map[tile_idx]];

drivers/gpu/ipu-v3/ipu-image-convert.c

856

struct ipu_image_tile *tile;

drivers/gpu/ipu-v3/ipu-image-convert.c

861

tile = &image->tile[ctx->out_tile_map[i]];

drivers/gpu/ipu-v3/ipu-image-convert.c

863

tile = &image->tile[i];

drivers/gpu/ipu-v3/ipu-image-convert.c

865

tile->size = ((tile->height * image->fmt->bpp) >> 3) *

drivers/gpu/ipu-v3/ipu-image-convert.c

866

tile->width;

drivers/gpu/ipu-v3/ipu-image-convert.c

869

tile->stride = tile->width;

drivers/gpu/ipu-v3/ipu-image-convert.c

870

tile->rot_stride = tile->height;

drivers/gpu/ipu-v3/ipu-image-convert.c

872

tile->stride =

drivers/gpu/ipu-v3/ipu-image-convert.c

873

(image->fmt->bpp * tile->width) >> 3;

drivers/gpu/ipu-v3/ipu-image-convert.c

874

tile->rot_stride =

drivers/gpu/ipu-v3/ipu-image-convert.c

875

(image->fmt->bpp * tile->height) >> 3;

drivers/gpu/ipu-v3/ipu-image-convert.c

883

tile->width, tile->height, tile->left, tile->top);

drivers/gpu/ipu-v3/ipu-image-convert.c

885

if (!tile->width || tile->width > max_width ||

drivers/gpu/ipu-v3/ipu-image-convert.c

886

!tile->height || tile->height > max_height) {

drivers/gpu/ipu-v3/ipu-image-convert.c

889

"output", tile->width, tile->height);

drivers/gpu/ipu-v3/ipu-image-convert.c

959

unsigned int row, col, tile = 0;

drivers/gpu/ipu-v3/ipu-image-convert.c

963

ctx->out_tile_map[tile] =

drivers/gpu/ipu-v3/ipu-image-convert.c

965

tile++;

drivers/gpu/ipu-v3/ipu-image-convert.c

976

unsigned int row, col, tile = 0;

drivers/gpu/ipu-v3/ipu-image-convert.c

994

top = image->tile[tile].top;

drivers/gpu/ipu-v3/ipu-image-convert.c

999

y_col_off = image->tile[tile].left;

drivers/hid/hid-picolcd_fb.c

114

hid_set_field(report1->field[0], 4, 0xb8 | tile);

drivers/hid/hid-picolcd_fb.c

127

tdata = vbitmap + (tile * 4 + chip) * 64;

drivers/hid/hid-picolcd_fb.c

142

int chip, int tile)

drivers/hid/hid-picolcd_fb.c

146

u8 *vdata = vbitmap + (tile * 4 + chip) * 64;

drivers/hid/hid-picolcd_fb.c

150

const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32;

drivers/hid/hid-picolcd_fb.c

158

const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8;

drivers/hid/hid-picolcd_fb.c

227

int chip, tile, n;

drivers/hid/hid-picolcd_fb.c

248

for (tile = 0; tile < 8; tile++) {

drivers/hid/hid-picolcd_fb.c

251

fbdata->bpp, chip, tile))

drivers/hid/hid-picolcd_fb.c

269

fbdata->vbitmap, chip, tile))

drivers/hid/hid-picolcd_fb.c

91

int chip, int tile)

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1004

if (instance->tile.va)

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1005

mtk_vcodec_mem_free(ctx, &instance->tile);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1007

instance->tile.size = AV1_TILE_BUF_SIZE * V4L2_AV1_MAX_TILE_COUNT;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1008

ret = mtk_vcodec_mem_alloc(ctx, &instance->tile);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1038

if (instance->tile.va)

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1039

mtk_vcodec_mem_free(ctx, &instance->tile);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1292

struct vdec_av1_slice_tile *tile = &frame->uh.tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1296

tile->tile_cols = ctrl_tile->tile_cols;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1297

tile->tile_rows = ctrl_tile->tile_rows;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1298

tile->context_update_tile_id = ctrl_tile->context_update_tile_id;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1299

tile->uniform_tile_spacing_flag =

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1302

for (i = 0; i < tile->tile_cols + 1; i++)

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1303

tile->mi_col_starts[i] =

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1306

for (i = 0; i < tile->tile_rows + 1; i++)

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1307

tile->mi_row_starts[i] =

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1393

struct vdec_av1_slice_tile *tile = &uh->tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1405

tile_group->num_tiles = tile->tile_cols * tile->tile_rows;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1415

if (i != ctrl_tge[i].tile_row * vsi->frame.uh.tile.tile_cols +

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1419

vsi->frame.uh.tile.tile_rows);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1630

vsi->tile.buf = instance->tile.dma_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1631

vsi->tile.size = instance->tile.size;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1632

memcpy(lat_buf->tile_addr.va, instance->tile.va, 64 * instance->tile_group.num_tiles);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1662

struct vdec_av1_slice_tile *tile = &uh->tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1668

u32 *tile_info_buf = instance->tile.va;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1677

tile_row = tile_num / tile->tile_cols;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1678

tile_col = tile_num % tile->tile_cols;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1690

(tile->mi_col_starts[tile_col + 1] - tile->mi_col_starts[tile_col] - 1) &

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1693

(tile->mi_row_starts[tile_row + 1] - tile->mi_row_starts[tile_row] - 1) &

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1699

if (tile_num == tile->context_update_tile_id &&

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1835

vsi->tile.dma_addr = lat_buf->tile_addr.dma_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

1836

vsi->tile.size = lat_buf->tile_addr.size;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

490

struct vdec_av1_slice_tile tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

662

struct vdec_av1_slice_mem tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c

718

struct mtk_vcodec_mem tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1113

tb = instance->tile.va;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1750

vsi->tile.dma_addr = instance->tile.dma_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

1751

vsi->tile.size = instance->tile.size;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

361

struct vdec_vp9_slice_mem tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

473

struct mtk_vcodec_mem tile;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

608

if (!instance->tile.va) {

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

609

instance->tile.size = VP9_TILE_BUF_SIZE;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

610

if (mtk_vcodec_mem_alloc(ctx, &instance->tile))

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

647

if (instance->tile.va)

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

648

mtk_vcodec_mem_free(ctx, &instance->tile);

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

997

vsi->tile.dma_addr = instance->tile.dma_addr;

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c

998

vsi->tile.size = instance->tile.size;

drivers/pinctrl/qcom/pinctrl-msm.c

107

return readl(pctrl->regs[g->tile] + reg);

drivers/pinctrl/qcom/pinctrl-msm.c

115

writel(val, pctrl->regs[g->tile] + reg);

drivers/pinctrl/qcom/pinctrl-msm.c

89

return readl(pctrl->regs[g->tile] + g->name##_reg); \

drivers/pinctrl/qcom/pinctrl-msm.c

94

writel(val, pctrl->regs[g->tile] + g->name##_reg); \

drivers/pinctrl/qcom/pinctrl-msm.h

101

unsigned int tile:2;

drivers/pinctrl/qcom/pinctrl-qcs404.c

46

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-qcs404.c

72

.tile = SOUTH, \

drivers/pinctrl/qcom/pinctrl-qcs615.c

46

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-qcs615.c

72

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-qcs615.c

97

.tile = WEST, \

drivers/pinctrl/qcom/pinctrl-sc7180.c

44

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sc7180.c

70

.tile = SOUTH, \

drivers/pinctrl/qcom/pinctrl-sc7180.c

95

.tile = SOUTH, \

drivers/pinctrl/qcom/pinctrl-sc8180x.c

117

.tile = SOUTH, \

drivers/pinctrl/qcom/pinctrl-sc8180x.c

63

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sc8180x.c

92

.tile = EAST, \

drivers/pinctrl/qcom/pinctrl-sdm660.c

49

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sdm660.c

75

.tile = NORTH, \

drivers/pinctrl/qcom/pinctrl-sm6115.c

46

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm6115.c

74

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm6115.c

99

.tile = WEST, \

drivers/pinctrl/qcom/pinctrl-sm6125.c

43

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm6125.c

69

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm6125.c

94

.tile = WEST, \

drivers/pinctrl/qcom/pinctrl-sm7150.c

101

.tile = WEST, \

drivers/pinctrl/qcom/pinctrl-sm7150.c

50

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm7150.c

76

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm8150.c

46

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm8150.c

72

.tile = NORTH, \

drivers/pinctrl/qcom/pinctrl-sm8150.c

97

.tile = SOUTH, \

drivers/pinctrl/qcom/pinctrl-sm8250.c

100

.tile = SOUTH, \

drivers/pinctrl/qcom/pinctrl-sm8250.c

47

.tile = _tile, \

drivers/pinctrl/qcom/pinctrl-sm8250.c

75

.tile = NORTH, \

drivers/video/fbdev/cirrusfb.c

868

unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);

drivers/video/fbdev/cirrusfb.c

878

fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);

drivers/video/fbdev/gbefb.c

1002

u16 *tile;

drivers/video/fbdev/gbefb.c

1023

tile = &gbe_tiles.cpu[offset >> TILE_SHIFT];

drivers/video/fbdev/gbefb.c

1029

phys_addr = (((unsigned long) (*tile)) << TILE_SHIFT) + offset;

drivers/video/fbdev/gbefb.c

1042

tile++;

tools/testing/selftests/kvm/x86/amx_test.c

66

static inline void __tileloadd(void *tile)

tools/testing/selftests/kvm/x86/amx_test.c

69

: : "a"(tile), "d"(0));

tools/testing/selftests/kvm/x86/amx_test.c

72

static inline int tileloadd_safe(void *tile)

tools/testing/selftests/kvm/x86/amx_test.c

75

"a"(tile), "d"(0));