setscl
i2c->bit.setscl = amdgpu_i2c_set_clock;
bit->setscl = ast_ddc_algo_bit_data_setscl;
gpio->algo.setscl = set_clock;
chan->algo.setscl = set_clock;
chan->algo.setscl = set_clock;
vdac->bit_data.setscl = hibmc_ddc_setscl;
algo->setscl = set_clock;
li2c->bit.setscl = lsdc_gpio_i2c_set_scl;
bit->setscl = mgag200_ddc_algo_bit_data_setscl;
bit->setscl = nvkm_i2c_bus_setscl;
i2c->bit.setscl = set_clock;
setscl(adap, 0);
#define setscl(adap, val) adap->setscl(adap->data, val)
setscl(adap, 0);
setscl(adap, 1);
.setscl = ioc_setscl,
setscl(bit_data, 0);
setscl(bit_data, 1);
bit_data->setscl = i2c_gpio_setscl_val;
#define setscl(bd, val) ((bd)->setscl((bd)->data, val))
.setscl = hydra_bit_setscl,
.setscl = { 0x02, PORT_DATA, 0 },
.setscl = { 0x01, PORT_DATA, 1 },
line_set((struct parport *) data, state, &adapter_parm[type].setscl);
.setscl = parport_setscl,
struct lineop setscl;
.setscl = { 0x08, PORT_CTRL, 0 },
.setscl = { 0x01, PORT_DATA, 0 },
.setscl = { 0x08, PORT_CTRL, 1 },
.setscl = { 0x01, PORT_DATA, 1 },
.setscl = { 0x01, PORT_DATA, 1 },
.setscl = { 0x01, PORT_DATA, 1 },
.setscl = { 0x01, PORT_DATA, 1 },
pd->bit.setscl = simtec_i2c_setscl;
.setscl = i2c_versatile_setscl,
.setscl = bit_via_setscl,
bus->algo.setscl = hfi1_setscl;
.setscl = bttv_bit_setscl,
.setscl = cx18_setscl,
.setscl = cx8800_bit_setscl,
.setscl = vp3054_bit_setscl,
dev->i2c_bit.setscl = dm1105_setscl;
.setscl = ivtv_setscl_old,
pluto->i2c_bit.setscl = pluto_setscl;
dev->i2c_bit[0].setscl = smi_i2c0_setscl;
dev->i2c_bit[1].setscl = smi_i2c1_setscl;
.setscl = zoran_i2c_setscl,
.setscl = pita_setscl,
.setscl = igb_set_i2c_clk,
.setscl = falcon_setscl,
chan->algo.setscl = radeon_gpio_setscl;
algo_data->setscl(algo_data->data, 0);
algo_data->setscl(algo_data->data, 1);
algo_data->setscl(algo_data->data, 1);
algo_data->setscl(algo_data->data, 1);
algo_data->setscl(algo_data->data, 0);
algo_data->setscl(algo_data->data, 0);
algo_data->setscl(algo_data->data, 1);
cfb->ddc_algo.setscl = cyber2000fb_ddc_setscl;
cfb->i2c_algo.setscl = cyber2000fb_i2c_setscl;
par->ddc_algo.setscl = i740fb_ddc_setscl;
chan->algo.setscl(chan, 1);
chan->algo.setscl = i810i2c_setscl;
.setscl = matroxfb_gpio_setscl,
chan->algo.setscl = nvidia_gpio_setscl;
chan->algo.setscl = riva_gpio_setscl;
par->ddc_algo.setscl = s3fb_ddc_setscl;
chan->algo.setscl(chan, 1);
par->chan.algo.setscl = prosavage_gpio_setscl;
par->chan.algo.setscl = prosavage_gpio_setscl;
par->chan.algo.setscl = savage4_gpio_setscl;
chan->algo.setscl = tdfxfb_ddc_setscl;
chan->algo.setscl = tdfxfb_i2c_setscl;
par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
par->ddc_algo.setscl = tridentfb_ddc_setscl;
algo->setscl = via_i2c_setscl;
void (*setscl) (void *data, int state);