set_mask_bits
set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_ACT_MSK,
set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_INACT_MSK,
set_mask_bits(&data->generic_event_en, intrmask, regval);
set_mask_bits(&field_value, BMA400_INT_CONFIG1_S_TAP_MASK,
set_mask_bits(&field_value, BMA400_INT_CONFIG1_D_TAP_MASK,
set_mask_bits(&data->tap_event_en_bitmask, mask, field_value);
set_mask_bits(&field_value, BMI270_INT_MAP_DATA_DRDY_INT1_MSK,
set_mask_bits(&field_value, BMI270_INT_MAP_DATA_DRDY_INT2_MSK,
set_mask_bits(&data->feature_events, BMI323_FEAT_IO0_STP_CNT_MSK,
set_mask_bits(&value, mask, ext_data);
set_mask_bits(&data->feature_events, msk, field_value);
set_mask_bits(&data->feature_events, BMI323_FEAT_IO0_S_TAP_MSK,
set_mask_bits(&data->feature_events, BMI323_FEAT_IO0_D_TAP_MSK,
set_mask_bits(&mddev->sb_flags, 0,
set_mask_bits(&mddev->sb_flags, 0,
set_mask_bits(&mddev->sb_flags, 0,
set_mask_bits(&mddev->sb_flags, 0,
set_mask_bits(&mddev->sb_flags, 0,
set_mask_bits(&mddev->sb_flags, 0,
set_mask_bits(&mddev->sb_flags, 0,
set_mask_bits(&sh->state, ~(STRIPE_EXPAND_SYNC_FLAGS |
set_mask_bits(&write_val, mask, val);
set_mask_bits(&inode->vfs_inode.i_flags,
set_mask_bits(&get_fuse_inode(inode)->inval_mask, 0, mask);
set_mask_bits(&fi->inval_mask, STATX_BASIC_STATS, 0);
set_mask_bits(&fi->inval_mask, STATX_BTIME, 0);
set_mask_bits(&inode->i_flags, mask, flags);
set_mask_bits(&bh->b_state, clear_bits, 0);
set_mask_bits(&bh->b_state, clear_bits, 0);
set_mask_bits(&bh->b_state, clear_bits, set_bits);
#ifndef set_mask_bits
set_mask_bits(&folio->flags.f, LRU_GEN_MASK | BIT(PG_active), flags);
flags = set_mask_bits(&folio->flags.f, LRU_GEN_MASK, flags);
set_mask_bits(&new->flags.f, LRU_REFS_MASK, refs);
set_mask_bits(bitmap, mask, bits);
set_mask_bits(&worker->flags, 0,
set_mask_bits(&folio->flags.f, LRU_REFS_MASK, BIT(PG_referenced));
set_mask_bits(&folio->flags.f, LRU_REFS_FLAGS | BIT(PG_workingset), 0);
set_mask_bits(&folio->flags.f, LRU_REFS_MASK, BIT(PG_referenced));
set_mask_bits(&folio->flags.f, LRU_REFS_MASK, 0);
set_mask_bits(&folio->flags.f, LRU_REFS_FLAGS, BIT(PG_active));
set_mask_bits(&folio->flags.f, LRU_REFS_MASK, BIT(PG_referenced));
set_mask_bits(&folio->flags.f, LRU_REFS_FLAGS, BIT(PG_workingset));
set_mask_bits(&folio->flags.f, LRU_REFS_MASK, (refs - 1UL) << LRU_REFS_PGOFF);
old = set_mask_bits(&subflow->delegated_status, 0, set_bits);
status = set_mask_bits(&subflow->delegated_status, MPTCP_DELEGATE_ACTIONS_MASK, 0);
set_mask_bits(&tmp, mask, val);
set_mask_bits(&tmp, mask, val);
set_mask_bits(&tmp, mask, val);
set_mask_bits(&tmp, mask, val);
set_mask_bits(&tmp, mask, val);
set_mask_bits(&tmp, mask, val);